xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt8183-kukui.dtsi (revision cb7aa33ac6cd46a5434798e50363136e64f3ae98)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 *	   Erin Lo <erin.lo@mediatek.com>
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include "mt8183.dtsi"
11#include "mt6358.dtsi"
12
13/ {
14	aliases {
15		serial0 = &uart0;
16		mmc0 = &mmc0;
17		mmc1 = &mmc1;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	backlight_lcd0: backlight_lcd0 {
25		compatible = "pwm-backlight";
26		pwms = <&pwm0 0 500000>;
27		power-supply = <&bl_pp5000>;
28		enable-gpios = <&pio 176 0>;
29		brightness-levels = <0 1023>;
30		num-interpolated-steps = <1023>;
31		default-brightness-level = <576>;
32		status = "okay";
33	};
34
35	memory@40000000 {
36		device_type = "memory";
37		reg = <0 0x40000000 0 0x80000000>;
38	};
39
40	clk32k: oscillator1 {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <32768>;
44		clock-output-names = "clk32k";
45	};
46
47	it6505_pp18_reg: regulator0 {
48		compatible = "regulator-fixed";
49		regulator-name = "it6505_pp18";
50		regulator-min-microvolt = <1800000>;
51		regulator-max-microvolt = <1800000>;
52		gpio = <&pio 178 0>;
53		enable-active-high;
54	};
55
56	lcd_pp3300: regulator1 {
57		compatible = "regulator-fixed";
58		regulator-name = "lcd_pp3300";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61		regulator-always-on;
62		regulator-boot-on;
63	};
64
65	bl_pp5000: regulator2 {
66		compatible = "regulator-fixed";
67		regulator-name = "bl_pp5000";
68		regulator-min-microvolt = <5000000>;
69		regulator-max-microvolt = <5000000>;
70		regulator-always-on;
71		regulator-boot-on;
72	};
73
74	mmc1_fixed_power: regulator3 {
75		compatible = "regulator-fixed";
76		regulator-name = "mmc1_power";
77		regulator-min-microvolt = <3300000>;
78		regulator-max-microvolt = <3300000>;
79	};
80
81	mmc1_fixed_io: regulator4 {
82		compatible = "regulator-fixed";
83		regulator-name = "mmc1_io";
84		regulator-min-microvolt = <1800000>;
85		regulator-max-microvolt = <1800000>;
86	};
87
88	pp1800_alw: regulator5 {
89		compatible = "regulator-fixed";
90		regulator-name = "pp1800_alw";
91		regulator-always-on;
92		regulator-boot-on;
93		regulator-min-microvolt = <1800000>;
94		regulator-max-microvolt = <1800000>;
95	};
96
97	pp3300_alw: regulator6 {
98		compatible = "regulator-fixed";
99		regulator-name = "pp3300_alw";
100		regulator-always-on;
101		regulator-boot-on;
102		regulator-min-microvolt = <3300000>;
103		regulator-max-microvolt = <3300000>;
104	};
105
106	reserved_memory: reserved-memory {
107		#address-cells = <2>;
108		#size-cells = <2>;
109		ranges;
110
111		scp_mem_reserved: scp_mem_region {
112			compatible = "shared-dma-pool";
113			reg = <0 0x50000000 0 0x2900000>;
114			no-map;
115		};
116	};
117
118	sound: mt8183-sound {
119		mediatek,platform = <&afe>;
120		pinctrl-names = "default",
121				"aud_tdm_out_on",
122				"aud_tdm_out_off";
123		pinctrl-0 = <&aud_pins_default>;
124		pinctrl-1 = <&aud_pins_tdm_out_on>;
125		pinctrl-2 = <&aud_pins_tdm_out_off>;
126		status = "okay";
127	};
128
129	btsco: bt-sco {
130		compatible = "linux,bt-sco";
131	};
132
133	wifi_pwrseq: wifi-pwrseq {
134		compatible = "mmc-pwrseq-simple";
135		pinctrl-names = "default";
136		pinctrl-0 = <&wifi_pins_pwrseq>;
137
138		/* Toggle WIFI_ENABLE to reset the chip. */
139		reset-gpios = <&pio 119 1>;
140	};
141
142	wifi_wakeup: wifi-wakeup {
143		compatible = "gpio-keys";
144		pinctrl-names = "default";
145		pinctrl-0 = <&wifi_pins_wakeup>;
146
147		button-wowlan {
148			label = "Wake on WiFi";
149			gpios = <&pio 113 GPIO_ACTIVE_HIGH>;
150			linux,code = <KEY_WAKEUP>;
151			wakeup-source;
152		};
153	};
154
155	tboard_thermistor1: thermal-sensor1 {
156		compatible = "generic-adc-thermal";
157		#thermal-sensor-cells = <0>;
158		io-channels = <&auxadc 0>;
159		io-channel-names = "sensor-channel";
160		temperature-lookup-table = <    (-5000) 1553
161						0 1488
162						5000 1412
163						10000 1326
164						15000 1232
165						20000 1132
166						25000 1029
167						30000 925
168						35000 823
169						40000 726
170						45000 635
171						50000 552
172						55000 478
173						60000 411
174						65000 353
175						70000 303
176						75000 260
177						80000 222
178						85000 190
179						90000 163
180						95000 140
181						100000 121
182						105000 104
183						110000 90
184						115000 78
185						120000 67
186						125000 59>;
187	};
188
189	tboard_thermistor2: thermal-sensor2 {
190		compatible = "generic-adc-thermal";
191		#thermal-sensor-cells = <0>;
192		io-channels = <&auxadc 1>;
193		io-channel-names = "sensor-channel";
194		temperature-lookup-table = <    (-5000) 1553
195						0 1488
196						5000 1412
197						10000 1326
198						15000 1232
199						20000 1132
200						25000 1029
201						30000 925
202						35000 823
203						40000 726
204						45000 635
205						50000 552
206						55000 478
207						60000 411
208						65000 353
209						70000 303
210						75000 260
211						80000 222
212						85000 190
213						90000 163
214						95000 140
215						100000 121
216						105000 104
217						110000 90
218						115000 78
219						120000 67
220						125000 59>;
221	};
222};
223
224&auxadc {
225	status = "okay";
226};
227
228&cci {
229	proc-supply = <&mt6358_vproc12_reg>;
230};
231
232&cpu0 {
233	proc-supply = <&mt6358_vproc12_reg>;
234};
235
236&cpu1 {
237	proc-supply = <&mt6358_vproc12_reg>;
238};
239
240&cpu2 {
241	proc-supply = <&mt6358_vproc12_reg>;
242};
243
244&cpu3 {
245	proc-supply = <&mt6358_vproc12_reg>;
246};
247
248&cpu4 {
249	proc-supply = <&mt6358_vproc11_reg>;
250};
251
252&cpu5 {
253	proc-supply = <&mt6358_vproc11_reg>;
254};
255
256&cpu6 {
257	proc-supply = <&mt6358_vproc11_reg>;
258};
259
260&cpu7 {
261	proc-supply = <&mt6358_vproc11_reg>;
262};
263
264&dsi0 {
265	status = "okay";
266	#address-cells = <1>;
267	#size-cells = <0>;
268	panel: panel@0 {
269		/* compatible will be set in board dts */
270		reg = <0>;
271		enable-gpios = <&pio 45 0>;
272		pinctrl-names = "default";
273		pinctrl-0 = <&panel_pins_default>;
274		avdd-supply = <&ppvarn_lcd>;
275		avee-supply = <&ppvarp_lcd>;
276		pp1800-supply = <&pp1800_lcd>;
277		backlight = <&backlight_lcd0>;
278		rotation = <270>;
279		port {
280			panel_in: endpoint {
281				remote-endpoint = <&dsi_out>;
282			};
283		};
284	};
285
286	ports {
287		port {
288			dsi_out: endpoint {
289				remote-endpoint = <&panel_in>;
290			};
291		};
292	};
293};
294
295&gpu {
296	mali-supply = <&mt6358_vgpu_reg>;
297	sram-supply = <&mt6358_vsram_gpu_reg>;
298};
299
300&i2c0 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&i2c0_pins>;
303	status = "okay";
304	clock-frequency = <400000>;
305	#address-cells = <1>;
306	#size-cells = <0>;
307};
308
309&i2c1 {
310	pinctrl-names = "default";
311	pinctrl-0 = <&i2c1_pins>;
312	status = "okay";
313	clock-frequency = <100000>;
314};
315
316&i2c3 {
317	pinctrl-names = "default";
318	pinctrl-0 = <&i2c3_pins>;
319	status = "okay";
320	clock-frequency = <100000>;
321	#address-cells = <1>;
322	#size-cells = <0>;
323};
324
325&i2c5 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&i2c5_pins>;
328	status = "okay";
329	clock-frequency = <100000>;
330	#address-cells = <1>;
331	#size-cells = <0>;
332};
333
334&i2c6 {
335	pinctrl-names = "default";
336	pinctrl-0 = <&i2c6_pins>;
337	status = "okay";
338	clock-frequency = <100000>;
339};
340
341&mipi_tx0 {
342	status = "okay";
343};
344
345&mmc0 {
346	status = "okay";
347	pinctrl-names = "default", "state_uhs";
348	pinctrl-0 = <&mmc0_pins_default>;
349	pinctrl-1 = <&mmc0_pins_uhs>;
350	bus-width = <8>;
351	max-frequency = <200000000>;
352	cap-mmc-highspeed;
353	mmc-hs200-1_8v;
354	mmc-hs400-1_8v;
355	cap-mmc-hw-reset;
356	no-sdio;
357	no-sd;
358	hs400-ds-delay = <0x12814>;
359	vmmc-supply = <&mt6358_vemc_reg>;
360	vqmmc-supply = <&mt6358_vio18_reg>;
361	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
362	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
363	non-removable;
364};
365
366&mmc1 {
367	status = "okay";
368	pinctrl-names = "default", "state_uhs";
369	pinctrl-0 = <&mmc1_pins_default>;
370	pinctrl-1 = <&mmc1_pins_uhs>;
371	vmmc-supply = <&mmc1_fixed_power>;
372	vqmmc-supply = <&mmc1_fixed_io>;
373	mmc-pwrseq = <&wifi_pwrseq>;
374	bus-width = <4>;
375	max-frequency = <200000000>;
376	cap-sd-highspeed;
377	sd-uhs-sdr50;
378	sd-uhs-sdr104;
379	keep-power-in-suspend;
380	wakeup-source;
381	cap-sdio-irq;
382	non-removable;
383	no-mmc;
384	no-sd;
385	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>;
386	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
387	#address-cells = <1>;
388	#size-cells = <0>;
389
390	qca_wifi: qca-wifi@1 {
391		compatible = "qcom,ath10k";
392		reg = <1>;
393	};
394};
395
396&mt6358_vdram2_reg {
397	regulator-always-on;
398};
399
400&mt6358codec {
401	Avdd-supply = <&mt6358_vaud28_reg>;
402};
403
404&mt6358_vsim1_reg {
405	regulator-min-microvolt = <2700000>;
406	regulator-max-microvolt = <2700000>;
407};
408
409&mt6358_vsim2_reg {
410	regulator-min-microvolt = <2700000>;
411	regulator-max-microvolt = <2700000>;
412};
413
414&pio {
415	aud_pins_default: audiopins {
416		pins_bus {
417			pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
418				<PINMUX_GPIO98__FUNC_I2S2_BCK>,
419				<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
420				<PINMUX_GPIO102__FUNC_I2S2_DI>,
421				<PINMUX_GPIO3__FUNC_I2S3_DO>, /*i2s to da7219/max98357*/
422				<PINMUX_GPIO89__FUNC_I2S5_BCK>,
423				<PINMUX_GPIO90__FUNC_I2S5_LRCK>,
424				<PINMUX_GPIO91__FUNC_I2S5_DO>,
425				<PINMUX_GPIO174__FUNC_I2S0_DI>, /*i2s to wifi/bt*/
426				<PINMUX_GPIO136__FUNC_AUD_CLK_MOSI>,
427				<PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI>,
428				<PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0>,
429				<PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1>,
430				<PINMUX_GPIO140__FUNC_AUD_CLK_MISO>,
431				<PINMUX_GPIO141__FUNC_AUD_SYNC_MISO>,
432				<PINMUX_GPIO142__FUNC_AUD_DAT_MISO0>,
433				<PINMUX_GPIO143__FUNC_AUD_DAT_MISO1>; /*mtkaif3.0*/
434		};
435	};
436
437	aud_pins_tdm_out_on: audiotdmouton {
438		pins_bus {
439			pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
440				<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
441				<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
442				<PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>,
443				<PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>,
444				<PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/
445			drive-strength = <MTK_DRIVE_6mA>;
446		};
447	};
448
449	aud_pins_tdm_out_off: audiotdmoutoff {
450		pins_bus {
451			pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
452				<PINMUX_GPIO170__FUNC_GPIO170>,
453				<PINMUX_GPIO171__FUNC_GPIO171>,
454				<PINMUX_GPIO172__FUNC_GPIO172>,
455				<PINMUX_GPIO173__FUNC_GPIO173>,
456				<PINMUX_GPIO10__FUNC_GPIO10>;
457			input-enable;
458			bias-pull-down;
459			drive-strength = <MTK_DRIVE_2mA>;
460		};
461	};
462
463	bt_pins: bt-pins {
464		pins_bt_en {
465			pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
466			output-low;
467		};
468	};
469
470	ec_ap_int_odl: ec_ap_int_odl {
471		pins1 {
472			pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
473			input-enable;
474			bias-pull-up;
475		};
476	};
477
478	h1_int_od_l: h1_int_od_l {
479		pins1 {
480			pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
481			input-enable;
482		};
483	};
484
485	i2c0_pins: i2c0 {
486		pins_bus {
487			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
488				 <PINMUX_GPIO83__FUNC_SCL0>;
489			mediatek,pull-up-adv = <3>;
490			mediatek,drive-strength-adv = <00>;
491		};
492	};
493
494	i2c1_pins: i2c1 {
495		pins_bus {
496			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
497				 <PINMUX_GPIO84__FUNC_SCL1>;
498			mediatek,pull-up-adv = <3>;
499			mediatek,drive-strength-adv = <00>;
500		};
501	};
502
503	i2c2_pins: i2c2 {
504		pins_bus {
505			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
506				 <PINMUX_GPIO104__FUNC_SDA2>;
507			bias-disable;
508			mediatek,drive-strength-adv = <00>;
509		};
510	};
511
512	i2c3_pins: i2c3 {
513		pins_bus {
514			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
515				 <PINMUX_GPIO51__FUNC_SDA3>;
516			mediatek,pull-up-adv = <3>;
517			mediatek,drive-strength-adv = <00>;
518		};
519	};
520
521	i2c4_pins: i2c4 {
522		pins_bus {
523			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
524				 <PINMUX_GPIO106__FUNC_SDA4>;
525			bias-disable;
526			mediatek,drive-strength-adv = <00>;
527		};
528	};
529
530	i2c5_pins: i2c5 {
531		pins_bus {
532			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
533				 <PINMUX_GPIO49__FUNC_SDA5>;
534			mediatek,pull-up-adv = <3>;
535			mediatek,drive-strength-adv = <00>;
536		};
537	};
538
539	i2c6_pins: i2c6 {
540		pins_bus {
541			pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
542				 <PINMUX_GPIO12__FUNC_SDA6>;
543			bias-disable;
544		};
545	};
546
547	mmc0_pins_default: mmc0-pins-default {
548		pins_cmd_dat {
549			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
550				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
551				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
552				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
553				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
554				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
555				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
556				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
557				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
558			input-enable;
559			drive-strength = <MTK_DRIVE_14mA>;
560			mediatek,pull-up-adv = <01>;
561		};
562
563		pins_clk {
564			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
565			drive-strength = <MTK_DRIVE_14mA>;
566			mediatek,pull-down-adv = <10>;
567		};
568
569		pins_rst {
570			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
571			drive-strength = <MTK_DRIVE_14mA>;
572			mediatek,pull-down-adv = <01>;
573		};
574	};
575
576	mmc0_pins_uhs: mmc0-pins-uhs {
577		pins_cmd_dat {
578			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
579				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
580				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
581				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
582				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
583				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
584				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
585				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
586				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
587			input-enable;
588			drive-strength = <MTK_DRIVE_14mA>;
589			mediatek,pull-up-adv = <01>;
590		};
591
592		pins_clk {
593			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
594			drive-strength = <MTK_DRIVE_14mA>;
595			mediatek,pull-down-adv = <10>;
596		};
597
598		pins_ds {
599			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
600			drive-strength = <MTK_DRIVE_14mA>;
601			mediatek,pull-down-adv = <10>;
602		};
603
604		pins_rst {
605			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
606			drive-strength = <MTK_DRIVE_14mA>;
607			mediatek,pull-up-adv = <01>;
608		};
609	};
610
611	mmc1_pins_default: mmc1-pins-default {
612		pins_cmd_dat {
613			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
614				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
615				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
616				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
617				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
618			input-enable;
619			mediatek,pull-up-adv = <10>;
620		};
621
622		pins_clk {
623			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
624			input-enable;
625			mediatek,pull-down-adv = <10>;
626		};
627	};
628
629	mmc1_pins_uhs: mmc1-pins-uhs {
630		pins_cmd_dat {
631			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
632				 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
633				 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
634				 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
635				 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
636			drive-strength = <MTK_DRIVE_6mA>;
637			input-enable;
638			mediatek,pull-up-adv = <10>;
639		};
640
641		pins_clk {
642			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
643			drive-strength = <MTK_DRIVE_8mA>;
644			mediatek,pull-down-adv = <10>;
645			input-enable;
646		};
647	};
648
649	panel_pins_default: panel_pins_default {
650		panel_reset {
651			pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
652			output-low;
653			bias-pull-up;
654		};
655	};
656
657	pwm0_pin_default: pwm0_pin_default {
658		pins1 {
659			pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
660			output-high;
661			bias-pull-up;
662		};
663		pins2 {
664			pinmux = <PINMUX_GPIO43__FUNC_DISP_PWM>;
665		};
666	};
667
668	scp_pins: scp {
669		pins_scp_uart {
670			pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
671				 <PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
672		};
673	};
674
675	spi0_pins: spi0 {
676		pins_spi{
677			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
678				 <PINMUX_GPIO86__FUNC_GPIO86>,
679				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
680				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
681			bias-disable;
682		};
683	};
684
685	spi1_pins: spi1 {
686		pins_spi{
687			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
688				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
689				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
690				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
691			bias-disable;
692		};
693	};
694
695	spi2_pins: spi2 {
696		pins_spi{
697			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
698				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
699				 <PINMUX_GPIO2__FUNC_SPI2_CLK>;
700			bias-disable;
701		};
702		pins_spi_mi {
703			pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
704			mediatek,pull-down-adv = <00>;
705		};
706	};
707
708	spi3_pins: spi3 {
709		pins_spi{
710			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
711				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
712				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
713				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
714			bias-disable;
715		};
716	};
717
718	spi4_pins: spi4 {
719		pins_spi{
720			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
721				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
722				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
723				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
724			bias-disable;
725		};
726	};
727
728	spi5_pins: spi5 {
729		pins_spi{
730			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
731				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
732				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
733				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
734			bias-disable;
735		};
736	};
737
738	uart0_pins_default: uart0-pins-default {
739		pins_rx {
740			pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
741			input-enable;
742			bias-pull-up;
743		};
744		pins_tx {
745			pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
746		};
747	};
748
749	uart1_pins_default: uart1-pins-default {
750		pins_rx {
751			pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
752			input-enable;
753			bias-pull-up;
754		};
755		pins_tx {
756			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
757		};
758		pins_rts {
759			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
760			output-enable;
761		};
762		pins_cts {
763			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
764			input-enable;
765		};
766	};
767
768	uart1_pins_sleep: uart1-pins-sleep {
769		pins_rx {
770			pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
771			input-enable;
772			bias-pull-up;
773		};
774		pins_tx {
775			pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
776		};
777		pins_rts {
778			pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
779			output-enable;
780		};
781		pins_cts {
782			pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
783			input-enable;
784		};
785	};
786
787	wifi_pins_pwrseq: wifi-pins-pwrseq {
788		pins_wifi_enable {
789			pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
790			output-low;
791		};
792	};
793
794	wifi_pins_wakeup: wifi-pins-wakeup {
795		pins_wifi_wakeup {
796			pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
797			input-enable;
798		};
799	};
800};
801
802&pwm0 {
803	status = "okay";
804	pinctrl-names = "default";
805	pinctrl-0 = <&pwm0_pin_default>;
806};
807
808&scp {
809	status = "okay";
810	pinctrl-names = "default";
811	pinctrl-0 = <&scp_pins>;
812
813	cros_ec {
814		compatible = "google,cros-ec-rpmsg";
815		mediatek,rpmsg-name = "cros-ec-rpmsg";
816	};
817};
818
819&mfg_async {
820	domain-supply = <&mt6358_vsram_gpu_reg>;
821};
822
823&mfg {
824	domain-supply = <&mt6358_vgpu_reg>;
825};
826
827&soc_data {
828	status = "okay";
829};
830
831&spi0 {
832	pinctrl-names = "default";
833	pinctrl-0 = <&spi0_pins>;
834	mediatek,pad-select = <0>;
835	status = "okay";
836	cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
837
838	cr50@0 {
839		compatible = "google,cr50";
840		reg = <0>;
841		spi-max-frequency = <1000000>;
842		pinctrl-names = "default";
843		pinctrl-0 = <&h1_int_od_l>;
844		interrupt-parent = <&pio>;
845		interrupts = <153 IRQ_TYPE_EDGE_RISING>;
846	};
847};
848
849&spi1 {
850	pinctrl-names = "default";
851	pinctrl-0 = <&spi1_pins>;
852	mediatek,pad-select = <0>;
853	status = "okay";
854
855	w25q64dw: flash@0 {
856		compatible = "winbond,w25q64dw", "jedec,spi-nor";
857		reg = <0>;
858		spi-max-frequency = <25000000>;
859	};
860};
861
862&spi2 {
863	pinctrl-names = "default";
864	pinctrl-0 = <&spi2_pins>;
865	mediatek,pad-select = <0>;
866	status = "okay";
867
868	cros_ec: cros-ec@0 {
869		compatible = "google,cros-ec-spi";
870		reg = <0>;
871		spi-max-frequency = <3000000>;
872		interrupt-parent = <&pio>;
873		interrupts = <151 IRQ_TYPE_LEVEL_LOW>;
874		pinctrl-names = "default";
875		pinctrl-0 = <&ec_ap_int_odl>;
876
877		i2c_tunnel: i2c-tunnel {
878			compatible = "google,cros-ec-i2c-tunnel";
879			google,remote-bus = <1>;
880			#address-cells = <1>;
881			#size-cells = <0>;
882		};
883
884		usbc_extcon: extcon0 {
885			compatible = "google,extcon-usbc-cros-ec";
886			google,usb-port-id = <0>;
887		};
888
889		cbas {
890			compatible = "google,cros-cbas";
891		};
892
893		typec {
894			compatible = "google,cros-ec-typec";
895			#address-cells = <1>;
896			#size-cells = <0>;
897
898			usb_c0: connector@0 {
899				compatible = "usb-c-connector";
900				reg = <0>;
901				power-role = "dual";
902				data-role = "host";
903				try-power-role = "sink";
904			};
905		};
906	};
907};
908
909&spi3 {
910	pinctrl-names = "default";
911	pinctrl-0 = <&spi3_pins>;
912	mediatek,pad-select = <0>;
913	status = "disabled";
914};
915
916&spi4 {
917	pinctrl-names = "default";
918	pinctrl-0 = <&spi4_pins>;
919	mediatek,pad-select = <0>;
920	status = "disabled";
921};
922
923&spi5 {
924	pinctrl-names = "default";
925	pinctrl-0 = <&spi5_pins>;
926	mediatek,pad-select = <0>;
927	status = "disabled";
928};
929
930&ssusb {
931	dr_mode = "host";
932	wakeup-source;
933	vusb33-supply = <&mt6358_vusb_reg>;
934	status = "okay";
935};
936
937&thermal_zones {
938	tboard1 {
939		polling-delay = <1000>; /* milliseconds */
940		polling-delay-passive = <0>; /* milliseconds */
941		thermal-sensors = <&tboard_thermistor1>;
942	};
943
944	tboard2 {
945		polling-delay = <1000>; /* milliseconds */
946		polling-delay-passive = <0>; /* milliseconds */
947		thermal-sensors = <&tboard_thermistor2>;
948	};
949};
950
951&u3phy {
952	status = "okay";
953};
954
955&uart0 {
956	pinctrl-names = "default";
957	pinctrl-0 = <&uart0_pins_default>;
958	status = "okay";
959};
960
961&uart1 {
962	pinctrl-names = "default", "sleep";
963	pinctrl-0 = <&uart1_pins_default>;
964	pinctrl-1 = <&uart1_pins_sleep>;
965	status = "okay";
966	/delete-property/ interrupts;
967	interrupts-extended = <&sysirq GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
968			      <&pio 121 IRQ_TYPE_EDGE_FALLING>;
969
970	bluetooth: bluetooth {
971		pinctrl-names = "default";
972		pinctrl-0 = <&bt_pins>;
973		status = "okay";
974		compatible = "qcom,qca6174-bt";
975		enable-gpios = <&pio 120 0>;
976		clocks = <&clk32k>;
977		firmware-name = "nvm_00440302_i2s.bin";
978	};
979};
980
981&usb_host {
982	#address-cells = <1>;
983	#size-cells = <0>;
984	vusb33-supply = <&mt6358_vusb_reg>;
985	status = "okay";
986
987	hub@1 {
988		compatible = "usb5e3,610";
989		reg = <1>;
990	};
991};
992
993#include <arm/cros-ec-sbs.dtsi>
994