1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Eddie Huang <eddie.huang@mediatek.com> 5 */ 6 7#include <dt-bindings/clock/mt8173-clk.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/memory/mt8173-larb-port.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/mt8173-power.h> 13#include <dt-bindings/reset/mt8173-resets.h> 14#include <dt-bindings/gce/mt8173-gce.h> 15#include <dt-bindings/thermal/thermal.h> 16#include "mt8173-pinfunc.h" 17 18/ { 19 compatible = "mediatek,mt8173"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl1 = &ovl1; 27 rdma0 = &rdma0; 28 rdma1 = &rdma1; 29 rdma2 = &rdma2; 30 wdma0 = &wdma0; 31 wdma1 = &wdma1; 32 color0 = &color0; 33 color1 = &color1; 34 split0 = &split0; 35 split1 = &split1; 36 dpi0 = &dpi0; 37 dsi0 = &dsi0; 38 dsi1 = &dsi1; 39 mdp-rdma0 = &mdp_rdma0; 40 mdp-rdma1 = &mdp_rdma1; 41 mdp-rsz0 = &mdp_rsz0; 42 mdp-rsz1 = &mdp_rsz1; 43 mdp-rsz2 = &mdp_rsz2; 44 mdp-wdma0 = &mdp_wdma0; 45 mdp-wrot0 = &mdp_wrot0; 46 mdp-wrot1 = &mdp_wrot1; 47 serial0 = &uart0; 48 serial1 = &uart1; 49 serial2 = &uart2; 50 serial3 = &uart3; 51 }; 52 53 cluster0_opp: opp-table-0 { 54 compatible = "operating-points-v2"; 55 opp-shared; 56 opp-507000000 { 57 opp-hz = /bits/ 64 <507000000>; 58 opp-microvolt = <859000>; 59 }; 60 opp-702000000 { 61 opp-hz = /bits/ 64 <702000000>; 62 opp-microvolt = <908000>; 63 }; 64 opp-1001000000 { 65 opp-hz = /bits/ 64 <1001000000>; 66 opp-microvolt = <983000>; 67 }; 68 opp-1105000000 { 69 opp-hz = /bits/ 64 <1105000000>; 70 opp-microvolt = <1009000>; 71 }; 72 opp-1209000000 { 73 opp-hz = /bits/ 64 <1209000000>; 74 opp-microvolt = <1034000>; 75 }; 76 opp-1300000000 { 77 opp-hz = /bits/ 64 <1300000000>; 78 opp-microvolt = <1057000>; 79 }; 80 opp-1508000000 { 81 opp-hz = /bits/ 64 <1508000000>; 82 opp-microvolt = <1109000>; 83 }; 84 opp-1703000000 { 85 opp-hz = /bits/ 64 <1703000000>; 86 opp-microvolt = <1125000>; 87 }; 88 }; 89 90 cluster1_opp: opp-table-1 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 opp-507000000 { 94 opp-hz = /bits/ 64 <507000000>; 95 opp-microvolt = <828000>; 96 }; 97 opp-702000000 { 98 opp-hz = /bits/ 64 <702000000>; 99 opp-microvolt = <867000>; 100 }; 101 opp-1001000000 { 102 opp-hz = /bits/ 64 <1001000000>; 103 opp-microvolt = <927000>; 104 }; 105 opp-1209000000 { 106 opp-hz = /bits/ 64 <1209000000>; 107 opp-microvolt = <968000>; 108 }; 109 opp-1404000000 { 110 opp-hz = /bits/ 64 <1404000000>; 111 opp-microvolt = <1007000>; 112 }; 113 opp-1612000000 { 114 opp-hz = /bits/ 64 <1612000000>; 115 opp-microvolt = <1049000>; 116 }; 117 opp-1807000000 { 118 opp-hz = /bits/ 64 <1807000000>; 119 opp-microvolt = <1089000>; 120 }; 121 opp-2106000000 { 122 opp-hz = /bits/ 64 <2106000000>; 123 opp-microvolt = <1125000>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 cpu-map { 132 cluster0 { 133 core0 { 134 cpu = <&cpu0>; 135 }; 136 core1 { 137 cpu = <&cpu1>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&cpu2>; 144 }; 145 core1 { 146 cpu = <&cpu3>; 147 }; 148 }; 149 }; 150 151 cpu0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x000>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 #cooling-cells = <2>; 158 dynamic-power-coefficient = <263>; 159 clocks = <&infracfg CLK_INFRA_CA53SEL>, 160 <&apmixedsys CLK_APMIXED_MAINPLL>; 161 clock-names = "cpu", "intermediate"; 162 operating-points-v2 = <&cluster0_opp>; 163 capacity-dmips-mhz = <740>; 164 }; 165 166 cpu1: cpu@1 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x001>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_SLEEP_0>; 172 #cooling-cells = <2>; 173 dynamic-power-coefficient = <263>; 174 clocks = <&infracfg CLK_INFRA_CA53SEL>, 175 <&apmixedsys CLK_APMIXED_MAINPLL>; 176 clock-names = "cpu", "intermediate"; 177 operating-points-v2 = <&cluster0_opp>; 178 capacity-dmips-mhz = <740>; 179 }; 180 181 cpu2: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a72"; 184 reg = <0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <530>; 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cluster1_opp>; 193 capacity-dmips-mhz = <1024>; 194 }; 195 196 cpu3: cpu@101 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a72"; 199 reg = <0x101>; 200 enable-method = "psci"; 201 cpu-idle-states = <&CPU_SLEEP_0>; 202 #cooling-cells = <2>; 203 dynamic-power-coefficient = <530>; 204 clocks = <&infracfg CLK_INFRA_CA72SEL>, 205 <&apmixedsys CLK_APMIXED_MAINPLL>; 206 clock-names = "cpu", "intermediate"; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <1024>; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 CPU_SLEEP_0: cpu-sleep-0 { 215 compatible = "arm,idle-state"; 216 local-timer-stop; 217 entry-latency-us = <639>; 218 exit-latency-us = <680>; 219 min-residency-us = <1088>; 220 arm,psci-suspend-param = <0x0010000>; 221 }; 222 }; 223 }; 224 225 pmu_a53 { 226 compatible = "arm,cortex-a53-pmu"; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 228 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 229 interrupt-affinity = <&cpu0>, <&cpu1>; 230 }; 231 232 pmu_a72 { 233 compatible = "arm,cortex-a72-pmu"; 234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 235 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 236 interrupt-affinity = <&cpu2>, <&cpu3>; 237 }; 238 239 psci { 240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 241 method = "smc"; 242 cpu_suspend = <0x84000001>; 243 cpu_off = <0x84000002>; 244 cpu_on = <0x84000003>; 245 }; 246 247 clk26m: oscillator0 { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <26000000>; 251 clock-output-names = "clk26m"; 252 }; 253 254 clk32k: oscillator1 { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <32000>; 258 clock-output-names = "clk32k"; 259 }; 260 261 cpum_ck: oscillator2 { 262 compatible = "fixed-clock"; 263 #clock-cells = <0>; 264 clock-frequency = <0>; 265 clock-output-names = "cpum_ck"; 266 }; 267 268 thermal-zones { 269 cpu_thermal: cpu-thermal { 270 polling-delay-passive = <1000>; /* milliseconds */ 271 polling-delay = <1000>; /* milliseconds */ 272 273 thermal-sensors = <&thermal>; 274 sustainable-power = <1500>; /* milliwatts */ 275 276 trips { 277 threshold: trip-point0 { 278 temperature = <68000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 target: trip-point1 { 284 temperature = <85000>; 285 hysteresis = <2000>; 286 type = "passive"; 287 }; 288 289 cpu_crit: cpu_crit0 { 290 temperature = <115000>; 291 hysteresis = <2000>; 292 type = "critical"; 293 }; 294 }; 295 296 cooling-maps { 297 map0 { 298 trip = <&target>; 299 cooling-device = <&cpu0 THERMAL_NO_LIMIT 300 THERMAL_NO_LIMIT>, 301 <&cpu1 THERMAL_NO_LIMIT 302 THERMAL_NO_LIMIT>; 303 contribution = <3072>; 304 }; 305 map1 { 306 trip = <&target>; 307 cooling-device = <&cpu2 THERMAL_NO_LIMIT 308 THERMAL_NO_LIMIT>, 309 <&cpu3 THERMAL_NO_LIMIT 310 THERMAL_NO_LIMIT>; 311 contribution = <1024>; 312 }; 313 }; 314 }; 315 }; 316 317 reserved-memory { 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 322 compatible = "shared-dma-pool"; 323 reg = <0 0xb7000000 0 0x500000>; 324 alignment = <0x1000>; 325 no-map; 326 }; 327 }; 328 329 timer { 330 compatible = "arm,armv8-timer"; 331 interrupt-parent = <&gic>; 332 interrupts = <GIC_PPI 13 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 334 <GIC_PPI 14 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336 <GIC_PPI 11 337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 338 <GIC_PPI 10 339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 340 arm,no-tick-in-suspend; 341 }; 342 343 soc { 344 #address-cells = <2>; 345 #size-cells = <2>; 346 compatible = "simple-bus"; 347 ranges; 348 349 topckgen: clock-controller@10000000 { 350 compatible = "mediatek,mt8173-topckgen"; 351 reg = <0 0x10000000 0 0x1000>; 352 #clock-cells = <1>; 353 }; 354 355 infracfg: power-controller@10001000 { 356 compatible = "mediatek,mt8173-infracfg", "syscon"; 357 reg = <0 0x10001000 0 0x1000>; 358 #clock-cells = <1>; 359 #reset-cells = <1>; 360 }; 361 362 pericfg: power-controller@10003000 { 363 compatible = "mediatek,mt8173-pericfg", "syscon"; 364 reg = <0 0x10003000 0 0x1000>; 365 #clock-cells = <1>; 366 #reset-cells = <1>; 367 }; 368 369 syscfg_pctl_a: syscfg_pctl_a@10005000 { 370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 371 reg = <0 0x10005000 0 0x1000>; 372 }; 373 374 pio: pinctrl@1000b000 { 375 compatible = "mediatek,mt8173-pinctrl"; 376 reg = <0 0x1000b000 0 0x1000>; 377 mediatek,pctl-regmap = <&syscfg_pctl_a>; 378 pins-are-numbered; 379 gpio-controller; 380 #gpio-cells = <2>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 386 387 hdmi_pin: xxx { 388 389 /*hdmi htplg pin*/ 390 pins1 { 391 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 392 input-enable; 393 bias-pull-down; 394 }; 395 }; 396 397 i2c0_pins_a: i2c0 { 398 pins1 { 399 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 400 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 401 bias-disable; 402 }; 403 }; 404 405 i2c1_pins_a: i2c1 { 406 pins1 { 407 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 408 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 409 bias-disable; 410 }; 411 }; 412 413 i2c2_pins_a: i2c2 { 414 pins1 { 415 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 416 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 417 bias-disable; 418 }; 419 }; 420 421 i2c3_pins_a: i2c3 { 422 pins1 { 423 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 424 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 425 bias-disable; 426 }; 427 }; 428 429 i2c4_pins_a: i2c4 { 430 pins1 { 431 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 432 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 433 bias-disable; 434 }; 435 }; 436 437 i2c6_pins_a: i2c6 { 438 pins1 { 439 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 440 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 441 bias-disable; 442 }; 443 }; 444 }; 445 446 scpsys: syscon@10006000 { 447 compatible = "syscon", "simple-mfd"; 448 reg = <0 0x10006000 0 0x1000>; 449 #power-domain-cells = <1>; 450 451 /* System Power Manager */ 452 spm: power-controller { 453 compatible = "mediatek,mt8173-power-controller"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 #power-domain-cells = <1>; 457 458 /* power domains of the SoC */ 459 power-domain@MT8173_POWER_DOMAIN_VDEC { 460 reg = <MT8173_POWER_DOMAIN_VDEC>; 461 clocks = <&topckgen CLK_TOP_MM_SEL>; 462 clock-names = "mm"; 463 #power-domain-cells = <0>; 464 }; 465 power-domain@MT8173_POWER_DOMAIN_VENC { 466 reg = <MT8173_POWER_DOMAIN_VENC>; 467 clocks = <&topckgen CLK_TOP_MM_SEL>, 468 <&topckgen CLK_TOP_VENC_SEL>; 469 clock-names = "mm", "venc"; 470 #power-domain-cells = <0>; 471 }; 472 power-domain@MT8173_POWER_DOMAIN_ISP { 473 reg = <MT8173_POWER_DOMAIN_ISP>; 474 clocks = <&topckgen CLK_TOP_MM_SEL>; 475 clock-names = "mm"; 476 #power-domain-cells = <0>; 477 }; 478 power-domain@MT8173_POWER_DOMAIN_MM { 479 reg = <MT8173_POWER_DOMAIN_MM>; 480 clocks = <&topckgen CLK_TOP_MM_SEL>; 481 clock-names = "mm"; 482 #power-domain-cells = <0>; 483 mediatek,infracfg = <&infracfg>; 484 }; 485 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 486 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 487 clocks = <&topckgen CLK_TOP_MM_SEL>, 488 <&topckgen CLK_TOP_VENC_LT_SEL>; 489 clock-names = "mm", "venclt"; 490 #power-domain-cells = <0>; 491 }; 492 power-domain@MT8173_POWER_DOMAIN_AUDIO { 493 reg = <MT8173_POWER_DOMAIN_AUDIO>; 494 #power-domain-cells = <0>; 495 }; 496 power-domain@MT8173_POWER_DOMAIN_USB { 497 reg = <MT8173_POWER_DOMAIN_USB>; 498 #power-domain-cells = <0>; 499 }; 500 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 501 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 502 clocks = <&clk26m>; 503 clock-names = "mfg"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 #power-domain-cells = <1>; 507 508 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 509 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 #power-domain-cells = <1>; 513 514 power-domain@MT8173_POWER_DOMAIN_MFG { 515 reg = <MT8173_POWER_DOMAIN_MFG>; 516 #power-domain-cells = <0>; 517 mediatek,infracfg = <&infracfg>; 518 }; 519 }; 520 }; 521 }; 522 }; 523 524 watchdog: watchdog@10007000 { 525 compatible = "mediatek,mt8173-wdt", 526 "mediatek,mt6589-wdt"; 527 reg = <0 0x10007000 0 0x100>; 528 }; 529 530 timer: timer@10008000 { 531 compatible = "mediatek,mt8173-timer", 532 "mediatek,mt6577-timer"; 533 reg = <0 0x10008000 0 0x1000>; 534 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 535 clocks = <&infracfg CLK_INFRA_CLK_13M>, 536 <&topckgen CLK_TOP_RTC_SEL>; 537 }; 538 539 pwrap: pwrap@1000d000 { 540 compatible = "mediatek,mt8173-pwrap"; 541 reg = <0 0x1000d000 0 0x1000>; 542 reg-names = "pwrap"; 543 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 544 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 545 reset-names = "pwrap"; 546 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 547 clock-names = "spi", "wrap"; 548 }; 549 550 cec: cec@10013000 { 551 compatible = "mediatek,mt8173-cec"; 552 reg = <0 0x10013000 0 0xbc>; 553 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 554 clocks = <&infracfg CLK_INFRA_CEC>; 555 status = "disabled"; 556 }; 557 558 vpu: vpu@10020000 { 559 compatible = "mediatek,mt8173-vpu"; 560 reg = <0 0x10020000 0 0x30000>, 561 <0 0x10050000 0 0x100>; 562 reg-names = "tcm", "cfg_reg"; 563 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&topckgen CLK_TOP_SCP_SEL>; 565 clock-names = "main"; 566 memory-region = <&vpu_dma_reserved>; 567 }; 568 569 sysirq: intpol-controller@10200620 { 570 compatible = "mediatek,mt8173-sysirq", 571 "mediatek,mt6577-sysirq"; 572 interrupt-controller; 573 #interrupt-cells = <3>; 574 interrupt-parent = <&gic>; 575 reg = <0 0x10200620 0 0x20>; 576 }; 577 578 iommu: iommu@10205000 { 579 compatible = "mediatek,mt8173-m4u"; 580 reg = <0 0x10205000 0 0x1000>; 581 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 582 clocks = <&infracfg CLK_INFRA_M4U>; 583 clock-names = "bclk"; 584 mediatek,infracfg = <&infracfg>; 585 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 586 <&larb3>, <&larb4>, <&larb5>; 587 #iommu-cells = <1>; 588 }; 589 590 efuse: efuse@10206000 { 591 compatible = "mediatek,mt8173-efuse"; 592 reg = <0 0x10206000 0 0x1000>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 thermal_calibration: calib@528 { 596 reg = <0x528 0xc>; 597 }; 598 }; 599 600 apmixedsys: clock-controller@10209000 { 601 compatible = "mediatek,mt8173-apmixedsys"; 602 reg = <0 0x10209000 0 0x1000>; 603 #clock-cells = <1>; 604 }; 605 606 hdmi_phy: hdmi-phy@10209100 { 607 compatible = "mediatek,mt8173-hdmi-phy"; 608 reg = <0 0x10209100 0 0x24>; 609 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 610 clock-names = "pll_ref"; 611 clock-output-names = "hdmitx_dig_cts"; 612 mediatek,ibias = <0xa>; 613 mediatek,ibias_up = <0x1c>; 614 #clock-cells = <0>; 615 #phy-cells = <0>; 616 status = "disabled"; 617 }; 618 619 gce: mailbox@10212000 { 620 compatible = "mediatek,mt8173-gce"; 621 reg = <0 0x10212000 0 0x1000>; 622 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 623 clocks = <&infracfg CLK_INFRA_GCE>; 624 clock-names = "gce"; 625 #mbox-cells = <2>; 626 }; 627 628 mipi_tx0: dsi-phy@10215000 { 629 compatible = "mediatek,mt8173-mipi-tx"; 630 reg = <0 0x10215000 0 0x1000>; 631 clocks = <&clk26m>; 632 clock-output-names = "mipi_tx0_pll"; 633 #clock-cells = <0>; 634 #phy-cells = <0>; 635 status = "disabled"; 636 }; 637 638 mipi_tx1: dsi-phy@10216000 { 639 compatible = "mediatek,mt8173-mipi-tx"; 640 reg = <0 0x10216000 0 0x1000>; 641 clocks = <&clk26m>; 642 clock-output-names = "mipi_tx1_pll"; 643 #clock-cells = <0>; 644 #phy-cells = <0>; 645 status = "disabled"; 646 }; 647 648 gic: interrupt-controller@10221000 { 649 compatible = "arm,gic-400"; 650 #interrupt-cells = <3>; 651 interrupt-parent = <&gic>; 652 interrupt-controller; 653 reg = <0 0x10221000 0 0x1000>, 654 <0 0x10222000 0 0x2000>, 655 <0 0x10224000 0 0x2000>, 656 <0 0x10226000 0 0x2000>; 657 interrupts = <GIC_PPI 9 658 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 659 }; 660 661 auxadc: auxadc@11001000 { 662 compatible = "mediatek,mt8173-auxadc"; 663 reg = <0 0x11001000 0 0x1000>; 664 clocks = <&pericfg CLK_PERI_AUXADC>; 665 clock-names = "main"; 666 #io-channel-cells = <1>; 667 }; 668 669 uart0: serial@11002000 { 670 compatible = "mediatek,mt8173-uart", 671 "mediatek,mt6577-uart"; 672 reg = <0 0x11002000 0 0x400>; 673 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 674 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 675 clock-names = "baud", "bus"; 676 status = "disabled"; 677 }; 678 679 uart1: serial@11003000 { 680 compatible = "mediatek,mt8173-uart", 681 "mediatek,mt6577-uart"; 682 reg = <0 0x11003000 0 0x400>; 683 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 684 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 685 clock-names = "baud", "bus"; 686 status = "disabled"; 687 }; 688 689 uart2: serial@11004000 { 690 compatible = "mediatek,mt8173-uart", 691 "mediatek,mt6577-uart"; 692 reg = <0 0x11004000 0 0x400>; 693 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 694 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 695 clock-names = "baud", "bus"; 696 status = "disabled"; 697 }; 698 699 uart3: serial@11005000 { 700 compatible = "mediatek,mt8173-uart", 701 "mediatek,mt6577-uart"; 702 reg = <0 0x11005000 0 0x400>; 703 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 704 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 705 clock-names = "baud", "bus"; 706 status = "disabled"; 707 }; 708 709 i2c0: i2c@11007000 { 710 compatible = "mediatek,mt8173-i2c"; 711 reg = <0 0x11007000 0 0x70>, 712 <0 0x11000100 0 0x80>; 713 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 714 clock-div = <16>; 715 clocks = <&pericfg CLK_PERI_I2C0>, 716 <&pericfg CLK_PERI_AP_DMA>; 717 clock-names = "main", "dma"; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&i2c0_pins_a>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 i2c1: i2c@11008000 { 726 compatible = "mediatek,mt8173-i2c"; 727 reg = <0 0x11008000 0 0x70>, 728 <0 0x11000180 0 0x80>; 729 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 730 clock-div = <16>; 731 clocks = <&pericfg CLK_PERI_I2C1>, 732 <&pericfg CLK_PERI_AP_DMA>; 733 clock-names = "main", "dma"; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&i2c1_pins_a>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 status = "disabled"; 739 }; 740 741 i2c2: i2c@11009000 { 742 compatible = "mediatek,mt8173-i2c"; 743 reg = <0 0x11009000 0 0x70>, 744 <0 0x11000200 0 0x80>; 745 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 746 clock-div = <16>; 747 clocks = <&pericfg CLK_PERI_I2C2>, 748 <&pericfg CLK_PERI_AP_DMA>; 749 clock-names = "main", "dma"; 750 pinctrl-names = "default"; 751 pinctrl-0 = <&i2c2_pins_a>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 spi: spi@1100a000 { 758 compatible = "mediatek,mt8173-spi"; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 reg = <0 0x1100a000 0 0x1000>; 762 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 763 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 764 <&topckgen CLK_TOP_SPI_SEL>, 765 <&pericfg CLK_PERI_SPI0>; 766 clock-names = "parent-clk", "sel-clk", "spi-clk"; 767 status = "disabled"; 768 }; 769 770 thermal: thermal@1100b000 { 771 #thermal-sensor-cells = <0>; 772 compatible = "mediatek,mt8173-thermal"; 773 reg = <0 0x1100b000 0 0x1000>; 774 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 775 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 776 clock-names = "therm", "auxadc"; 777 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 778 mediatek,auxadc = <&auxadc>; 779 mediatek,apmixedsys = <&apmixedsys>; 780 nvmem-cells = <&thermal_calibration>; 781 nvmem-cell-names = "calibration-data"; 782 }; 783 784 nor_flash: spi@1100d000 { 785 compatible = "mediatek,mt8173-nor"; 786 reg = <0 0x1100d000 0 0xe0>; 787 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; 788 assigned-clock-parents = <&clk26m>; 789 clocks = <&pericfg CLK_PERI_SPI>, 790 <&topckgen CLK_TOP_SPINFI_IFR_SEL>, 791 <&pericfg CLK_PERI_NFI>; 792 clock-names = "spi", "sf", "axi"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 status = "disabled"; 796 }; 797 798 i2c3: i2c@11010000 { 799 compatible = "mediatek,mt8173-i2c"; 800 reg = <0 0x11010000 0 0x70>, 801 <0 0x11000280 0 0x80>; 802 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 803 clock-div = <16>; 804 clocks = <&pericfg CLK_PERI_I2C3>, 805 <&pericfg CLK_PERI_AP_DMA>; 806 clock-names = "main", "dma"; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&i2c3_pins_a>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 status = "disabled"; 812 }; 813 814 i2c4: i2c@11011000 { 815 compatible = "mediatek,mt8173-i2c"; 816 reg = <0 0x11011000 0 0x70>, 817 <0 0x11000300 0 0x80>; 818 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 819 clock-div = <16>; 820 clocks = <&pericfg CLK_PERI_I2C4>, 821 <&pericfg CLK_PERI_AP_DMA>; 822 clock-names = "main", "dma"; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&i2c4_pins_a>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 status = "disabled"; 828 }; 829 830 hdmiddc0: i2c@11012000 { 831 compatible = "mediatek,mt8173-hdmi-ddc"; 832 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 833 reg = <0 0x11012000 0 0x1C>; 834 clocks = <&pericfg CLK_PERI_I2C5>; 835 clock-names = "ddc-i2c"; 836 }; 837 838 i2c6: i2c@11013000 { 839 compatible = "mediatek,mt8173-i2c"; 840 reg = <0 0x11013000 0 0x70>, 841 <0 0x11000080 0 0x80>; 842 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 843 clock-div = <16>; 844 clocks = <&pericfg CLK_PERI_I2C6>, 845 <&pericfg CLK_PERI_AP_DMA>; 846 clock-names = "main", "dma"; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&i2c6_pins_a>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 afe: audio-controller@11220000 { 855 compatible = "mediatek,mt8173-afe-pcm"; 856 reg = <0 0x11220000 0 0x1000>; 857 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 858 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 859 clocks = <&infracfg CLK_INFRA_AUDIO>, 860 <&topckgen CLK_TOP_AUDIO_SEL>, 861 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 862 <&topckgen CLK_TOP_APLL1_DIV0>, 863 <&topckgen CLK_TOP_APLL2_DIV0>, 864 <&topckgen CLK_TOP_I2S0_M_SEL>, 865 <&topckgen CLK_TOP_I2S1_M_SEL>, 866 <&topckgen CLK_TOP_I2S2_M_SEL>, 867 <&topckgen CLK_TOP_I2S3_M_SEL>, 868 <&topckgen CLK_TOP_I2S3_B_SEL>; 869 clock-names = "infra_sys_audio_clk", 870 "top_pdn_audio", 871 "top_pdn_aud_intbus", 872 "bck0", 873 "bck1", 874 "i2s0_m", 875 "i2s1_m", 876 "i2s2_m", 877 "i2s3_m", 878 "i2s3_b"; 879 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 880 <&topckgen CLK_TOP_AUD_2_SEL>; 881 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 882 <&topckgen CLK_TOP_APLL2>; 883 }; 884 885 mmc0: mmc@11230000 { 886 compatible = "mediatek,mt8173-mmc"; 887 reg = <0 0x11230000 0 0x1000>; 888 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 889 clocks = <&pericfg CLK_PERI_MSDC30_0>, 890 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 891 clock-names = "source", "hclk"; 892 status = "disabled"; 893 }; 894 895 mmc1: mmc@11240000 { 896 compatible = "mediatek,mt8173-mmc"; 897 reg = <0 0x11240000 0 0x1000>; 898 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 899 clocks = <&pericfg CLK_PERI_MSDC30_1>, 900 <&topckgen CLK_TOP_AXI_SEL>; 901 clock-names = "source", "hclk"; 902 status = "disabled"; 903 }; 904 905 mmc2: mmc@11250000 { 906 compatible = "mediatek,mt8173-mmc"; 907 reg = <0 0x11250000 0 0x1000>; 908 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 909 clocks = <&pericfg CLK_PERI_MSDC30_2>, 910 <&topckgen CLK_TOP_AXI_SEL>; 911 clock-names = "source", "hclk"; 912 status = "disabled"; 913 }; 914 915 mmc3: mmc@11260000 { 916 compatible = "mediatek,mt8173-mmc"; 917 reg = <0 0x11260000 0 0x1000>; 918 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 919 clocks = <&pericfg CLK_PERI_MSDC30_3>, 920 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 921 clock-names = "source", "hclk"; 922 status = "disabled"; 923 }; 924 925 ssusb: usb@11271000 { 926 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 927 reg = <0 0x11271000 0 0x3000>, 928 <0 0x11280700 0 0x0100>; 929 reg-names = "mac", "ippc"; 930 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 931 phys = <&u2port0 PHY_TYPE_USB2>, 932 <&u3port0 PHY_TYPE_USB3>, 933 <&u2port1 PHY_TYPE_USB2>; 934 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 935 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 936 clock-names = "sys_ck", "ref_ck"; 937 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 938 #address-cells = <2>; 939 #size-cells = <2>; 940 ranges; 941 status = "disabled"; 942 943 usb_host: usb@11270000 { 944 compatible = "mediatek,mt8173-xhci", 945 "mediatek,mtk-xhci"; 946 reg = <0 0x11270000 0 0x1000>; 947 reg-names = "mac"; 948 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 949 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 950 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 951 clock-names = "sys_ck", "ref_ck"; 952 status = "disabled"; 953 }; 954 }; 955 956 u3phy: t-phy@11290000 { 957 compatible = "mediatek,mt8173-u3phy"; 958 reg = <0 0x11290000 0 0x800>; 959 #address-cells = <2>; 960 #size-cells = <2>; 961 ranges; 962 status = "okay"; 963 964 u2port0: usb-phy@11290800 { 965 reg = <0 0x11290800 0 0x100>; 966 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 967 clock-names = "ref"; 968 #phy-cells = <1>; 969 status = "okay"; 970 }; 971 972 u3port0: usb-phy@11290900 { 973 reg = <0 0x11290900 0 0x700>; 974 clocks = <&clk26m>; 975 clock-names = "ref"; 976 #phy-cells = <1>; 977 status = "okay"; 978 }; 979 980 u2port1: usb-phy@11291000 { 981 reg = <0 0x11291000 0 0x100>; 982 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 983 clock-names = "ref"; 984 #phy-cells = <1>; 985 status = "okay"; 986 }; 987 }; 988 989 mmsys: syscon@14000000 { 990 compatible = "mediatek,mt8173-mmsys", "syscon"; 991 reg = <0 0x14000000 0 0x1000>; 992 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 993 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 994 assigned-clock-rates = <400000000>; 995 #clock-cells = <1>; 996 #reset-cells = <1>; 997 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 998 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 999 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1000 }; 1001 1002 mdp_rdma0: rdma@14001000 { 1003 compatible = "mediatek,mt8173-mdp-rdma", 1004 "mediatek,mt8173-mdp"; 1005 reg = <0 0x14001000 0 0x1000>; 1006 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1007 <&mmsys CLK_MM_MUTEX_32K>; 1008 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1009 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1010 mediatek,vpu = <&vpu>; 1011 }; 1012 1013 mdp_rdma1: rdma@14002000 { 1014 compatible = "mediatek,mt8173-mdp-rdma"; 1015 reg = <0 0x14002000 0 0x1000>; 1016 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1017 <&mmsys CLK_MM_MUTEX_32K>; 1018 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1019 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1020 }; 1021 1022 mdp_rsz0: rsz@14003000 { 1023 compatible = "mediatek,mt8173-mdp-rsz"; 1024 reg = <0 0x14003000 0 0x1000>; 1025 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1026 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1027 }; 1028 1029 mdp_rsz1: rsz@14004000 { 1030 compatible = "mediatek,mt8173-mdp-rsz"; 1031 reg = <0 0x14004000 0 0x1000>; 1032 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1033 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1034 }; 1035 1036 mdp_rsz2: rsz@14005000 { 1037 compatible = "mediatek,mt8173-mdp-rsz"; 1038 reg = <0 0x14005000 0 0x1000>; 1039 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 1040 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1041 }; 1042 1043 mdp_wdma0: wdma@14006000 { 1044 compatible = "mediatek,mt8173-mdp-wdma"; 1045 reg = <0 0x14006000 0 0x1000>; 1046 clocks = <&mmsys CLK_MM_MDP_WDMA>; 1047 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1048 iommus = <&iommu M4U_PORT_MDP_WDMA>; 1049 }; 1050 1051 mdp_wrot0: wrot@14007000 { 1052 compatible = "mediatek,mt8173-mdp-wrot"; 1053 reg = <0 0x14007000 0 0x1000>; 1054 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1055 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1056 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1057 }; 1058 1059 mdp_wrot1: wrot@14008000 { 1060 compatible = "mediatek,mt8173-mdp-wrot"; 1061 reg = <0 0x14008000 0 0x1000>; 1062 clocks = <&mmsys CLK_MM_MDP_WROT1>; 1063 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1064 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1065 }; 1066 1067 ovl0: ovl@1400c000 { 1068 compatible = "mediatek,mt8173-disp-ovl"; 1069 reg = <0 0x1400c000 0 0x1000>; 1070 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1071 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1072 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1073 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1074 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1075 }; 1076 1077 ovl1: ovl@1400d000 { 1078 compatible = "mediatek,mt8173-disp-ovl"; 1079 reg = <0 0x1400d000 0 0x1000>; 1080 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1081 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1082 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1083 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1084 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1085 }; 1086 1087 rdma0: rdma@1400e000 { 1088 compatible = "mediatek,mt8173-disp-rdma"; 1089 reg = <0 0x1400e000 0 0x1000>; 1090 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1091 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1092 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1093 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1094 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1095 }; 1096 1097 rdma1: rdma@1400f000 { 1098 compatible = "mediatek,mt8173-disp-rdma"; 1099 reg = <0 0x1400f000 0 0x1000>; 1100 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1101 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1102 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1103 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1104 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1105 }; 1106 1107 rdma2: rdma@14010000 { 1108 compatible = "mediatek,mt8173-disp-rdma"; 1109 reg = <0 0x14010000 0 0x1000>; 1110 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1111 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1112 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1113 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1114 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1115 }; 1116 1117 wdma0: wdma@14011000 { 1118 compatible = "mediatek,mt8173-disp-wdma"; 1119 reg = <0 0x14011000 0 0x1000>; 1120 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1121 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1122 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1123 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1124 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1125 }; 1126 1127 wdma1: wdma@14012000 { 1128 compatible = "mediatek,mt8173-disp-wdma"; 1129 reg = <0 0x14012000 0 0x1000>; 1130 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1131 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1132 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1133 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1134 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1135 }; 1136 1137 color0: color@14013000 { 1138 compatible = "mediatek,mt8173-disp-color"; 1139 reg = <0 0x14013000 0 0x1000>; 1140 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1141 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1142 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1143 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1144 }; 1145 1146 color1: color@14014000 { 1147 compatible = "mediatek,mt8173-disp-color"; 1148 reg = <0 0x14014000 0 0x1000>; 1149 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1150 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1151 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1152 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1153 }; 1154 1155 aal@14015000 { 1156 compatible = "mediatek,mt8173-disp-aal"; 1157 reg = <0 0x14015000 0 0x1000>; 1158 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1159 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1160 clocks = <&mmsys CLK_MM_DISP_AAL>; 1161 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1162 }; 1163 1164 gamma@14016000 { 1165 compatible = "mediatek,mt8173-disp-gamma"; 1166 reg = <0 0x14016000 0 0x1000>; 1167 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1168 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1169 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1170 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1171 }; 1172 1173 merge@14017000 { 1174 compatible = "mediatek,mt8173-disp-merge"; 1175 reg = <0 0x14017000 0 0x1000>; 1176 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1177 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1178 }; 1179 1180 split0: split@14018000 { 1181 compatible = "mediatek,mt8173-disp-split"; 1182 reg = <0 0x14018000 0 0x1000>; 1183 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1184 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1185 }; 1186 1187 split1: split@14019000 { 1188 compatible = "mediatek,mt8173-disp-split"; 1189 reg = <0 0x14019000 0 0x1000>; 1190 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1191 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1192 }; 1193 1194 ufoe@1401a000 { 1195 compatible = "mediatek,mt8173-disp-ufoe"; 1196 reg = <0 0x1401a000 0 0x1000>; 1197 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1198 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1199 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1200 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 1201 }; 1202 1203 dsi0: dsi@1401b000 { 1204 compatible = "mediatek,mt8173-dsi"; 1205 reg = <0 0x1401b000 0 0x1000>; 1206 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1207 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1208 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1209 <&mmsys CLK_MM_DSI0_DIGITAL>, 1210 <&mipi_tx0>; 1211 clock-names = "engine", "digital", "hs"; 1212 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 1213 phys = <&mipi_tx0>; 1214 phy-names = "dphy"; 1215 status = "disabled"; 1216 }; 1217 1218 dsi1: dsi@1401c000 { 1219 compatible = "mediatek,mt8173-dsi"; 1220 reg = <0 0x1401c000 0 0x1000>; 1221 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1222 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1223 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1224 <&mmsys CLK_MM_DSI1_DIGITAL>, 1225 <&mipi_tx1>; 1226 clock-names = "engine", "digital", "hs"; 1227 phys = <&mipi_tx1>; 1228 phy-names = "dphy"; 1229 status = "disabled"; 1230 }; 1231 1232 dpi0: dpi@1401d000 { 1233 compatible = "mediatek,mt8173-dpi"; 1234 reg = <0 0x1401d000 0 0x1000>; 1235 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1236 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1237 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1238 <&mmsys CLK_MM_DPI_ENGINE>, 1239 <&apmixedsys CLK_APMIXED_TVDPLL>; 1240 clock-names = "pixel", "engine", "pll"; 1241 status = "disabled"; 1242 1243 port { 1244 dpi0_out: endpoint { 1245 remote-endpoint = <&hdmi0_in>; 1246 }; 1247 }; 1248 }; 1249 1250 pwm0: pwm@1401e000 { 1251 compatible = "mediatek,mt8173-disp-pwm", 1252 "mediatek,mt6595-disp-pwm"; 1253 reg = <0 0x1401e000 0 0x1000>; 1254 #pwm-cells = <2>; 1255 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1256 <&mmsys CLK_MM_DISP_PWM0MM>; 1257 clock-names = "main", "mm"; 1258 status = "disabled"; 1259 }; 1260 1261 pwm1: pwm@1401f000 { 1262 compatible = "mediatek,mt8173-disp-pwm", 1263 "mediatek,mt6595-disp-pwm"; 1264 reg = <0 0x1401f000 0 0x1000>; 1265 #pwm-cells = <2>; 1266 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1267 <&mmsys CLK_MM_DISP_PWM1MM>; 1268 clock-names = "main", "mm"; 1269 status = "disabled"; 1270 }; 1271 1272 mutex: mutex@14020000 { 1273 compatible = "mediatek,mt8173-disp-mutex"; 1274 reg = <0 0x14020000 0 0x1000>; 1275 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1276 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1277 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1278 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 1279 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1280 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1281 }; 1282 1283 larb0: larb@14021000 { 1284 compatible = "mediatek,mt8173-smi-larb"; 1285 reg = <0 0x14021000 0 0x1000>; 1286 mediatek,smi = <&smi_common>; 1287 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1288 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1289 <&mmsys CLK_MM_SMI_LARB0>; 1290 clock-names = "apb", "smi"; 1291 }; 1292 1293 smi_common: smi@14022000 { 1294 compatible = "mediatek,mt8173-smi-common"; 1295 reg = <0 0x14022000 0 0x1000>; 1296 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1297 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1298 <&mmsys CLK_MM_SMI_COMMON>; 1299 clock-names = "apb", "smi"; 1300 }; 1301 1302 od@14023000 { 1303 compatible = "mediatek,mt8173-disp-od"; 1304 reg = <0 0x14023000 0 0x1000>; 1305 clocks = <&mmsys CLK_MM_DISP_OD>; 1306 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 1307 }; 1308 1309 hdmi0: hdmi@14025000 { 1310 compatible = "mediatek,mt8173-hdmi"; 1311 reg = <0 0x14025000 0 0x400>; 1312 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1313 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1314 <&mmsys CLK_MM_HDMI_PLLCK>, 1315 <&mmsys CLK_MM_HDMI_AUDIO>, 1316 <&mmsys CLK_MM_HDMI_SPDIF>; 1317 clock-names = "pixel", "pll", "bclk", "spdif"; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&hdmi_pin>; 1320 phys = <&hdmi_phy>; 1321 phy-names = "hdmi"; 1322 mediatek,syscon-hdmi = <&mmsys 0x900>; 1323 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1324 assigned-clock-parents = <&hdmi_phy>; 1325 status = "disabled"; 1326 1327 ports { 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 1331 port@0 { 1332 reg = <0>; 1333 1334 hdmi0_in: endpoint { 1335 remote-endpoint = <&dpi0_out>; 1336 }; 1337 }; 1338 }; 1339 }; 1340 1341 larb4: larb@14027000 { 1342 compatible = "mediatek,mt8173-smi-larb"; 1343 reg = <0 0x14027000 0 0x1000>; 1344 mediatek,smi = <&smi_common>; 1345 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1346 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1347 <&mmsys CLK_MM_SMI_LARB4>; 1348 clock-names = "apb", "smi"; 1349 }; 1350 1351 imgsys: clock-controller@15000000 { 1352 compatible = "mediatek,mt8173-imgsys", "syscon"; 1353 reg = <0 0x15000000 0 0x1000>; 1354 #clock-cells = <1>; 1355 }; 1356 1357 larb2: larb@15001000 { 1358 compatible = "mediatek,mt8173-smi-larb"; 1359 reg = <0 0x15001000 0 0x1000>; 1360 mediatek,smi = <&smi_common>; 1361 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 1362 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1363 <&imgsys CLK_IMG_LARB2_SMI>; 1364 clock-names = "apb", "smi"; 1365 }; 1366 1367 vdecsys: clock-controller@16000000 { 1368 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1369 reg = <0 0x16000000 0 0x1000>; 1370 #clock-cells = <1>; 1371 }; 1372 1373 vcodec_dec: vcodec@16000000 { 1374 compatible = "mediatek,mt8173-vcodec-dec"; 1375 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1376 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1377 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1378 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1379 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1380 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1381 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1382 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1383 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1384 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1385 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1386 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1387 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1388 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1389 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1390 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1391 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1392 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1393 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1394 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1395 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1396 mediatek,vpu = <&vpu>; 1397 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1398 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1399 <&topckgen CLK_TOP_UNIVPLL_D2>, 1400 <&topckgen CLK_TOP_CCI400_SEL>, 1401 <&topckgen CLK_TOP_VDEC_SEL>, 1402 <&topckgen CLK_TOP_VCODECPLL>, 1403 <&apmixedsys CLK_APMIXED_VENCPLL>, 1404 <&topckgen CLK_TOP_VENC_LT_SEL>, 1405 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1406 clock-names = "vcodecpll", 1407 "univpll_d2", 1408 "clk_cci400_sel", 1409 "vdec_sel", 1410 "vdecpll", 1411 "vencpll", 1412 "venc_lt_sel", 1413 "vdec_bus_clk_src"; 1414 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1415 <&topckgen CLK_TOP_CCI400_SEL>, 1416 <&topckgen CLK_TOP_VDEC_SEL>, 1417 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1418 <&apmixedsys CLK_APMIXED_VENCPLL>; 1419 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1420 <&topckgen CLK_TOP_UNIVPLL_D2>, 1421 <&topckgen CLK_TOP_VCODECPLL>; 1422 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1423 }; 1424 1425 larb1: larb@16010000 { 1426 compatible = "mediatek,mt8173-smi-larb"; 1427 reg = <0 0x16010000 0 0x1000>; 1428 mediatek,smi = <&smi_common>; 1429 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1430 clocks = <&vdecsys CLK_VDEC_CKEN>, 1431 <&vdecsys CLK_VDEC_LARB_CKEN>; 1432 clock-names = "apb", "smi"; 1433 }; 1434 1435 vencsys: clock-controller@18000000 { 1436 compatible = "mediatek,mt8173-vencsys", "syscon"; 1437 reg = <0 0x18000000 0 0x1000>; 1438 #clock-cells = <1>; 1439 }; 1440 1441 larb3: larb@18001000 { 1442 compatible = "mediatek,mt8173-smi-larb"; 1443 reg = <0 0x18001000 0 0x1000>; 1444 mediatek,smi = <&smi_common>; 1445 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1446 clocks = <&vencsys CLK_VENC_CKE1>, 1447 <&vencsys CLK_VENC_CKE0>; 1448 clock-names = "apb", "smi"; 1449 }; 1450 1451 vcodec_enc_avc: vcodec@18002000 { 1452 compatible = "mediatek,mt8173-vcodec-enc"; 1453 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1454 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 1455 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1456 <&iommu M4U_PORT_VENC_REC>, 1457 <&iommu M4U_PORT_VENC_BSDMA>, 1458 <&iommu M4U_PORT_VENC_SV_COMV>, 1459 <&iommu M4U_PORT_VENC_RD_COMV>, 1460 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1461 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1462 <&iommu M4U_PORT_VENC_REF_LUMA>, 1463 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1464 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1465 <&iommu M4U_PORT_VENC_NBM_WDMA>; 1466 mediatek,vpu = <&vpu>; 1467 clocks = <&topckgen CLK_TOP_VENC_SEL>; 1468 clock-names = "venc_sel"; 1469 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1470 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1471 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1472 }; 1473 1474 jpegdec: jpegdec@18004000 { 1475 compatible = "mediatek,mt8173-jpgdec"; 1476 reg = <0 0x18004000 0 0x1000>; 1477 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1478 clocks = <&vencsys CLK_VENC_CKE0>, 1479 <&vencsys CLK_VENC_CKE3>; 1480 clock-names = "jpgdec-smi", 1481 "jpgdec"; 1482 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1483 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1484 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1485 }; 1486 1487 vencltsys: clock-controller@19000000 { 1488 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1489 reg = <0 0x19000000 0 0x1000>; 1490 #clock-cells = <1>; 1491 }; 1492 1493 larb5: larb@19001000 { 1494 compatible = "mediatek,mt8173-smi-larb"; 1495 reg = <0 0x19001000 0 0x1000>; 1496 mediatek,smi = <&smi_common>; 1497 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1498 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1499 <&vencltsys CLK_VENCLT_CKE0>; 1500 clock-names = "apb", "smi"; 1501 }; 1502 1503 vcodec_enc_vp8: vcodec@19002000 { 1504 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1505 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1506 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1507 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1508 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1509 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1510 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1511 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1512 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1513 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1514 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1515 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1516 mediatek,vpu = <&vpu>; 1517 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1518 clock-names = "venc_lt_sel"; 1519 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1520 assigned-clock-parents = 1521 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1522 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1523 }; 1524 }; 1525}; 1526