xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt8173-elm.dtsi (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e) 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2016 MediaTek Inc.
4 */
5
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/regulator/dlg,da9211-regulator.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "mt8173.dtsi"
11
12/ {
13	aliases {
14		mmc0 = &mmc0;
15		mmc1 = &mmc1;
16		mmc2 = &mmc3;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0 0x40000000 0 0x80000000>;
22	};
23
24	backlight: backlight {
25		compatible = "pwm-backlight";
26		pwms = <&pwm0 0 1000000>;
27		power-supply = <&bl_fixed_reg>;
28		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
29
30		pinctrl-names = "default";
31		pinctrl-0 = <&panel_backlight_en_pins>;
32		status = "okay";
33	};
34
35	bl_fixed_reg: fixedregulator2 {
36		compatible = "regulator-fixed";
37		regulator-name = "bl_fixed";
38		regulator-min-microvolt = <1800000>;
39		regulator-max-microvolt = <1800000>;
40		startup-delay-us = <1000>;
41		enable-active-high;
42		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
43		pinctrl-names = "default";
44		pinctrl-0 = <&bl_fixed_pins>;
45	};
46
47	chosen {
48		stdout-path = "serial0:115200n8";
49	};
50
51	gpio_keys: gpio-keys {
52		compatible = "gpio-keys";
53		pinctrl-names = "default";
54		pinctrl-0 = <&gpio_keys_pins>;
55
56		switch-lid {
57			label = "Lid";
58			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
59			linux,code = <SW_LID>;
60			linux,input-type = <EV_SW>;
61			wakeup-source;
62		};
63
64		switch-power {
65			label = "Power";
66			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
67			linux,code = <KEY_POWER>;
68			debounce-interval = <30>;
69			wakeup-source;
70		};
71
72		switch-tablet-mode {
73			label = "Tablet_mode";
74			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
75			linux,code = <SW_TABLET_MODE>;
76			linux,input-type = <EV_SW>;
77			wakeup-source;
78		};
79
80		switch-volume-down {
81			label = "Volume_down";
82			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
83			linux,code = <KEY_VOLUMEDOWN>;
84		};
85
86		switch-volume-up {
87			label = "Volume_up";
88			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
89			linux,code = <KEY_VOLUMEUP>;
90		};
91	};
92
93	panel_fixed_3v3: regulator1 {
94		compatible = "regulator-fixed";
95		regulator-name = "PANEL_3V3";
96		regulator-min-microvolt = <3300000>;
97		regulator-max-microvolt = <3300000>;
98		enable-active-high;
99		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
100		pinctrl-names = "default";
101		pinctrl-0 = <&panel_fixed_pins>;
102	};
103
104	ps8640_fixed_1v2: regulator2 {
105		compatible = "regulator-fixed";
106		regulator-name = "PS8640_1V2";
107		regulator-min-microvolt = <1200000>;
108		regulator-max-microvolt = <1200000>;
109		regulator-enable-ramp-delay = <2000>;
110		enable-active-high;
111		regulator-boot-on;
112		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
113		pinctrl-names = "default";
114		pinctrl-0 = <&ps8640_fixed_pins>;
115	};
116
117	sdio_fixed_3v3: fixedregulator0 {
118		compatible = "regulator-fixed";
119		regulator-name = "3V3";
120		regulator-min-microvolt = <3300000>;
121		regulator-max-microvolt = <3300000>;
122		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
123		pinctrl-names = "default";
124		pinctrl-0 = <&sdio_fixed_3v3_pins>;
125	};
126
127	sound: sound {
128		compatible = "mediatek,mt8173-rt5650";
129		mediatek,audio-codec = <&rt5650 &hdmi0>;
130		mediatek,platform = <&afe>;
131		pinctrl-names = "default";
132		pinctrl-0 = <&aud_i2s2>;
133
134		mediatek,mclk = <1>;
135		codec-capture {
136			sound-dai = <&rt5650 1>;
137		};
138	};
139
140	hdmicon: connector {
141		compatible = "hdmi-connector";
142		label = "hdmi";
143		type = "a";
144		ddc-i2c-bus = <&hdmiddc0>;
145
146		port {
147			hdmi_connector_in: endpoint {
148				remote-endpoint = <&hdmi0_out>;
149			};
150		};
151	};
152
153	watchdog {
154		compatible = "arm,smc-wdt";
155	};
156};
157
158/*
159 * Disable the original MMIO watch dog and switch to the SMC watchdog, which
160 * operates on the same MMIO.
161 */
162&watchdog {
163	status = "disabled";
164};
165
166&mfg_async {
167	domain-supply = <&da9211_vgpu_reg>;
168};
169
170&cec {
171	status = "okay";
172};
173
174&cpu0 {
175	proc-supply = <&mt6397_vpca15_reg>;
176};
177
178&cpu1 {
179	proc-supply = <&mt6397_vpca15_reg>;
180};
181
182&cpu2 {
183	proc-supply = <&da9211_vcpu_reg>;
184	sram-supply = <&mt6397_vsramca7_reg>;
185};
186
187&cpu3 {
188	proc-supply = <&da9211_vcpu_reg>;
189	sram-supply = <&mt6397_vsramca7_reg>;
190};
191
192&cpu_thermal {
193	sustainable-power = <4500>; /* milliwatts */
194	trips {
195		threshold: trip-point0 {
196			temperature = <60000>;
197		};
198
199		target: trip-point1 {
200			temperature = <65000>;
201		};
202	};
203};
204
205&dsi0 {
206	status = "okay";
207	ports {
208		port {
209			dsi0_out: endpoint {
210				remote-endpoint = <&ps8640_in>;
211			};
212		};
213	};
214};
215
216&dpi0 {
217	status = "okay";
218};
219
220&hdmi0 {
221	status = "okay";
222	ports {
223		port@1 {
224			reg = <1>;
225
226			hdmi0_out: endpoint {
227				remote-endpoint = <&hdmi_connector_in>;
228			};
229		};
230	};
231};
232
233&hdmi_phy {
234	status = "okay";
235	mediatek,ibias = <0xc>;
236};
237
238&i2c0 {
239	status = "okay";
240
241	rt5650: audio-codec@1a {
242		compatible = "realtek,rt5650";
243		reg = <0x1a>;
244		avdd-supply = <&mt6397_vgp1_reg>;
245		cpvdd-supply = <&mt6397_vcama_reg>;
246		interrupt-parent = <&pio>;
247		interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
248		pinctrl-names = "default";
249		pinctrl-0 = <&rt5650_irq>;
250		#sound-dai-cells = <1>;
251		realtek,dmic1-data-pin = <2>;
252		realtek,jd-mode = <2>;
253	};
254
255	ps8640: edp-bridge@8 {
256		compatible = "parade,ps8640";
257		reg = <0x8>;
258		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
259		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
260		pinctrl-names = "default";
261		pinctrl-0 = <&ps8640_pins>;
262		vdd12-supply = <&ps8640_fixed_1v2>;
263		vdd33-supply = <&mt6397_vgp2_reg>;
264
265		ports {
266			#address-cells = <1>;
267			#size-cells = <0>;
268
269			port@0 {
270				reg = <0>;
271
272				ps8640_in: endpoint {
273					remote-endpoint = <&dsi0_out>;
274				};
275			};
276
277			port@1 {
278				reg = <1>;
279
280				ps8640_out: endpoint {
281					remote-endpoint = <&panel_in>;
282				};
283			};
284		};
285
286		aux-bus {
287			panel: panel {
288				compatible = "lg,lp120up1";
289				power-supply = <&panel_fixed_3v3>;
290				backlight = <&backlight>;
291
292				port {
293					panel_in: endpoint {
294						remote-endpoint = <&ps8640_out>;
295					};
296				};
297			};
298		};
299	};
300};
301
302&i2c1 {
303	clock-frequency = <1500000>;
304	status = "okay";
305
306	da9211: da9211@68 {
307		compatible = "dlg,da9211";
308		reg = <0x68>;
309		interrupt-parent = <&pio>;
310		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
311
312		regulators {
313			da9211_vcpu_reg: BUCKA {
314				regulator-name = "VBUCKA";
315				regulator-min-microvolt = < 700000>;
316				regulator-max-microvolt = <1310000>;
317				regulator-min-microamp = <2000000>;
318				regulator-max-microamp = <4400000>;
319				regulator-ramp-delay = <10000>;
320				regulator-always-on;
321				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
322							   DA9211_BUCK_MODE_AUTO>;
323			};
324
325			da9211_vgpu_reg: BUCKB {
326				regulator-name = "VBUCKB";
327				regulator-min-microvolt = < 700000>;
328				regulator-max-microvolt = <1310000>;
329				regulator-min-microamp = <2000000>;
330				regulator-max-microamp = <3000000>;
331				regulator-ramp-delay = <10000>;
332			};
333		};
334	};
335};
336
337&i2c2 {
338	status = "okay";
339
340	tpm: tpm@20 {
341		compatible = "infineon,slb9645tt";
342		reg = <0x20>;
343		powered-while-suspended;
344	};
345};
346
347&i2c3 {
348	clock-frequency = <400000>;
349	status = "okay";
350
351	touchscreen: touchscreen@10 {
352		compatible = "elan,ekth3500";
353		reg = <0x10>;
354		interrupt-parent = <&pio>;
355		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
356	};
357};
358
359&i2c4 {
360	clock-frequency = <400000>;
361	status = "okay";
362	pinctrl-names = "default";
363	pinctrl-0 = <&trackpad_irq>;
364
365	trackpad: trackpad@15 {
366		compatible = "elan,ekth3000";
367		interrupt-parent = <&pio>;
368		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
369		reg = <0x15>;
370		vcc-supply = <&mt6397_vgp6_reg>;
371		wakeup-source;
372	};
373};
374
375&mipi_tx0 {
376	status = "okay";
377};
378
379&mmc0 {
380	status = "okay";
381	pinctrl-names = "default", "state_uhs";
382	pinctrl-0 = <&mmc0_pins_default>;
383	pinctrl-1 = <&mmc0_pins_uhs>;
384	bus-width = <8>;
385	max-frequency = <200000000>;
386	cap-mmc-highspeed;
387	mmc-hs200-1_8v;
388	mmc-hs400-1_8v;
389	cap-mmc-hw-reset;
390	hs400-ds-delay = <0x14015>;
391	mediatek,hs200-cmd-int-delay = <30>;
392	mediatek,hs400-cmd-int-delay = <14>;
393	mediatek,hs400-cmd-resp-sel-rising;
394	vmmc-supply = <&mt6397_vemc_3v3_reg>;
395	vqmmc-supply = <&mt6397_vio18_reg>;
396	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
397	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
398	non-removable;
399};
400
401&mmc1 {
402	status = "okay";
403	pinctrl-names = "default", "state_uhs";
404	pinctrl-0 = <&mmc1_pins_default>;
405	pinctrl-1 = <&mmc1_pins_uhs>;
406	bus-width = <4>;
407	max-frequency = <200000000>;
408	cap-sd-highspeed;
409	sd-uhs-sdr50;
410	sd-uhs-sdr104;
411	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
412	vmmc-supply = <&mt6397_vmch_reg>;
413	vqmmc-supply = <&mt6397_vmc_reg>;
414};
415
416&mmc3 {
417	status = "okay";
418	pinctrl-names = "default", "state_uhs";
419	pinctrl-0 = <&mmc3_pins_default>;
420	pinctrl-1 = <&mmc3_pins_uhs>;
421	bus-width = <4>;
422	max-frequency = <200000000>;
423	cap-sd-highspeed;
424	sd-uhs-sdr50;
425	sd-uhs-sdr104;
426	keep-power-in-suspend;
427	wakeup-source;
428	cap-sdio-irq;
429	vmmc-supply = <&sdio_fixed_3v3>;
430	vqmmc-supply = <&mt6397_vgp3_reg>;
431	non-removable;
432	cap-power-off-card;
433
434	#address-cells = <1>;
435	#size-cells = <0>;
436
437	btmrvl: btmrvl@2 {
438		compatible = "marvell,sd8897-bt";
439		reg = <2>;
440		interrupt-parent = <&pio>;
441		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
442		marvell,wakeup-pin = /bits/ 16 <0x0d>;
443		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
444	};
445
446	mwifiex: mwifiex@1 {
447		compatible = "marvell,sd8897";
448		reg = <1>;
449		interrupt-parent = <&pio>;
450		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
451		marvell,wakeup-pin = <3>;
452	};
453};
454
455&nor_flash {
456	status = "okay";
457	pinctrl-names = "default";
458	pinctrl-0 = <&nor_gpio1_pins>;
459
460	flash@0 {
461		compatible = "jedec,spi-nor";
462		reg = <0>;
463		spi-max-frequency = <50000000>;
464	};
465};
466
467&pio {
468	gpio-line-names = "EC_INT_1V8",
469			  "SD_CD_L",
470			  "ALC5514_IRQ",
471			  "ALC5650_IRQ",
472			  /*
473			   * AP_FLASH_WP_L is crossystem ABI. Schematics
474			   * call it SFWP_B.
475			   */
476			  "AP_FLASH_WP_L",
477			  "SFIN",
478			  "SFCS0",
479			  "SFHOLD",
480			  "SFOUT",
481			  "SFCK",
482			  "WRAP_EVENT_S_EINT10",
483			  "PMU_INT",
484			  "I2S2_WS_ALC5650",
485			  "I2S2_BCK_ALC5650",
486			  "PWR_BTN_1V8",
487			  "DA9212_IRQ",
488			  "IDDIG",
489			  "WATCHDOG",
490			  "CEC",
491			  "HDMISCK",
492			  "HDMISD",
493			  "HTPLG",
494			  "MSDC3_DAT0",
495			  "MSDC3_DAT1",
496			  "MSDC3_DAT2",
497			  "MSDC3_DAT3",
498			  "MSDC3_CLK",
499			  "MSDC3_CMD",
500			  "USB_C0_OC_FLAGB",
501			  "USBA_OC1_L",
502			  "PS8640_1V2_ENABLE",
503			  "THERM_ALERT_N",
504			  "PANEL_LCD_POWER_EN",
505			  "ANX7688_CHIP_PD_C",
506			  "EC_IN_RW_1V8",
507			  "ANX7688_1V_EN_C",
508			  "USB_DP_HPD_C",
509			  "TPM_DAVINT_N",
510			  "MARVELL8897_IRQ",
511			  "EN_USB_A0_PWR",
512			  "USBA_A0_OC_L",
513			  "EN_PP3300_DX_EDP",
514			  "",
515			  "SOC_I2C2_1V8_SDA_400K",
516			  "SOC_I2C2_1V8_SCL_400K",
517			  "SOC_I2C0_1V8_SDA_400K",
518			  "SOC_I2C0_1V8_SCL_400K",
519			  "EMMC_ID1",
520			  "EMMC_ID0",
521			  "MEM_CONFIG3",
522			  "EMMC_ID2",
523			  "MEM_CONFIG1",
524			  "MEM_CONFIG2",
525			  "BRD_ID2",
526			  "MEM_CONFIG0",
527			  "BRD_ID0",
528			  "BRD_ID1",
529			  "EMMC_DAT0",
530			  "EMMC_DAT1",
531			  "EMMC_DAT2",
532			  "EMMC_DAT3",
533			  "EMMC_DAT4",
534			  "EMMC_DAT5",
535			  "EMMC_DAT6",
536			  "EMMC_DAT7",
537			  "EMMC_CLK",
538			  "EMMC_CMD",
539			  "EMMC_RCLK",
540			  "PLT_RST_L",
541			  "LID_OPEN_1V8_L",
542			  "AUDIO_SPI_MISO_R",
543			  "",
544			  "AC_OK_1V8",
545			  "SD_DATA0",
546			  "SD_DATA1",
547			  "SD_DATA2",
548			  "SD_DATA3",
549			  "SD_CLK",
550			  "SD_CMD",
551			  "PWRAP_SPI0_MI",
552			  "PWRAP_SPI0_MO",
553			  "PWRAP_SPI0_CK",
554			  "PWRAP_SPI0_CSN",
555			  "",
556			  "",
557			  "WIFI_PDN",
558			  "RTC32K_1V8",
559			  "DISP_PWM0",
560			  "TOUCHSCREEN_INT_L",
561			  "",
562			  "SRCLKENA0",
563			  "SRCLKENA1",
564			  "PS8640_MODE_CONF",
565			  "TOUCHSCREEN_RESET_R",
566			  "PLATFORM_PROCHOT_L",
567			  "PANEL_POWER_EN",
568			  "REC_MODE_L",
569			  "EC_FW_UPDATE_L",
570			  "ACCEL2_INT_L",
571			  "HDMI_DP_INT",
572			  "ACCELGYRO3_INT_L",
573			  "ACCELGYRO4_INT_L",
574			  "SPI_EC_CLK",
575			  "SPI_EC_MI",
576			  "SPI_EC_MO",
577			  "SPI_EC_CSN",
578			  "SOC_I2C3_1V8_SDA_400K",
579			  "SOC_I2C3_1V8_SCL_400K",
580			  "",
581			  "",
582			  "",
583			  "",
584			  "",
585			  "",
586			  "",
587			  "PS8640_SYSRSTN_1V8",
588			  "APIN_MAX98090_DOUT2",
589			  "TP_INT_1V8_L_R",
590			  "RST_USB_HUB_R",
591			  "BT_WAKE_L",
592			  "ACCEL1_INT_L",
593			  "TABLET_MODE_L",
594			  "",
595			  "V_UP_IN_L_R",
596			  "V_DOWN_IN_L_R",
597			  "SOC_I2C1_1V8_SDA_1M",
598			  "SOC_I2C1_1V8_SCL_1M",
599			  "PS8640_PDN_1V8",
600			  "MAX98090_LRCLK",
601			  "MAX98090_BCLK",
602			  "MAX98090_MCLK",
603			  "APOUT_MAX98090_DIN",
604			  "APIN_MAX98090_DOUT",
605			  "SOC_I2C4_1V8_SDA_400K",
606			  "SOC_I2C4_1V8_SCL_400K";
607
608	aud_i2s2: aud_i2s2 {
609		pins1 {
610			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
611				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
612				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
613				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
614				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
615				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
616				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
617			bias-pull-down;
618		};
619	};
620
621	bl_fixed_pins: bl_fixed_pins {
622		pins1 {
623			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
624			output-low;
625		};
626	};
627
628	bt_wake_pins: bt_wake_pins {
629		pins1 {
630			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
631			bias-pull-up;
632		};
633	};
634
635	disp_pwm0_pins: disp_pwm0_pins {
636		pins1 {
637			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
638			output-low;
639		};
640	};
641
642	gpio_keys_pins: gpio_keys_pins {
643		volume_pins {
644			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
645				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
646			bias-pull-up;
647		};
648
649		tablet_mode_pins {
650			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
651			bias-pull-up;
652		};
653	};
654
655	hdmi_mux_pins: hdmi_mux_pins {
656		pins1 {
657			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
658		};
659	};
660
661	i2c1_pins_a: i2c1 {
662		da9211_pins {
663			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
664			bias-pull-up;
665		};
666	};
667
668	mmc0_pins_default: mmc0default {
669		pins_cmd_dat {
670			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
671				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
672				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
673				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
674				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
675				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
676				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
677				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
678				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
679			bias-pull-up;
680		};
681
682		pins_clk {
683			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
684			bias-pull-down;
685		};
686
687		pins_rst {
688			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
689			bias-pull-up;
690		};
691	};
692
693	mmc1_pins_default: mmc1default {
694		pins_cmd_dat {
695			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
696				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
697				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
698				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
699				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
700			input-enable;
701			drive-strength = <MTK_DRIVE_4mA>;
702			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
703		};
704
705		pins_clk {
706			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
707			bias-pull-down;
708			drive-strength = <MTK_DRIVE_4mA>;
709		};
710
711		pins_insert {
712			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
713			bias-pull-up;
714		};
715	};
716
717	mmc3_pins_default: mmc3default {
718		pins_dat {
719			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
720				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
721				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
722				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
723			input-enable;
724			drive-strength = <MTK_DRIVE_8mA>;
725			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
726		};
727
728		pins_cmd {
729			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
730			input-enable;
731			drive-strength = <MTK_DRIVE_8mA>;
732			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
733		};
734
735		pins_clk {
736			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
737			bias-pull-down;
738			drive-strength = <MTK_DRIVE_8mA>;
739		};
740	};
741
742	mmc0_pins_uhs: mmc0 {
743		pins_cmd_dat {
744			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
745				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
746				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
747				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
748				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
749				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
750				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
751				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
752				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
753			input-enable;
754			drive-strength = <MTK_DRIVE_6mA>;
755			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
756		};
757
758		pins_clk {
759			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
760			drive-strength = <MTK_DRIVE_6mA>;
761			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
762		};
763
764		pins_ds {
765			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
766			drive-strength = <MTK_DRIVE_10mA>;
767			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
768		};
769
770		pins_rst {
771			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
772			bias-pull-up;
773		};
774	};
775
776	mmc1_pins_uhs: mmc1 {
777		pins_cmd_dat {
778			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
779				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
780				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
781				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
782				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
783			input-enable;
784			drive-strength = <MTK_DRIVE_6mA>;
785			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
786		};
787
788		pins_clk {
789			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
790			drive-strength = <MTK_DRIVE_8mA>;
791			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
792		};
793	};
794
795	mmc3_pins_uhs: mmc3 {
796		pins_dat {
797			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
798				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
799				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
800				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
801			input-enable;
802			drive-strength = <MTK_DRIVE_8mA>;
803			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
804		};
805
806		pins_cmd {
807			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
808			input-enable;
809			drive-strength = <MTK_DRIVE_8mA>;
810			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
811		};
812
813		pins_clk {
814			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
815			drive-strength = <MTK_DRIVE_8mA>;
816			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
817		};
818	};
819
820	nor_gpio1_pins: nor {
821		pins1 {
822			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
823				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
824				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
825			input-enable;
826			drive-strength = <MTK_DRIVE_4mA>;
827			bias-pull-up;
828		};
829
830		pins2 {
831			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
832			drive-strength = <MTK_DRIVE_4mA>;
833			bias-pull-up;
834		};
835
836		pins_clk {
837			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
838			input-enable;
839			drive-strength = <MTK_DRIVE_4mA>;
840			bias-pull-up;
841		};
842	};
843
844	panel_backlight_en_pins: panel_backlight_en_pins {
845		pins1 {
846			pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
847		};
848	};
849
850	panel_fixed_pins: panel_fixed_pins {
851		pins1 {
852			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
853		};
854	};
855
856	ps8640_pins: ps8640_pins {
857		pins1 {
858			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
859				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
860				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
861		};
862	};
863
864	ps8640_fixed_pins: ps8640_fixed_pins {
865		pins1 {
866			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
867		};
868	};
869
870	rt5650_irq: rt5650_irq {
871		pins1 {
872			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
873			bias-pull-down;
874		};
875	};
876
877	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
878		pins1 {
879			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
880			output-low;
881		};
882	};
883
884	spi_pins_a: spi1 {
885		pins1 {
886			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
887			bias-pull-up;
888		};
889
890		pins_spi {
891			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
892				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
893				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
894				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
895			bias-disable;
896		};
897	};
898
899	trackpad_irq: trackpad_irq {
900		pins1 {
901			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
902			input-enable;
903			bias-pull-up;
904		};
905	};
906
907	usb_pins: usb {
908		pins1 {
909			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
910			output-high;
911			bias-disable;
912		};
913	};
914
915	wifi_wake_pins: wifi_wake_pins {
916		pins1 {
917			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
918			bias-pull-up;
919		};
920	};
921};
922
923&pwm0 {
924	pinctrl-names = "default";
925	pinctrl-0 = <&disp_pwm0_pins>;
926	status = "okay";
927};
928
929&pwrap {
930	pmic: pmic {
931		compatible = "mediatek,mt6397";
932		#address-cells = <1>;
933		#size-cells = <1>;
934		interrupt-parent = <&pio>;
935		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
936		interrupt-controller;
937		#interrupt-cells = <2>;
938
939		clock: mt6397clock {
940			compatible = "mediatek,mt6397-clk";
941			#clock-cells = <1>;
942		};
943
944		pio6397: pinctrl {
945			compatible = "mediatek,mt6397-pinctrl";
946			gpio-controller;
947			#gpio-cells = <2>;
948		};
949
950		regulator: mt6397regulator {
951			compatible = "mediatek,mt6397-regulator";
952
953			mt6397_vpca15_reg: buck_vpca15 {
954				regulator-compatible = "buck_vpca15";
955				regulator-name = "vpca15";
956				regulator-min-microvolt = < 700000>;
957				regulator-max-microvolt = <1350000>;
958				regulator-ramp-delay = <12500>;
959				regulator-always-on;
960				regulator-allowed-modes = <0 1>;
961			};
962
963			mt6397_vpca7_reg: buck_vpca7 {
964				regulator-compatible = "buck_vpca7";
965				regulator-name = "vpca7";
966				regulator-min-microvolt = < 700000>;
967				regulator-max-microvolt = <1350000>;
968				regulator-ramp-delay = <12500>;
969				regulator-enable-ramp-delay = <115>;
970				regulator-always-on;
971			};
972
973			mt6397_vsramca15_reg: buck_vsramca15 {
974				regulator-compatible = "buck_vsramca15";
975				regulator-name = "vsramca15";
976				regulator-min-microvolt = < 700000>;
977				regulator-max-microvolt = <1350000>;
978				regulator-ramp-delay = <12500>;
979				regulator-always-on;
980			};
981
982			mt6397_vsramca7_reg: buck_vsramca7 {
983				regulator-compatible = "buck_vsramca7";
984				regulator-name = "vsramca7";
985				regulator-min-microvolt = < 700000>;
986				regulator-max-microvolt = <1350000>;
987				regulator-ramp-delay = <12500>;
988				regulator-always-on;
989			};
990
991			mt6397_vcore_reg: buck_vcore {
992				regulator-compatible = "buck_vcore";
993				regulator-name = "vcore";
994				regulator-min-microvolt = < 700000>;
995				regulator-max-microvolt = <1350000>;
996				regulator-ramp-delay = <12500>;
997				regulator-always-on;
998			};
999
1000			mt6397_vgpu_reg: buck_vgpu {
1001				regulator-compatible = "buck_vgpu";
1002				regulator-name = "vgpu";
1003				regulator-min-microvolt = < 700000>;
1004				regulator-max-microvolt = <1350000>;
1005				regulator-ramp-delay = <12500>;
1006				regulator-enable-ramp-delay = <115>;
1007			};
1008
1009			mt6397_vdrm_reg: buck_vdrm {
1010				regulator-compatible = "buck_vdrm";
1011				regulator-name = "vdrm";
1012				regulator-min-microvolt = <1200000>;
1013				regulator-max-microvolt = <1400000>;
1014				regulator-ramp-delay = <12500>;
1015				regulator-always-on;
1016			};
1017
1018			mt6397_vio18_reg: buck_vio18 {
1019				regulator-compatible = "buck_vio18";
1020				regulator-name = "vio18";
1021				regulator-min-microvolt = <1620000>;
1022				regulator-max-microvolt = <1980000>;
1023				regulator-ramp-delay = <12500>;
1024				regulator-always-on;
1025			};
1026
1027			mt6397_vtcxo_reg: ldo_vtcxo {
1028				regulator-compatible = "ldo_vtcxo";
1029				regulator-name = "vtcxo";
1030				regulator-always-on;
1031			};
1032
1033			mt6397_va28_reg: ldo_va28 {
1034				regulator-compatible = "ldo_va28";
1035				regulator-name = "va28";
1036			};
1037
1038			mt6397_vcama_reg: ldo_vcama {
1039				regulator-compatible = "ldo_vcama";
1040				regulator-name = "vcama";
1041				regulator-min-microvolt = <1800000>;
1042				regulator-max-microvolt = <1800000>;
1043				regulator-enable-ramp-delay = <218>;
1044			};
1045
1046			mt6397_vio28_reg: ldo_vio28 {
1047				regulator-compatible = "ldo_vio28";
1048				regulator-name = "vio28";
1049				regulator-always-on;
1050			};
1051
1052			mt6397_vusb_reg: ldo_vusb {
1053				regulator-compatible = "ldo_vusb";
1054				regulator-name = "vusb";
1055			};
1056
1057			mt6397_vmc_reg: ldo_vmc {
1058				regulator-compatible = "ldo_vmc";
1059				regulator-name = "vmc";
1060				regulator-min-microvolt = <1800000>;
1061				regulator-max-microvolt = <3300000>;
1062				regulator-enable-ramp-delay = <218>;
1063			};
1064
1065			mt6397_vmch_reg: ldo_vmch {
1066				regulator-compatible = "ldo_vmch";
1067				regulator-name = "vmch";
1068				regulator-min-microvolt = <3000000>;
1069				regulator-max-microvolt = <3300000>;
1070				regulator-enable-ramp-delay = <218>;
1071			};
1072
1073			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
1074				regulator-compatible = "ldo_vemc3v3";
1075				regulator-name = "vemc_3v3";
1076				regulator-min-microvolt = <3000000>;
1077				regulator-max-microvolt = <3300000>;
1078				regulator-enable-ramp-delay = <218>;
1079			};
1080
1081			mt6397_vgp1_reg: ldo_vgp1 {
1082				regulator-compatible = "ldo_vgp1";
1083				regulator-name = "vcamd";
1084				regulator-min-microvolt = <1800000>;
1085				regulator-max-microvolt = <1800000>;
1086				regulator-enable-ramp-delay = <240>;
1087			};
1088
1089			mt6397_vgp2_reg: ldo_vgp2 {
1090				regulator-compatible = "ldo_vgp2";
1091				regulator-name = "vcamio";
1092				regulator-min-microvolt = <3300000>;
1093				regulator-max-microvolt = <3300000>;
1094				regulator-enable-ramp-delay = <218>;
1095			};
1096
1097			mt6397_vgp3_reg: ldo_vgp3 {
1098				regulator-compatible = "ldo_vgp3";
1099				regulator-name = "vcamaf";
1100				regulator-min-microvolt = <1800000>;
1101				regulator-max-microvolt = <1800000>;
1102				regulator-enable-ramp-delay = <218>;
1103			};
1104
1105			mt6397_vgp4_reg: ldo_vgp4 {
1106				regulator-compatible = "ldo_vgp4";
1107				regulator-name = "vgp4";
1108				regulator-min-microvolt = <1200000>;
1109				regulator-max-microvolt = <3300000>;
1110				regulator-enable-ramp-delay = <218>;
1111			};
1112
1113			mt6397_vgp5_reg: ldo_vgp5 {
1114				regulator-compatible = "ldo_vgp5";
1115				regulator-name = "vgp5";
1116				regulator-min-microvolt = <1200000>;
1117				regulator-max-microvolt = <3000000>;
1118				regulator-enable-ramp-delay = <218>;
1119			};
1120
1121			mt6397_vgp6_reg: ldo_vgp6 {
1122				regulator-compatible = "ldo_vgp6";
1123				regulator-name = "vgp6";
1124				regulator-min-microvolt = <3300000>;
1125				regulator-max-microvolt = <3300000>;
1126				regulator-enable-ramp-delay = <218>;
1127				regulator-always-on;
1128			};
1129
1130			mt6397_vibr_reg: ldo_vibr {
1131				regulator-compatible = "ldo_vibr";
1132				regulator-name = "vibr";
1133				regulator-min-microvolt = <1300000>;
1134				regulator-max-microvolt = <3300000>;
1135				regulator-enable-ramp-delay = <218>;
1136			};
1137		};
1138
1139		rtc: mt6397rtc {
1140			compatible = "mediatek,mt6397-rtc";
1141		};
1142
1143		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
1144			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
1145				     "syscon";
1146			reg = <0 0x0000c000 0 0x0108>;
1147		};
1148	};
1149};
1150
1151&spi {
1152	pinctrl-names = "default";
1153	pinctrl-0 = <&spi_pins_a>;
1154	mediatek,pad-select = <1>;
1155	status = "okay";
1156	/* clients */
1157	cros_ec: ec@0 {
1158		compatible = "google,cros-ec-spi";
1159		reg = <0x0>;
1160		spi-max-frequency = <12000000>;
1161		interrupt-parent = <&pio>;
1162		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1163		google,cros-ec-spi-msg-delay = <500>;
1164
1165		i2c_tunnel: i2c-tunnel0 {
1166			compatible = "google,cros-ec-i2c-tunnel";
1167			google,remote-bus = <0>;
1168			#address-cells = <1>;
1169			#size-cells = <0>;
1170
1171			battery: sbs-battery@b {
1172				compatible = "sbs,sbs-battery";
1173				reg = <0xb>;
1174				sbs,i2c-retry-count = <2>;
1175				sbs,poll-retry-count = <1>;
1176			};
1177		};
1178	};
1179};
1180
1181&ssusb {
1182	dr_mode = "host";
1183	wakeup-source;
1184	vusb33-supply = <&mt6397_vusb_reg>;
1185	status = "okay";
1186};
1187
1188&thermal {
1189	bank0-supply = <&mt6397_vpca15_reg>;
1190	bank1-supply = <&da9211_vcpu_reg>;
1191};
1192
1193&uart0 {
1194	status = "okay";
1195};
1196
1197&usb_host {
1198	pinctrl-names = "default";
1199	pinctrl-0 = <&usb_pins>;
1200	vusb33-supply = <&mt6397_vusb_reg>;
1201	status = "okay";
1202};
1203
1204#include <arm/cros-ec-keyboard.dtsi>
1205