xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt8173-elm.dtsi (revision 9f44a47fd07924afc035991af15d84e6585dea4f) 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2016 MediaTek Inc.
4 */
5
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/regulator/dlg,da9211-regulator.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "mt8173.dtsi"
11
12/ {
13	aliases {
14		mmc0 = &mmc0;
15		mmc1 = &mmc1;
16		mmc2 = &mmc3;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0 0x40000000 0 0x80000000>;
22	};
23
24	backlight: backlight {
25		compatible = "pwm-backlight";
26		pwms = <&pwm0 0 1000000>;
27		power-supply = <&bl_fixed_reg>;
28		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
29
30		pinctrl-names = "default";
31		pinctrl-0 = <&panel_backlight_en_pins>;
32		status = "okay";
33	};
34
35	bl_fixed_reg: fixedregulator2 {
36		compatible = "regulator-fixed";
37		regulator-name = "bl_fixed";
38		regulator-min-microvolt = <1800000>;
39		regulator-max-microvolt = <1800000>;
40		startup-delay-us = <1000>;
41		enable-active-high;
42		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
43		pinctrl-names = "default";
44		pinctrl-0 = <&bl_fixed_pins>;
45	};
46
47	chosen {
48		stdout-path = "serial0:115200n8";
49	};
50
51	gpio_keys: gpio-keys {
52		compatible = "gpio-keys";
53		pinctrl-names = "default";
54		pinctrl-0 = <&gpio_keys_pins>;
55
56		switch-lid {
57			label = "Lid";
58			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
59			linux,code = <SW_LID>;
60			linux,input-type = <EV_SW>;
61			gpio-key,wakeup;
62		};
63
64		switch-power {
65			label = "Power";
66			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
67			linux,code = <KEY_POWER>;
68			debounce-interval = <30>;
69			gpio-key,wakeup;
70		};
71
72		switch-tablet-mode {
73			label = "Tablet_mode";
74			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
75			linux,code = <SW_TABLET_MODE>;
76			linux,input-type = <EV_SW>;
77			gpio-key,wakeup;
78		};
79
80		switch-volume-down {
81			label = "Volume_down";
82			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
83			linux,code = <KEY_VOLUMEDOWN>;
84		};
85
86		switch-volume-up {
87			label = "Volume_up";
88			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
89			linux,code = <KEY_VOLUMEUP>;
90		};
91	};
92
93	panel: panel {
94		compatible = "lg,lp120up1";
95		power-supply = <&panel_fixed_3v3>;
96		backlight = <&backlight>;
97
98		port {
99			panel_in: endpoint {
100				remote-endpoint = <&ps8640_out>;
101			};
102		};
103	};
104
105	panel_fixed_3v3: regulator1 {
106		compatible = "regulator-fixed";
107		regulator-name = "PANEL_3V3";
108		regulator-min-microvolt = <3300000>;
109		regulator-max-microvolt = <3300000>;
110		enable-active-high;
111		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
112		pinctrl-names = "default";
113		pinctrl-0 = <&panel_fixed_pins>;
114	};
115
116	ps8640_fixed_1v2: regulator2 {
117		compatible = "regulator-fixed";
118		regulator-name = "PS8640_1V2";
119		regulator-min-microvolt = <1200000>;
120		regulator-max-microvolt = <1200000>;
121		regulator-enable-ramp-delay = <2000>;
122		enable-active-high;
123		regulator-boot-on;
124		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
125		pinctrl-names = "default";
126		pinctrl-0 = <&ps8640_fixed_pins>;
127	};
128
129	sdio_fixed_3v3: fixedregulator0 {
130		compatible = "regulator-fixed";
131		regulator-name = "3V3";
132		regulator-min-microvolt = <3300000>;
133		regulator-max-microvolt = <3300000>;
134		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
135		pinctrl-names = "default";
136		pinctrl-0 = <&sdio_fixed_3v3_pins>;
137	};
138
139	sound: sound {
140		compatible = "mediatek,mt8173-rt5650";
141		mediatek,audio-codec = <&rt5650 &hdmi0>;
142		mediatek,platform = <&afe>;
143		pinctrl-names = "default";
144		pinctrl-0 = <&aud_i2s2>;
145
146		mediatek,mclk = <1>;
147		codec-capture {
148			sound-dai = <&rt5650 1>;
149		};
150	};
151
152	hdmicon: connector {
153		compatible = "hdmi-connector";
154		label = "hdmi";
155		type = "a";
156		ddc-i2c-bus = <&hdmiddc0>;
157
158		port {
159			hdmi_connector_in: endpoint {
160				remote-endpoint = <&hdmi0_out>;
161			};
162		};
163	};
164};
165
166&mfg_async {
167	domain-supply = <&da9211_vgpu_reg>;
168};
169
170&cec {
171	status = "okay";
172};
173
174&cpu0 {
175	proc-supply = <&mt6397_vpca15_reg>;
176};
177
178&cpu1 {
179	proc-supply = <&mt6397_vpca15_reg>;
180};
181
182&cpu2 {
183	proc-supply = <&da9211_vcpu_reg>;
184	sram-supply = <&mt6397_vsramca7_reg>;
185};
186
187&cpu3 {
188	proc-supply = <&da9211_vcpu_reg>;
189	sram-supply = <&mt6397_vsramca7_reg>;
190};
191
192&cpu_thermal {
193	sustainable-power = <4500>; /* milliwatts */
194	trips {
195		threshold: trip-point0 {
196			temperature = <60000>;
197		};
198
199		target: trip-point1 {
200			temperature = <65000>;
201		};
202	};
203};
204
205&dsi0 {
206	status = "okay";
207	ports {
208		port {
209			dsi0_out: endpoint {
210				remote-endpoint = <&ps8640_in>;
211			};
212		};
213	};
214};
215
216&dpi0 {
217	status = "okay";
218};
219
220&hdmi0 {
221	status = "okay";
222	ports {
223		port@1 {
224			reg = <1>;
225
226			hdmi0_out: endpoint {
227				remote-endpoint = <&hdmi_connector_in>;
228			};
229		};
230	};
231};
232
233&hdmi_phy {
234	status = "okay";
235	mediatek,ibias = <0xc>;
236};
237
238&i2c0 {
239	status = "okay";
240
241	rt5650: audio-codec@1a {
242		compatible = "realtek,rt5650";
243		reg = <0x1a>;
244		avdd-supply = <&mt6397_vgp1_reg>;
245		cpvdd-supply = <&mt6397_vcama_reg>;
246		interrupt-parent = <&pio>;
247		interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
248		pinctrl-names = "default";
249		pinctrl-0 = <&rt5650_irq>;
250		#sound-dai-cells = <1>;
251		realtek,dmic1-data-pin = <2>;
252		realtek,jd-mode = <2>;
253	};
254
255	ps8640: edp-bridge@8 {
256		compatible = "parade,ps8640";
257		reg = <0x8>;
258		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
259		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
260		pinctrl-names = "default";
261		pinctrl-0 = <&ps8640_pins>;
262		vdd12-supply = <&ps8640_fixed_1v2>;
263		vdd33-supply = <&mt6397_vgp2_reg>;
264
265		ports {
266			#address-cells = <1>;
267			#size-cells = <0>;
268
269			port@0 {
270				reg = <0>;
271
272				ps8640_in: endpoint {
273					remote-endpoint = <&dsi0_out>;
274				};
275			};
276
277			port@1 {
278				reg = <1>;
279
280				ps8640_out: endpoint {
281					remote-endpoint = <&panel_in>;
282				};
283			};
284		};
285	};
286};
287
288&i2c1 {
289	clock-frequency = <1500000>;
290	status = "okay";
291
292	da9211: da9211@68 {
293		compatible = "dlg,da9211";
294		reg = <0x68>;
295		interrupt-parent = <&pio>;
296		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
297
298		regulators {
299			da9211_vcpu_reg: BUCKA {
300				regulator-name = "VBUCKA";
301				regulator-min-microvolt = < 700000>;
302				regulator-max-microvolt = <1310000>;
303				regulator-min-microamp = <2000000>;
304				regulator-max-microamp = <4400000>;
305				regulator-ramp-delay = <10000>;
306				regulator-always-on;
307				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
308							   DA9211_BUCK_MODE_AUTO>;
309			};
310
311			da9211_vgpu_reg: BUCKB {
312				regulator-name = "VBUCKB";
313				regulator-min-microvolt = < 700000>;
314				regulator-max-microvolt = <1310000>;
315				regulator-min-microamp = <2000000>;
316				regulator-max-microamp = <3000000>;
317				regulator-ramp-delay = <10000>;
318			};
319		};
320	};
321};
322
323&i2c2 {
324	status = "okay";
325
326	tpm: tpm@20 {
327		compatible = "infineon,slb9645tt";
328		reg = <0x20>;
329		powered-while-suspended;
330	};
331};
332
333&i2c3 {
334	clock-frequency = <400000>;
335	status = "okay";
336
337	touchscreen: touchscreen@10 {
338		compatible = "elan,ekth3500";
339		reg = <0x10>;
340		interrupt-parent = <&pio>;
341		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
342	};
343};
344
345&i2c4 {
346	clock-frequency = <400000>;
347	status = "okay";
348	pinctrl-names = "default";
349	pinctrl-0 = <&trackpad_irq>;
350
351	trackpad: trackpad@15 {
352		compatible = "elan,ekth3000";
353		interrupt-parent = <&pio>;
354		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
355		reg = <0x15>;
356		vcc-supply = <&mt6397_vgp6_reg>;
357		wakeup-source;
358	};
359};
360
361&mipi_tx0 {
362	status = "okay";
363};
364
365&mmc0 {
366	status = "okay";
367	pinctrl-names = "default", "state_uhs";
368	pinctrl-0 = <&mmc0_pins_default>;
369	pinctrl-1 = <&mmc0_pins_uhs>;
370	bus-width = <8>;
371	max-frequency = <200000000>;
372	cap-mmc-highspeed;
373	mmc-hs200-1_8v;
374	mmc-hs400-1_8v;
375	cap-mmc-hw-reset;
376	hs400-ds-delay = <0x14015>;
377	mediatek,hs200-cmd-int-delay = <30>;
378	mediatek,hs400-cmd-int-delay = <14>;
379	mediatek,hs400-cmd-resp-sel-rising;
380	vmmc-supply = <&mt6397_vemc_3v3_reg>;
381	vqmmc-supply = <&mt6397_vio18_reg>;
382	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
383	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
384	non-removable;
385};
386
387&mmc1 {
388	status = "okay";
389	pinctrl-names = "default", "state_uhs";
390	pinctrl-0 = <&mmc1_pins_default>;
391	pinctrl-1 = <&mmc1_pins_uhs>;
392	bus-width = <4>;
393	max-frequency = <200000000>;
394	cap-sd-highspeed;
395	sd-uhs-sdr50;
396	sd-uhs-sdr104;
397	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
398	vmmc-supply = <&mt6397_vmch_reg>;
399	vqmmc-supply = <&mt6397_vmc_reg>;
400};
401
402&mmc3 {
403	status = "okay";
404	pinctrl-names = "default", "state_uhs";
405	pinctrl-0 = <&mmc3_pins_default>;
406	pinctrl-1 = <&mmc3_pins_uhs>;
407	bus-width = <4>;
408	max-frequency = <200000000>;
409	cap-sd-highspeed;
410	sd-uhs-sdr50;
411	sd-uhs-sdr104;
412	keep-power-in-suspend;
413	wakeup-source;
414	cap-sdio-irq;
415	vmmc-supply = <&sdio_fixed_3v3>;
416	vqmmc-supply = <&mt6397_vgp3_reg>;
417	non-removable;
418	cap-power-off-card;
419
420	#address-cells = <1>;
421	#size-cells = <0>;
422
423	btmrvl: btmrvl@2 {
424		compatible = "marvell,sd8897-bt";
425		reg = <2>;
426		interrupt-parent = <&pio>;
427		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
428		marvell,wakeup-pin = /bits/ 16 <0x0d>;
429		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
430	};
431
432	mwifiex: mwifiex@1 {
433		compatible = "marvell,sd8897";
434		reg = <1>;
435		interrupt-parent = <&pio>;
436		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
437		marvell,wakeup-pin = <3>;
438	};
439};
440
441&nor_flash {
442	status = "okay";
443	pinctrl-names = "default";
444	pinctrl-0 = <&nor_gpio1_pins>;
445
446	flash@0 {
447		compatible = "jedec,spi-nor";
448		reg = <0>;
449		spi-max-frequency = <50000000>;
450	};
451};
452
453&pio {
454	gpio-line-names = "EC_INT_1V8",
455			  "SD_CD_L",
456			  "ALC5514_IRQ",
457			  "ALC5650_IRQ",
458			  /*
459			   * AP_FLASH_WP_L is crossystem ABI. Schematics
460			   * call it SFWP_B.
461			   */
462			  "AP_FLASH_WP_L",
463			  "SFIN",
464			  "SFCS0",
465			  "SFHOLD",
466			  "SFOUT",
467			  "SFCK",
468			  "WRAP_EVENT_S_EINT10",
469			  "PMU_INT",
470			  "I2S2_WS_ALC5650",
471			  "I2S2_BCK_ALC5650",
472			  "PWR_BTN_1V8",
473			  "DA9212_IRQ",
474			  "IDDIG",
475			  "WATCHDOG",
476			  "CEC",
477			  "HDMISCK",
478			  "HDMISD",
479			  "HTPLG",
480			  "MSDC3_DAT0",
481			  "MSDC3_DAT1",
482			  "MSDC3_DAT2",
483			  "MSDC3_DAT3",
484			  "MSDC3_CLK",
485			  "MSDC3_CMD",
486			  "USB_C0_OC_FLAGB",
487			  "USBA_OC1_L",
488			  "PS8640_1V2_ENABLE",
489			  "THERM_ALERT_N",
490			  "PANEL_LCD_POWER_EN",
491			  "ANX7688_CHIP_PD_C",
492			  "EC_IN_RW_1V8",
493			  "ANX7688_1V_EN_C",
494			  "USB_DP_HPD_C",
495			  "TPM_DAVINT_N",
496			  "MARVELL8897_IRQ",
497			  "EN_USB_A0_PWR",
498			  "USBA_A0_OC_L",
499			  "EN_PP3300_DX_EDP",
500			  "",
501			  "SOC_I2C2_1V8_SDA_400K",
502			  "SOC_I2C2_1V8_SCL_400K",
503			  "SOC_I2C0_1V8_SDA_400K",
504			  "SOC_I2C0_1V8_SCL_400K",
505			  "EMMC_ID1",
506			  "EMMC_ID0",
507			  "MEM_CONFIG3",
508			  "EMMC_ID2",
509			  "MEM_CONFIG1",
510			  "MEM_CONFIG2",
511			  "BRD_ID2",
512			  "MEM_CONFIG0",
513			  "BRD_ID0",
514			  "BRD_ID1",
515			  "EMMC_DAT0",
516			  "EMMC_DAT1",
517			  "EMMC_DAT2",
518			  "EMMC_DAT3",
519			  "EMMC_DAT4",
520			  "EMMC_DAT5",
521			  "EMMC_DAT6",
522			  "EMMC_DAT7",
523			  "EMMC_CLK",
524			  "EMMC_CMD",
525			  "EMMC_RCLK",
526			  "PLT_RST_L",
527			  "LID_OPEN_1V8_L",
528			  "AUDIO_SPI_MISO_R",
529			  "",
530			  "AC_OK_1V8",
531			  "SD_DATA0",
532			  "SD_DATA1",
533			  "SD_DATA2",
534			  "SD_DATA3",
535			  "SD_CLK",
536			  "SD_CMD",
537			  "PWRAP_SPI0_MI",
538			  "PWRAP_SPI0_MO",
539			  "PWRAP_SPI0_CK",
540			  "PWRAP_SPI0_CSN",
541			  "",
542			  "",
543			  "WIFI_PDN",
544			  "RTC32K_1V8",
545			  "DISP_PWM0",
546			  "TOUCHSCREEN_INT_L",
547			  "",
548			  "SRCLKENA0",
549			  "SRCLKENA1",
550			  "PS8640_MODE_CONF",
551			  "TOUCHSCREEN_RESET_R",
552			  "PLATFORM_PROCHOT_L",
553			  "PANEL_POWER_EN",
554			  "REC_MODE_L",
555			  "EC_FW_UPDATE_L",
556			  "ACCEL2_INT_L",
557			  "HDMI_DP_INT",
558			  "ACCELGYRO3_INT_L",
559			  "ACCELGYRO4_INT_L",
560			  "SPI_EC_CLK",
561			  "SPI_EC_MI",
562			  "SPI_EC_MO",
563			  "SPI_EC_CSN",
564			  "SOC_I2C3_1V8_SDA_400K",
565			  "SOC_I2C3_1V8_SCL_400K",
566			  "",
567			  "",
568			  "",
569			  "",
570			  "",
571			  "",
572			  "",
573			  "PS8640_SYSRSTN_1V8",
574			  "APIN_MAX98090_DOUT2",
575			  "TP_INT_1V8_L_R",
576			  "RST_USB_HUB_R",
577			  "BT_WAKE_L",
578			  "ACCEL1_INT_L",
579			  "TABLET_MODE_L",
580			  "",
581			  "V_UP_IN_L_R",
582			  "V_DOWN_IN_L_R",
583			  "SOC_I2C1_1V8_SDA_1M",
584			  "SOC_I2C1_1V8_SCL_1M",
585			  "PS8640_PDN_1V8",
586			  "MAX98090_LRCLK",
587			  "MAX98090_BCLK",
588			  "MAX98090_MCLK",
589			  "APOUT_MAX98090_DIN",
590			  "APIN_MAX98090_DOUT",
591			  "SOC_I2C4_1V8_SDA_400K",
592			  "SOC_I2C4_1V8_SCL_400K";
593
594	aud_i2s2: aud_i2s2 {
595		pins1 {
596			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
597				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
598				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
599				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
600				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
601				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
602				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
603			bias-pull-down;
604		};
605	};
606
607	bl_fixed_pins: bl_fixed_pins {
608		pins1 {
609			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
610			output-low;
611		};
612	};
613
614	bt_wake_pins: bt_wake_pins {
615		pins1 {
616			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
617			bias-pull-up;
618		};
619	};
620
621	disp_pwm0_pins: disp_pwm0_pins {
622		pins1 {
623			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
624			output-low;
625		};
626	};
627
628	gpio_keys_pins: gpio_keys_pins {
629		volume_pins {
630			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
631				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
632			bias-pull-up;
633		};
634
635		tablet_mode_pins {
636			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
637			bias-pull-up;
638		};
639	};
640
641	hdmi_mux_pins: hdmi_mux_pins {
642		pins1 {
643			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
644		};
645	};
646
647	i2c1_pins_a: i2c1 {
648		da9211_pins {
649			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
650			bias-pull-up;
651		};
652	};
653
654	mmc0_pins_default: mmc0default {
655		pins_cmd_dat {
656			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
657				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
658				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
659				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
660				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
661				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
662				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
663				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
664				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
665			bias-pull-up;
666		};
667
668		pins_clk {
669			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
670			bias-pull-down;
671		};
672
673		pins_rst {
674			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
675			bias-pull-up;
676		};
677	};
678
679	mmc1_pins_default: mmc1default {
680		pins_cmd_dat {
681			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
682				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
683				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
684				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
685				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
686			input-enable;
687			drive-strength = <MTK_DRIVE_4mA>;
688			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
689		};
690
691		pins_clk {
692			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
693			bias-pull-down;
694			drive-strength = <MTK_DRIVE_4mA>;
695		};
696
697		pins_insert {
698			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
699			bias-pull-up;
700		};
701	};
702
703	mmc3_pins_default: mmc3default {
704		pins_dat {
705			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
706				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
707				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
708				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
709			input-enable;
710			drive-strength = <MTK_DRIVE_8mA>;
711			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
712		};
713
714		pins_cmd {
715			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
716			input-enable;
717			drive-strength = <MTK_DRIVE_8mA>;
718			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
719		};
720
721		pins_clk {
722			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
723			bias-pull-down;
724			drive-strength = <MTK_DRIVE_8mA>;
725		};
726	};
727
728	mmc0_pins_uhs: mmc0 {
729		pins_cmd_dat {
730			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
731				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
732				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
733				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
734				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
735				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
736				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
737				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
738				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
739			input-enable;
740			drive-strength = <MTK_DRIVE_6mA>;
741			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
742		};
743
744		pins_clk {
745			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
746			drive-strength = <MTK_DRIVE_6mA>;
747			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
748		};
749
750		pins_ds {
751			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
752			drive-strength = <MTK_DRIVE_10mA>;
753			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
754		};
755
756		pins_rst {
757			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
758			bias-pull-up;
759		};
760	};
761
762	mmc1_pins_uhs: mmc1 {
763		pins_cmd_dat {
764			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
765				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
766				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
767				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
768				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
769			input-enable;
770			drive-strength = <MTK_DRIVE_6mA>;
771			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
772		};
773
774		pins_clk {
775			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
776			drive-strength = <MTK_DRIVE_8mA>;
777			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
778		};
779	};
780
781	mmc3_pins_uhs: mmc3 {
782		pins_dat {
783			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
784				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
785				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
786				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
787			input-enable;
788			drive-strength = <MTK_DRIVE_8mA>;
789			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
790		};
791
792		pins_cmd {
793			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
794			input-enable;
795			drive-strength = <MTK_DRIVE_8mA>;
796			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
797		};
798
799		pins_clk {
800			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
801			drive-strength = <MTK_DRIVE_8mA>;
802			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
803		};
804	};
805
806	nor_gpio1_pins: nor {
807		pins1 {
808			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
809				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
810				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
811			input-enable;
812			drive-strength = <MTK_DRIVE_4mA>;
813			bias-pull-up;
814		};
815
816		pins2 {
817			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
818			drive-strength = <MTK_DRIVE_4mA>;
819			bias-pull-up;
820		};
821
822		pins_clk {
823			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
824			input-enable;
825			drive-strength = <MTK_DRIVE_4mA>;
826			bias-pull-up;
827		};
828	};
829
830	panel_backlight_en_pins: panel_backlight_en_pins {
831		pins1 {
832			pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
833		};
834	};
835
836	panel_fixed_pins: panel_fixed_pins {
837		pins1 {
838			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
839		};
840	};
841
842	ps8640_pins: ps8640_pins {
843		pins1 {
844			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
845				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
846				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
847		};
848	};
849
850	ps8640_fixed_pins: ps8640_fixed_pins {
851		pins1 {
852			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
853		};
854	};
855
856	rt5650_irq: rt5650_irq {
857		pins1 {
858			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
859			bias-pull-down;
860		};
861	};
862
863	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
864		pins1 {
865			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
866			output-low;
867		};
868	};
869
870	spi_pins_a: spi1 {
871		pins1 {
872			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
873			bias-pull-up;
874		};
875
876		pins_spi {
877			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
878				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
879				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
880				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
881			bias-disable;
882		};
883	};
884
885	trackpad_irq: trackpad_irq {
886		pins1 {
887			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
888			input-enable;
889			bias-pull-up;
890		};
891	};
892
893	usb_pins: usb {
894		pins1 {
895			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
896			output-high;
897			bias-disable;
898		};
899	};
900
901	wifi_wake_pins: wifi_wake_pins {
902		pins1 {
903			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
904			bias-pull-up;
905		};
906	};
907};
908
909&pwm0 {
910	pinctrl-names = "default";
911	pinctrl-0 = <&disp_pwm0_pins>;
912	status = "okay";
913};
914
915&pwrap {
916	pmic: mt6397 {
917		compatible = "mediatek,mt6397";
918		#address-cells = <1>;
919		#size-cells = <1>;
920		interrupt-parent = <&pio>;
921		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
922		interrupt-controller;
923		#interrupt-cells = <2>;
924
925		clock: mt6397clock {
926			compatible = "mediatek,mt6397-clk";
927			#clock-cells = <1>;
928		};
929
930		pio6397: pinctrl {
931			compatible = "mediatek,mt6397-pinctrl";
932			pins-are-numbered;
933			gpio-controller;
934			#gpio-cells = <2>;
935		};
936
937		regulator: mt6397regulator {
938			compatible = "mediatek,mt6397-regulator";
939
940			mt6397_vpca15_reg: buck_vpca15 {
941				regulator-compatible = "buck_vpca15";
942				regulator-name = "vpca15";
943				regulator-min-microvolt = < 700000>;
944				regulator-max-microvolt = <1350000>;
945				regulator-ramp-delay = <12500>;
946				regulator-always-on;
947				regulator-allowed-modes = <0 1>;
948			};
949
950			mt6397_vpca7_reg: buck_vpca7 {
951				regulator-compatible = "buck_vpca7";
952				regulator-name = "vpca7";
953				regulator-min-microvolt = < 700000>;
954				regulator-max-microvolt = <1350000>;
955				regulator-ramp-delay = <12500>;
956				regulator-enable-ramp-delay = <115>;
957				regulator-always-on;
958			};
959
960			mt6397_vsramca15_reg: buck_vsramca15 {
961				regulator-compatible = "buck_vsramca15";
962				regulator-name = "vsramca15";
963				regulator-min-microvolt = < 700000>;
964				regulator-max-microvolt = <1350000>;
965				regulator-ramp-delay = <12500>;
966				regulator-always-on;
967			};
968
969			mt6397_vsramca7_reg: buck_vsramca7 {
970				regulator-compatible = "buck_vsramca7";
971				regulator-name = "vsramca7";
972				regulator-min-microvolt = < 700000>;
973				regulator-max-microvolt = <1350000>;
974				regulator-ramp-delay = <12500>;
975				regulator-always-on;
976			};
977
978			mt6397_vcore_reg: buck_vcore {
979				regulator-compatible = "buck_vcore";
980				regulator-name = "vcore";
981				regulator-min-microvolt = < 700000>;
982				regulator-max-microvolt = <1350000>;
983				regulator-ramp-delay = <12500>;
984				regulator-always-on;
985			};
986
987			mt6397_vgpu_reg: buck_vgpu {
988				regulator-compatible = "buck_vgpu";
989				regulator-name = "vgpu";
990				regulator-min-microvolt = < 700000>;
991				regulator-max-microvolt = <1350000>;
992				regulator-ramp-delay = <12500>;
993				regulator-enable-ramp-delay = <115>;
994			};
995
996			mt6397_vdrm_reg: buck_vdrm {
997				regulator-compatible = "buck_vdrm";
998				regulator-name = "vdrm";
999				regulator-min-microvolt = <1200000>;
1000				regulator-max-microvolt = <1400000>;
1001				regulator-ramp-delay = <12500>;
1002				regulator-always-on;
1003			};
1004
1005			mt6397_vio18_reg: buck_vio18 {
1006				regulator-compatible = "buck_vio18";
1007				regulator-name = "vio18";
1008				regulator-min-microvolt = <1620000>;
1009				regulator-max-microvolt = <1980000>;
1010				regulator-ramp-delay = <12500>;
1011				regulator-always-on;
1012			};
1013
1014			mt6397_vtcxo_reg: ldo_vtcxo {
1015				regulator-compatible = "ldo_vtcxo";
1016				regulator-name = "vtcxo";
1017				regulator-always-on;
1018			};
1019
1020			mt6397_va28_reg: ldo_va28 {
1021				regulator-compatible = "ldo_va28";
1022				regulator-name = "va28";
1023			};
1024
1025			mt6397_vcama_reg: ldo_vcama {
1026				regulator-compatible = "ldo_vcama";
1027				regulator-name = "vcama";
1028				regulator-min-microvolt = <1800000>;
1029				regulator-max-microvolt = <1800000>;
1030				regulator-enable-ramp-delay = <218>;
1031			};
1032
1033			mt6397_vio28_reg: ldo_vio28 {
1034				regulator-compatible = "ldo_vio28";
1035				regulator-name = "vio28";
1036				regulator-always-on;
1037			};
1038
1039			mt6397_vusb_reg: ldo_vusb {
1040				regulator-compatible = "ldo_vusb";
1041				regulator-name = "vusb";
1042			};
1043
1044			mt6397_vmc_reg: ldo_vmc {
1045				regulator-compatible = "ldo_vmc";
1046				regulator-name = "vmc";
1047				regulator-min-microvolt = <1800000>;
1048				regulator-max-microvolt = <3300000>;
1049				regulator-enable-ramp-delay = <218>;
1050			};
1051
1052			mt6397_vmch_reg: ldo_vmch {
1053				regulator-compatible = "ldo_vmch";
1054				regulator-name = "vmch";
1055				regulator-min-microvolt = <3000000>;
1056				regulator-max-microvolt = <3300000>;
1057				regulator-enable-ramp-delay = <218>;
1058			};
1059
1060			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
1061				regulator-compatible = "ldo_vemc3v3";
1062				regulator-name = "vemc_3v3";
1063				regulator-min-microvolt = <3000000>;
1064				regulator-max-microvolt = <3300000>;
1065				regulator-enable-ramp-delay = <218>;
1066			};
1067
1068			mt6397_vgp1_reg: ldo_vgp1 {
1069				regulator-compatible = "ldo_vgp1";
1070				regulator-name = "vcamd";
1071				regulator-min-microvolt = <1800000>;
1072				regulator-max-microvolt = <1800000>;
1073				regulator-enable-ramp-delay = <240>;
1074			};
1075
1076			mt6397_vgp2_reg: ldo_vgp2 {
1077				regulator-compatible = "ldo_vgp2";
1078				regulator-name = "vcamio";
1079				regulator-min-microvolt = <3300000>;
1080				regulator-max-microvolt = <3300000>;
1081				regulator-enable-ramp-delay = <218>;
1082			};
1083
1084			mt6397_vgp3_reg: ldo_vgp3 {
1085				regulator-compatible = "ldo_vgp3";
1086				regulator-name = "vcamaf";
1087				regulator-min-microvolt = <1800000>;
1088				regulator-max-microvolt = <1800000>;
1089				regulator-enable-ramp-delay = <218>;
1090			};
1091
1092			mt6397_vgp4_reg: ldo_vgp4 {
1093				regulator-compatible = "ldo_vgp4";
1094				regulator-name = "vgp4";
1095				regulator-min-microvolt = <1200000>;
1096				regulator-max-microvolt = <3300000>;
1097				regulator-enable-ramp-delay = <218>;
1098			};
1099
1100			mt6397_vgp5_reg: ldo_vgp5 {
1101				regulator-compatible = "ldo_vgp5";
1102				regulator-name = "vgp5";
1103				regulator-min-microvolt = <1200000>;
1104				regulator-max-microvolt = <3000000>;
1105				regulator-enable-ramp-delay = <218>;
1106			};
1107
1108			mt6397_vgp6_reg: ldo_vgp6 {
1109				regulator-compatible = "ldo_vgp6";
1110				regulator-name = "vgp6";
1111				regulator-min-microvolt = <3300000>;
1112				regulator-max-microvolt = <3300000>;
1113				regulator-enable-ramp-delay = <218>;
1114				regulator-always-on;
1115			};
1116
1117			mt6397_vibr_reg: ldo_vibr {
1118				regulator-compatible = "ldo_vibr";
1119				regulator-name = "vibr";
1120				regulator-min-microvolt = <1300000>;
1121				regulator-max-microvolt = <3300000>;
1122				regulator-enable-ramp-delay = <218>;
1123			};
1124		};
1125
1126		rtc: mt6397rtc {
1127			compatible = "mediatek,mt6397-rtc";
1128		};
1129
1130		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
1131			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
1132				     "syscon";
1133			reg = <0 0x0000c000 0 0x0108>;
1134		};
1135	};
1136};
1137
1138&spi {
1139	pinctrl-names = "default";
1140	pinctrl-0 = <&spi_pins_a>;
1141	mediatek,pad-select = <1>;
1142	status = "okay";
1143	/* clients */
1144	cros_ec: ec@0 {
1145		compatible = "google,cros-ec-spi";
1146		reg = <0x0>;
1147		spi-max-frequency = <12000000>;
1148		interrupt-parent = <&pio>;
1149		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1150		google,cros-ec-spi-msg-delay = <500>;
1151
1152		i2c_tunnel: i2c-tunnel0 {
1153			compatible = "google,cros-ec-i2c-tunnel";
1154			google,remote-bus = <0>;
1155			#address-cells = <1>;
1156			#size-cells = <0>;
1157
1158			battery: sbs-battery@b {
1159				compatible = "sbs,sbs-battery";
1160				reg = <0xb>;
1161				sbs,i2c-retry-count = <2>;
1162				sbs,poll-retry-count = <1>;
1163			};
1164		};
1165	};
1166};
1167
1168&ssusb {
1169	dr_mode = "host";
1170	wakeup-source;
1171	vusb33-supply = <&mt6397_vusb_reg>;
1172	status = "okay";
1173};
1174
1175&thermal {
1176	bank0-supply = <&mt6397_vpca15_reg>;
1177	bank1-supply = <&da9211_vcpu_reg>;
1178};
1179
1180&uart0 {
1181	status = "okay";
1182};
1183
1184&usb_host {
1185	pinctrl-names = "default";
1186	pinctrl-0 = <&usb_pins>;
1187	vusb33-supply = <&mt6397_vusb_reg>;
1188	status = "okay";
1189};
1190
1191#include <arm/cros-ec-keyboard.dtsi>
1192