1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2020 MediaTek Inc. 4 * Copyright (c) 2020 BayLibre, SAS. 5 * Author: Fabien Parent <fparent@baylibre.com> 6 */ 7 8#include <dt-bindings/clock/mt8167-clk.h> 9#include <dt-bindings/memory/mt8167-larb-port.h> 10 11#include "mt8167-pinfunc.h" 12 13#include "mt8516.dtsi" 14 15/ { 16 compatible = "mediatek,mt8167"; 17 18 soc { 19 topckgen: topckgen@10000000 { 20 compatible = "mediatek,mt8167-topckgen", "syscon"; 21 reg = <0 0x10000000 0 0x1000>; 22 #clock-cells = <1>; 23 }; 24 25 infracfg: infracfg@10001000 { 26 compatible = "mediatek,mt8167-infracfg", "syscon"; 27 reg = <0 0x10001000 0 0x1000>; 28 #clock-cells = <1>; 29 }; 30 31 apmixedsys: apmixedsys@10018000 { 32 compatible = "mediatek,mt8167-apmixedsys", "syscon"; 33 reg = <0 0x10018000 0 0x710>; 34 #clock-cells = <1>; 35 }; 36 37 imgsys: syscon@15000000 { 38 compatible = "mediatek,mt8167-imgsys", "syscon"; 39 reg = <0 0x15000000 0 0x1000>; 40 #clock-cells = <1>; 41 }; 42 43 vdecsys: syscon@16000000 { 44 compatible = "mediatek,mt8167-vdecsys", "syscon"; 45 reg = <0 0x16000000 0 0x1000>; 46 #clock-cells = <1>; 47 }; 48 49 pio: pinctrl@1000b000 { 50 compatible = "mediatek,mt8167-pinctrl"; 51 reg = <0 0x1000b000 0 0x1000>; 52 mediatek,pctl-regmap = <&syscfg_pctl>; 53 pins-are-numbered; 54 gpio-controller; 55 #gpio-cells = <2>; 56 interrupt-controller; 57 #interrupt-cells = <2>; 58 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 59 }; 60 }; 61}; 62