xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt7986a-bananapi-bpi-r3.dts (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Authors: Sam.Shih <sam.shih@mediatek.com>
5 *          Frank Wunderlich <frank-w@public-files.de>
6 *          Daniel Golle <daniel@makrotopia.org>
7 */
8
9/dts-v1/;
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/leds/common.h>
13#include <dt-bindings/pinctrl/mt65xx.h>
14
15#include "mt7986a.dtsi"
16
17/ {
18	model = "Bananapi BPI-R3";
19	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
20
21	aliases {
22		serial0 = &uart0;
23		ethernet0 = &gmac0;
24		ethernet1 = &gmac1;
25	};
26
27	chosen {
28		stdout-path = "serial0:115200n8";
29	};
30
31	dcin: regulator-12vd {
32		compatible = "regulator-fixed";
33		regulator-name = "12vd";
34		regulator-min-microvolt = <12000000>;
35		regulator-max-microvolt = <12000000>;
36		regulator-boot-on;
37		regulator-always-on;
38	};
39
40	gpio-keys {
41		compatible = "gpio-keys";
42
43		reset-key {
44			label = "reset";
45			linux,code = <KEY_RESTART>;
46			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
47		};
48
49		wps-key {
50			label = "wps";
51			linux,code = <KEY_WPS_BUTTON>;
52			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
53		};
54	};
55
56	/* i2c of the left SFP cage (wan) */
57	i2c_sfp1: i2c-gpio-0 {
58		compatible = "i2c-gpio";
59		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
60		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
61		i2c-gpio,delay-us = <2>;
62		#address-cells = <1>;
63		#size-cells = <0>;
64	};
65
66	/* i2c of the right SFP cage (lan) */
67	i2c_sfp2: i2c-gpio-1 {
68		compatible = "i2c-gpio";
69		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
70		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
71		i2c-gpio,delay-us = <2>;
72		#address-cells = <1>;
73		#size-cells = <0>;
74	};
75
76	leds {
77		compatible = "gpio-leds";
78
79		green_led: led-0 {
80			color = <LED_COLOR_ID_GREEN>;
81			function = LED_FUNCTION_POWER;
82			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
83			default-state = "on";
84		};
85
86		blue_led: led-1 {
87			color = <LED_COLOR_ID_BLUE>;
88			function = LED_FUNCTION_STATUS;
89			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
90			default-state = "off";
91		};
92	};
93
94	reg_1p8v: regulator-1p8v {
95		compatible = "regulator-fixed";
96		regulator-name = "1.8vd";
97		regulator-min-microvolt = <1800000>;
98		regulator-max-microvolt = <1800000>;
99		regulator-boot-on;
100		regulator-always-on;
101		vin-supply = <&dcin>;
102	};
103
104	reg_3p3v: regulator-3p3v {
105		compatible = "regulator-fixed";
106		regulator-name = "3.3vd";
107		regulator-min-microvolt = <3300000>;
108		regulator-max-microvolt = <3300000>;
109		regulator-boot-on;
110		regulator-always-on;
111		vin-supply = <&dcin>;
112	};
113
114	/* left SFP cage (wan) */
115	sfp1: sfp-1 {
116		compatible = "sff,sfp";
117		i2c-bus = <&i2c_sfp1>;
118		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
119		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
120		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
121		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
122	};
123
124	/* right SFP cage (lan) */
125	sfp2: sfp-2 {
126		compatible = "sff,sfp";
127		i2c-bus = <&i2c_sfp2>;
128		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
129		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
130		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
131		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
132	};
133};
134
135&crypto {
136	status = "okay";
137};
138
139&eth {
140	status = "okay";
141
142	gmac0: mac@0 {
143		compatible = "mediatek,eth-mac";
144		reg = <0>;
145		phy-mode = "2500base-x";
146
147		fixed-link {
148			speed = <2500>;
149			full-duplex;
150			pause;
151		};
152	};
153
154	gmac1: mac@1 {
155		compatible = "mediatek,eth-mac";
156		reg = <1>;
157		phy-mode = "2500base-x";
158		sfp = <&sfp1>;
159		managed = "in-band-status";
160	};
161
162	mdio: mdio-bus {
163		#address-cells = <1>;
164		#size-cells = <0>;
165	};
166};
167
168&mdio {
169	switch: switch@31 {
170		compatible = "mediatek,mt7531";
171		reg = <31>;
172		interrupt-controller;
173		#interrupt-cells = <1>;
174		interrupt-parent = <&pio>;
175		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
176		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
177	};
178};
179
180&mmc0 {
181	pinctrl-names = "default", "state_uhs";
182	pinctrl-0 = <&mmc0_pins_default>;
183	pinctrl-1 = <&mmc0_pins_uhs>;
184	vmmc-supply = <&reg_3p3v>;
185	vqmmc-supply = <&reg_1p8v>;
186};
187
188&i2c0 {
189	pinctrl-names = "default";
190	pinctrl-0 = <&i2c_pins>;
191	status = "okay";
192};
193
194&pcie {
195	pinctrl-names = "default";
196	pinctrl-0 = <&pcie_pins>;
197	status = "okay";
198};
199
200&pcie_phy {
201	status = "okay";
202};
203
204&pio {
205	i2c_pins: i2c-pins {
206		mux {
207			function = "i2c";
208			groups = "i2c";
209		};
210	};
211
212	mmc0_pins_default: mmc0-pins {
213		mux {
214			function = "emmc";
215			groups = "emmc_51";
216		};
217		conf-cmd-dat {
218			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
219			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
220			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
221			input-enable;
222			drive-strength = <4>;
223			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
224		};
225		conf-clk {
226			pins = "EMMC_CK";
227			drive-strength = <6>;
228			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
229		};
230		conf-ds {
231			pins = "EMMC_DSL";
232			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
233		};
234		conf-rst {
235			pins = "EMMC_RSTB";
236			drive-strength = <4>;
237			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
238		};
239	};
240
241	mmc0_pins_uhs: mmc0-uhs-pins {
242		mux {
243			function = "emmc";
244			groups = "emmc_51";
245		};
246		conf-cmd-dat {
247			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
248			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
249			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
250			input-enable;
251			drive-strength = <4>;
252			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
253		};
254		conf-clk {
255			pins = "EMMC_CK";
256			drive-strength = <6>;
257			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
258		};
259		conf-ds {
260			pins = "EMMC_DSL";
261			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
262		};
263		conf-rst {
264			pins = "EMMC_RSTB";
265			drive-strength = <4>;
266			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
267		};
268	};
269
270	pcie_pins: pcie-pins {
271		mux {
272			function = "pcie";
273			groups = "pcie_clk", "pcie_pereset";
274		};
275	};
276
277	spi_flash_pins: spi-flash-pins {
278		mux {
279			function = "spi";
280			groups = "spi0", "spi0_wp_hold";
281		};
282	};
283
284	spic_pins: spic-pins {
285		mux {
286			function = "spi";
287			groups = "spi1_0";
288		};
289	};
290
291	uart1_pins: uart1-pins {
292		mux {
293			function = "uart";
294			groups = "uart1_rx_tx";
295		};
296	};
297
298	uart2_pins: uart2-pins {
299		mux {
300			function = "uart";
301			groups = "uart2_0_rx_tx";
302		};
303	};
304
305	wf_2g_5g_pins: wf-2g-5g-pins {
306		mux {
307			function = "wifi";
308			groups = "wf_2g", "wf_5g";
309		};
310		conf {
311			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
312			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
313			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
314			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
315			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
316			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
317			       "WF1_TOP_CLK", "WF1_TOP_DATA";
318			drive-strength = <4>;
319		};
320	};
321
322	wf_dbdc_pins: wf-dbdc-pins {
323		mux {
324			function = "wifi";
325			groups = "wf_dbdc";
326		};
327		conf {
328			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
329			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
330			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
331			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
332			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
333			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
334			       "WF1_TOP_CLK", "WF1_TOP_DATA";
335			drive-strength = <4>;
336		};
337	};
338
339	wf_led_pins: wf-led-pins {
340		mux {
341			function = "led";
342			groups = "wifi_led";
343		};
344	};
345};
346
347&spi0 {
348	pinctrl-names = "default";
349	pinctrl-0 = <&spi_flash_pins>;
350	status = "okay";
351};
352
353&spi1 {
354	pinctrl-names = "default";
355	pinctrl-0 = <&spic_pins>;
356	status = "okay";
357};
358
359&ssusb {
360	status = "okay";
361};
362
363&switch {
364	ports {
365		#address-cells = <1>;
366		#size-cells = <0>;
367
368		port@0 {
369			reg = <0>;
370			label = "wan";
371		};
372
373		port@1 {
374			reg = <1>;
375			label = "lan0";
376		};
377
378		port@2 {
379			reg = <2>;
380			label = "lan1";
381		};
382
383		port@3 {
384			reg = <3>;
385			label = "lan2";
386		};
387
388		port@4 {
389			reg = <4>;
390			label = "lan3";
391		};
392
393		port5: port@5 {
394			reg = <5>;
395			label = "lan4";
396			phy-mode = "2500base-x";
397			sfp = <&sfp2>;
398			managed = "in-band-status";
399		};
400
401		port@6 {
402			reg = <6>;
403			label = "cpu";
404			ethernet = <&gmac0>;
405			phy-mode = "2500base-x";
406
407			fixed-link {
408				speed = <2500>;
409				full-duplex;
410				pause;
411			};
412		};
413	};
414};
415
416&trng {
417	status = "okay";
418};
419
420&uart0 {
421	status = "okay";
422};
423
424&uart1 {
425	pinctrl-names = "default";
426	pinctrl-0 = <&uart1_pins>;
427	status = "okay";
428};
429
430&uart2 {
431	pinctrl-names = "default";
432	pinctrl-0 = <&uart2_pins>;
433	status = "okay";
434};
435
436&usb_phy {
437	status = "okay";
438};
439
440&watchdog {
441	status = "okay";
442};
443
444&wifi {
445	status = "okay";
446	pinctrl-names = "default", "dbdc";
447	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
448	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
449};
450
451