1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/mt7622-clk.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/power/mt7622-power.h> 14#include <dt-bindings/reset/mt7622-reset.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 compatible = "mediatek,mt7622"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpu_opp_table: opp-table { 24 compatible = "operating-points-v2"; 25 opp-shared; 26 opp-300000000 { 27 opp-hz = /bits/ 64 <30000000>; 28 opp-microvolt = <950000>; 29 }; 30 31 opp-437500000 { 32 opp-hz = /bits/ 64 <437500000>; 33 opp-microvolt = <1000000>; 34 }; 35 36 opp-600000000 { 37 opp-hz = /bits/ 64 <600000000>; 38 opp-microvolt = <1050000>; 39 }; 40 41 opp-812500000 { 42 opp-hz = /bits/ 64 <812500000>; 43 opp-microvolt = <1100000>; 44 }; 45 46 opp-1025000000 { 47 opp-hz = /bits/ 64 <1025000000>; 48 opp-microvolt = <1150000>; 49 }; 50 51 opp-1137500000 { 52 opp-hz = /bits/ 64 <1137500000>; 53 opp-microvolt = <1200000>; 54 }; 55 56 opp-1262500000 { 57 opp-hz = /bits/ 64 <1262500000>; 58 opp-microvolt = <1250000>; 59 }; 60 61 opp-1350000000 { 62 opp-hz = /bits/ 64 <1350000000>; 63 opp-microvolt = <1310000>; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <2>; 69 #size-cells = <0>; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x0 0x0>; 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; 77 clock-names = "cpu", "intermediate"; 78 operating-points-v2 = <&cpu_opp_table>; 79 #cooling-cells = <2>; 80 enable-method = "psci"; 81 clock-frequency = <1300000000>; 82 cci-control-port = <&cci_control2>; 83 next-level-cache = <&L2>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x0 0x1>; 90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 91 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; 92 clock-names = "cpu", "intermediate"; 93 operating-points-v2 = <&cpu_opp_table>; 94 #cooling-cells = <2>; 95 enable-method = "psci"; 96 clock-frequency = <1300000000>; 97 cci-control-port = <&cci_control2>; 98 next-level-cache = <&L2>; 99 }; 100 101 L2: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 }; 106 }; 107 108 pwrap_clk: dummy40m { 109 compatible = "fixed-clock"; 110 clock-frequency = <40000000>; 111 #clock-cells = <0>; 112 }; 113 114 clk25m: oscillator { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <25000000>; 118 clock-output-names = "clkxtal"; 119 }; 120 121 psci { 122 compatible = "arm,psci-0.2"; 123 method = "smc"; 124 }; 125 126 pmu { 127 compatible = "arm,cortex-a53-pmu"; 128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 129 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 130 interrupt-affinity = <&cpu0>, <&cpu1>; 131 }; 132 133 reserved-memory { 134 #address-cells = <2>; 135 #size-cells = <2>; 136 ranges; 137 138 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 139 secmon_reserved: secmon@43000000 { 140 reg = <0 0x43000000 0 0x30000>; 141 no-map; 142 }; 143 }; 144 145 thermal-zones { 146 cpu_thermal: cpu-thermal { 147 polling-delay-passive = <1000>; 148 polling-delay = <1000>; 149 150 thermal-sensors = <&thermal 0>; 151 152 trips { 153 cpu_passive: cpu-passive { 154 temperature = <47000>; 155 hysteresis = <2000>; 156 type = "passive"; 157 }; 158 159 cpu_active: cpu-active { 160 temperature = <67000>; 161 hysteresis = <2000>; 162 type = "active"; 163 }; 164 165 cpu_hot: cpu-hot { 166 temperature = <87000>; 167 hysteresis = <2000>; 168 type = "hot"; 169 }; 170 171 cpu-crit { 172 temperature = <107000>; 173 hysteresis = <2000>; 174 type = "critical"; 175 }; 176 }; 177 178 cooling-maps { 179 map0 { 180 trip = <&cpu_passive>; 181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 182 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 183 }; 184 185 map1 { 186 trip = <&cpu_active>; 187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 189 }; 190 191 map2 { 192 trip = <&cpu_hot>; 193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 195 }; 196 }; 197 }; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupt-parent = <&gic>; 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 204 IRQ_TYPE_LEVEL_HIGH)>, 205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 206 IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 208 IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 210 IRQ_TYPE_LEVEL_HIGH)>; 211 }; 212 213 infracfg: infracfg@10000000 { 214 compatible = "mediatek,mt7622-infracfg", 215 "syscon"; 216 reg = <0 0x10000000 0 0x1000>; 217 #clock-cells = <1>; 218 #reset-cells = <1>; 219 }; 220 221 pwrap: pwrap@10001000 { 222 compatible = "mediatek,mt7622-pwrap"; 223 reg = <0 0x10001000 0 0x250>; 224 reg-names = "pwrap"; 225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; 226 clock-names = "spi", "wrap"; 227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; 228 reset-names = "pwrap"; 229 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 230 status = "disabled"; 231 }; 232 233 pericfg: pericfg@10002000 { 234 compatible = "mediatek,mt7622-pericfg", 235 "syscon"; 236 reg = <0 0x10002000 0 0x1000>; 237 #clock-cells = <1>; 238 #reset-cells = <1>; 239 }; 240 241 scpsys: power-controller@10006000 { 242 compatible = "mediatek,mt7622-scpsys", 243 "syscon"; 244 #power-domain-cells = <1>; 245 reg = <0 0x10006000 0 0x1000>; 246 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>, 247 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>, 248 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>, 249 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 250 infracfg = <&infracfg>; 251 clocks = <&topckgen CLK_TOP_HIF_SEL>; 252 clock-names = "hif_sel"; 253 }; 254 255 cir: cir@10009000 { 256 compatible = "mediatek,mt7622-cir"; 257 reg = <0 0x10009000 0 0x1000>; 258 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; 259 clocks = <&infracfg CLK_INFRA_IRRX_PD>, 260 <&topckgen CLK_TOP_AXI_SEL>; 261 clock-names = "clk", "bus"; 262 status = "disabled"; 263 }; 264 265 sysirq: interrupt-controller@10200620 { 266 compatible = "mediatek,mt7622-sysirq", 267 "mediatek,mt6577-sysirq"; 268 interrupt-controller; 269 #interrupt-cells = <3>; 270 interrupt-parent = <&gic>; 271 reg = <0 0x10200620 0 0x20>; 272 }; 273 274 efuse: efuse@10206000 { 275 compatible = "mediatek,mt7622-efuse", 276 "mediatek,efuse"; 277 reg = <0 0x10206000 0 0x1000>; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 281 thermal_calibration: calib@198 { 282 reg = <0x198 0xc>; 283 }; 284 }; 285 286 apmixedsys: apmixedsys@10209000 { 287 compatible = "mediatek,mt7622-apmixedsys", 288 "syscon"; 289 reg = <0 0x10209000 0 0x1000>; 290 #clock-cells = <1>; 291 }; 292 293 topckgen: topckgen@10210000 { 294 compatible = "mediatek,mt7622-topckgen", 295 "syscon"; 296 reg = <0 0x10210000 0 0x1000>; 297 #clock-cells = <1>; 298 }; 299 300 rng: rng@1020f000 { 301 compatible = "mediatek,mt7622-rng", 302 "mediatek,mt7623-rng"; 303 reg = <0 0x1020f000 0 0x1000>; 304 clocks = <&infracfg CLK_INFRA_TRNG>; 305 clock-names = "rng"; 306 }; 307 308 pio: pinctrl@10211000 { 309 compatible = "mediatek,mt7622-pinctrl"; 310 reg = <0 0x10211000 0 0x1000>, 311 <0 0x10005000 0 0x1000>; 312 reg-names = "base", "eint"; 313 gpio-controller; 314 #gpio-cells = <2>; 315 gpio-ranges = <&pio 0 0 103>; 316 interrupt-controller; 317 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-parent = <&gic>; 319 #interrupt-cells = <2>; 320 }; 321 322 watchdog: watchdog@10212000 { 323 compatible = "mediatek,mt7622-wdt", 324 "mediatek,mt6589-wdt"; 325 reg = <0 0x10212000 0 0x800>; 326 }; 327 328 rtc: rtc@10212800 { 329 compatible = "mediatek,mt7622-rtc", 330 "mediatek,soc-rtc"; 331 reg = <0 0x10212800 0 0x200>; 332 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 333 clocks = <&topckgen CLK_TOP_RTC>; 334 clock-names = "rtc"; 335 }; 336 337 gic: interrupt-controller@10300000 { 338 compatible = "arm,gic-400"; 339 interrupt-controller; 340 #interrupt-cells = <3>; 341 interrupt-parent = <&gic>; 342 reg = <0 0x10310000 0 0x1000>, 343 <0 0x10320000 0 0x1000>, 344 <0 0x10340000 0 0x2000>, 345 <0 0x10360000 0 0x2000>; 346 }; 347 348 cci: cci@10390000 { 349 compatible = "arm,cci-400"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 reg = <0 0x10390000 0 0x1000>; 353 ranges = <0 0 0x10390000 0x10000>; 354 355 cci_control0: slave-if@1000 { 356 compatible = "arm,cci-400-ctrl-if"; 357 interface-type = "ace-lite"; 358 reg = <0x1000 0x1000>; 359 }; 360 361 cci_control1: slave-if@4000 { 362 compatible = "arm,cci-400-ctrl-if"; 363 interface-type = "ace"; 364 reg = <0x4000 0x1000>; 365 }; 366 367 cci_control2: slave-if@5000 { 368 compatible = "arm,cci-400-ctrl-if", "syscon"; 369 interface-type = "ace"; 370 reg = <0x5000 0x1000>; 371 }; 372 373 pmu@9000 { 374 compatible = "arm,cci-400-pmu,r1"; 375 reg = <0x9000 0x5000>; 376 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 }; 383 384 auxadc: adc@11001000 { 385 compatible = "mediatek,mt7622-auxadc"; 386 reg = <0 0x11001000 0 0x1000>; 387 clocks = <&pericfg CLK_PERI_AUXADC_PD>; 388 clock-names = "main"; 389 #io-channel-cells = <1>; 390 }; 391 392 uart0: serial@11002000 { 393 compatible = "mediatek,mt7622-uart", 394 "mediatek,mt6577-uart"; 395 reg = <0 0x11002000 0 0x400>; 396 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 397 clocks = <&topckgen CLK_TOP_UART_SEL>, 398 <&pericfg CLK_PERI_UART0_PD>; 399 clock-names = "baud", "bus"; 400 status = "disabled"; 401 }; 402 403 uart1: serial@11003000 { 404 compatible = "mediatek,mt7622-uart", 405 "mediatek,mt6577-uart"; 406 reg = <0 0x11003000 0 0x400>; 407 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 408 clocks = <&topckgen CLK_TOP_UART_SEL>, 409 <&pericfg CLK_PERI_UART1_PD>; 410 clock-names = "baud", "bus"; 411 status = "disabled"; 412 }; 413 414 uart2: serial@11004000 { 415 compatible = "mediatek,mt7622-uart", 416 "mediatek,mt6577-uart"; 417 reg = <0 0x11004000 0 0x400>; 418 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 419 clocks = <&topckgen CLK_TOP_UART_SEL>, 420 <&pericfg CLK_PERI_UART2_PD>; 421 clock-names = "baud", "bus"; 422 status = "disabled"; 423 }; 424 425 uart3: serial@11005000 { 426 compatible = "mediatek,mt7622-uart", 427 "mediatek,mt6577-uart"; 428 reg = <0 0x11005000 0 0x400>; 429 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 430 clocks = <&topckgen CLK_TOP_UART_SEL>, 431 <&pericfg CLK_PERI_UART3_PD>; 432 clock-names = "baud", "bus"; 433 status = "disabled"; 434 }; 435 436 pwm: pwm@11006000 { 437 compatible = "mediatek,mt7622-pwm"; 438 reg = <0 0x11006000 0 0x1000>; 439 #pwm-cells = <2>; 440 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 441 clocks = <&topckgen CLK_TOP_PWM_SEL>, 442 <&pericfg CLK_PERI_PWM_PD>, 443 <&pericfg CLK_PERI_PWM1_PD>, 444 <&pericfg CLK_PERI_PWM2_PD>, 445 <&pericfg CLK_PERI_PWM3_PD>, 446 <&pericfg CLK_PERI_PWM4_PD>, 447 <&pericfg CLK_PERI_PWM5_PD>, 448 <&pericfg CLK_PERI_PWM6_PD>; 449 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", 450 "pwm5", "pwm6"; 451 status = "disabled"; 452 }; 453 454 i2c0: i2c@11007000 { 455 compatible = "mediatek,mt7622-i2c"; 456 reg = <0 0x11007000 0 0x90>, 457 <0 0x11000100 0 0x80>; 458 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 459 clock-div = <16>; 460 clocks = <&pericfg CLK_PERI_I2C0_PD>, 461 <&pericfg CLK_PERI_AP_DMA_PD>; 462 clock-names = "main", "dma"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c1: i2c@11008000 { 469 compatible = "mediatek,mt7622-i2c"; 470 reg = <0 0x11008000 0 0x90>, 471 <0 0x11000180 0 0x80>; 472 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 473 clock-div = <16>; 474 clocks = <&pericfg CLK_PERI_I2C1_PD>, 475 <&pericfg CLK_PERI_AP_DMA_PD>; 476 clock-names = "main", "dma"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 i2c2: i2c@11009000 { 483 compatible = "mediatek,mt7622-i2c"; 484 reg = <0 0x11009000 0 0x90>, 485 <0 0x11000200 0 0x80>; 486 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 487 clock-div = <16>; 488 clocks = <&pericfg CLK_PERI_I2C2_PD>, 489 <&pericfg CLK_PERI_AP_DMA_PD>; 490 clock-names = "main", "dma"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 spi0: spi@1100a000 { 497 compatible = "mediatek,mt7622-spi"; 498 reg = <0 0x1100a000 0 0x100>; 499 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 500 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 501 <&topckgen CLK_TOP_SPI0_SEL>, 502 <&pericfg CLK_PERI_SPI0_PD>; 503 clock-names = "parent-clk", "sel-clk", "spi-clk"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 status = "disabled"; 507 }; 508 509 thermal: thermal@1100b000 { 510 #thermal-sensor-cells = <1>; 511 compatible = "mediatek,mt7622-thermal"; 512 reg = <0 0x1100b000 0 0x1000>; 513 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; 514 clocks = <&pericfg CLK_PERI_THERM_PD>, 515 <&pericfg CLK_PERI_AUXADC_PD>; 516 clock-names = "therm", "auxadc"; 517 resets = <&pericfg MT7622_PERI_THERM_SW_RST>; 518 reset-names = "therm"; 519 mediatek,auxadc = <&auxadc>; 520 mediatek,apmixedsys = <&apmixedsys>; 521 nvmem-cells = <&thermal_calibration>; 522 nvmem-cell-names = "calibration-data"; 523 }; 524 525 btif: serial@1100c000 { 526 compatible = "mediatek,mt7622-btif", 527 "mediatek,mtk-btif"; 528 reg = <0 0x1100c000 0 0x1000>; 529 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&pericfg CLK_PERI_BTIF_PD>; 531 reg-shift = <2>; 532 reg-io-width = <4>; 533 status = "disabled"; 534 535 bluetooth { 536 compatible = "mediatek,mt7622-bluetooth"; 537 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; 538 clocks = <&clk25m>; 539 clock-names = "ref"; 540 }; 541 }; 542 543 nandc: nand-controller@1100d000 { 544 compatible = "mediatek,mt7622-nfc"; 545 reg = <0 0x1100D000 0 0x1000>; 546 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 547 clocks = <&pericfg CLK_PERI_NFI_PD>, 548 <&pericfg CLK_PERI_SNFI_PD>; 549 clock-names = "nfi_clk", "pad_clk"; 550 ecc-engine = <&bch>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 snfi: spi@1100d000 { 557 compatible = "mediatek,mt7622-snand"; 558 reg = <0 0x1100d000 0 0x1000>; 559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 560 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; 561 clock-names = "nfi_clk", "pad_clk"; 562 nand-ecc-engine = <&bch>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 568 bch: ecc@1100e000 { 569 compatible = "mediatek,mt7622-ecc"; 570 reg = <0 0x1100e000 0 0x1000>; 571 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 572 clocks = <&pericfg CLK_PERI_NFIECC_PD>; 573 clock-names = "nfiecc_clk"; 574 status = "disabled"; 575 }; 576 577 nor_flash: spi@11014000 { 578 compatible = "mediatek,mt7622-nor", 579 "mediatek,mt8173-nor"; 580 reg = <0 0x11014000 0 0xe0>; 581 clocks = <&pericfg CLK_PERI_FLASH_PD>, 582 <&topckgen CLK_TOP_FLASH_SEL>; 583 clock-names = "spi", "sf"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 status = "disabled"; 587 }; 588 589 spi1: spi@11016000 { 590 compatible = "mediatek,mt7622-spi"; 591 reg = <0 0x11016000 0 0x100>; 592 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 593 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 594 <&topckgen CLK_TOP_SPI1_SEL>, 595 <&pericfg CLK_PERI_SPI1_PD>; 596 clock-names = "parent-clk", "sel-clk", "spi-clk"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 uart4: serial@11019000 { 603 compatible = "mediatek,mt7622-uart", 604 "mediatek,mt6577-uart"; 605 reg = <0 0x11019000 0 0x400>; 606 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 607 clocks = <&topckgen CLK_TOP_UART_SEL>, 608 <&pericfg CLK_PERI_UART4_PD>; 609 clock-names = "baud", "bus"; 610 status = "disabled"; 611 }; 612 613 audsys: clock-controller@11220000 { 614 compatible = "mediatek,mt7622-audsys", "syscon"; 615 reg = <0 0x11220000 0 0x2000>; 616 #clock-cells = <1>; 617 618 afe: audio-controller { 619 compatible = "mediatek,mt7622-audio"; 620 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, 621 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 622 interrupt-names = "afe", "asys"; 623 624 clocks = <&infracfg CLK_INFRA_AUDIO_PD>, 625 <&topckgen CLK_TOP_AUD1_SEL>, 626 <&topckgen CLK_TOP_AUD2_SEL>, 627 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, 628 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, 629 <&topckgen CLK_TOP_I2S0_MCK_SEL>, 630 <&topckgen CLK_TOP_I2S1_MCK_SEL>, 631 <&topckgen CLK_TOP_I2S2_MCK_SEL>, 632 <&topckgen CLK_TOP_I2S3_MCK_SEL>, 633 <&topckgen CLK_TOP_I2S0_MCK_DIV>, 634 <&topckgen CLK_TOP_I2S1_MCK_DIV>, 635 <&topckgen CLK_TOP_I2S2_MCK_DIV>, 636 <&topckgen CLK_TOP_I2S3_MCK_DIV>, 637 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, 638 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, 639 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, 640 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, 641 <&audsys CLK_AUDIO_I2SO1>, 642 <&audsys CLK_AUDIO_I2SO2>, 643 <&audsys CLK_AUDIO_I2SO3>, 644 <&audsys CLK_AUDIO_I2SO4>, 645 <&audsys CLK_AUDIO_I2SIN1>, 646 <&audsys CLK_AUDIO_I2SIN2>, 647 <&audsys CLK_AUDIO_I2SIN3>, 648 <&audsys CLK_AUDIO_I2SIN4>, 649 <&audsys CLK_AUDIO_ASRCO1>, 650 <&audsys CLK_AUDIO_ASRCO2>, 651 <&audsys CLK_AUDIO_ASRCO3>, 652 <&audsys CLK_AUDIO_ASRCO4>, 653 <&audsys CLK_AUDIO_AFE>, 654 <&audsys CLK_AUDIO_AFE_CONN>, 655 <&audsys CLK_AUDIO_A1SYS>, 656 <&audsys CLK_AUDIO_A2SYS>; 657 658 clock-names = "infra_sys_audio_clk", 659 "top_audio_mux1_sel", 660 "top_audio_mux2_sel", 661 "top_audio_a1sys_hp", 662 "top_audio_a2sys_hp", 663 "i2s0_src_sel", 664 "i2s1_src_sel", 665 "i2s2_src_sel", 666 "i2s3_src_sel", 667 "i2s0_src_div", 668 "i2s1_src_div", 669 "i2s2_src_div", 670 "i2s3_src_div", 671 "i2s0_mclk_en", 672 "i2s1_mclk_en", 673 "i2s2_mclk_en", 674 "i2s3_mclk_en", 675 "i2so0_hop_ck", 676 "i2so1_hop_ck", 677 "i2so2_hop_ck", 678 "i2so3_hop_ck", 679 "i2si0_hop_ck", 680 "i2si1_hop_ck", 681 "i2si2_hop_ck", 682 "i2si3_hop_ck", 683 "asrc0_out_ck", 684 "asrc1_out_ck", 685 "asrc2_out_ck", 686 "asrc3_out_ck", 687 "audio_afe_pd", 688 "audio_afe_conn_pd", 689 "audio_a1sys_pd", 690 "audio_a2sys_pd"; 691 692 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, 693 <&topckgen CLK_TOP_A2SYS_HP_SEL>, 694 <&topckgen CLK_TOP_A1SYS_HP_DIV>, 695 <&topckgen CLK_TOP_A2SYS_HP_DIV>; 696 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, 697 <&topckgen CLK_TOP_AUD2PLL>; 698 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 699 }; 700 }; 701 702 mmc0: mmc@11230000 { 703 compatible = "mediatek,mt7622-mmc"; 704 reg = <0 0x11230000 0 0x1000>; 705 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 706 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, 707 <&topckgen CLK_TOP_MSDC50_0_SEL>; 708 clock-names = "source", "hclk"; 709 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; 710 reset-names = "hrst"; 711 status = "disabled"; 712 }; 713 714 mmc1: mmc@11240000 { 715 compatible = "mediatek,mt7622-mmc"; 716 reg = <0 0x11240000 0 0x1000>; 717 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 718 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, 719 <&topckgen CLK_TOP_AXI_SEL>; 720 clock-names = "source", "hclk"; 721 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; 722 reset-names = "hrst"; 723 status = "disabled"; 724 }; 725 726 wmac: wmac@18000000 { 727 compatible = "mediatek,mt7622-wmac"; 728 reg = <0 0x18000000 0 0x100000>; 729 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; 730 731 mediatek,infracfg = <&infracfg>; 732 status = "disabled"; 733 734 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; 735 }; 736 737 ssusbsys: ssusbsys@1a000000 { 738 compatible = "mediatek,mt7622-ssusbsys", 739 "syscon"; 740 reg = <0 0x1a000000 0 0x1000>; 741 #clock-cells = <1>; 742 #reset-cells = <1>; 743 }; 744 745 ssusb: usb@1a0c0000 { 746 compatible = "mediatek,mt7622-xhci", 747 "mediatek,mtk-xhci"; 748 reg = <0 0x1a0c0000 0 0x01000>, 749 <0 0x1a0c4700 0 0x0100>; 750 reg-names = "mac", "ippc"; 751 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 752 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; 753 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, 754 <&ssusbsys CLK_SSUSB_REF_EN>, 755 <&ssusbsys CLK_SSUSB_MCU_EN>, 756 <&ssusbsys CLK_SSUSB_DMA_EN>; 757 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 758 phys = <&u2port0 PHY_TYPE_USB2>, 759 <&u3port0 PHY_TYPE_USB3>, 760 <&u2port1 PHY_TYPE_USB2>; 761 762 status = "disabled"; 763 }; 764 765 u3phy: t-phy@1a0c4000 { 766 compatible = "mediatek,mt7622-tphy", 767 "mediatek,generic-tphy-v1"; 768 reg = <0 0x1a0c4000 0 0x700>; 769 #address-cells = <2>; 770 #size-cells = <2>; 771 ranges; 772 status = "disabled"; 773 774 u2port0: usb-phy@1a0c4800 { 775 reg = <0 0x1a0c4800 0 0x0100>; 776 #phy-cells = <1>; 777 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; 778 clock-names = "ref"; 779 }; 780 781 u3port0: usb-phy@1a0c4900 { 782 reg = <0 0x1a0c4900 0 0x0700>; 783 #phy-cells = <1>; 784 clocks = <&clk25m>; 785 clock-names = "ref"; 786 }; 787 788 u2port1: usb-phy@1a0c5000 { 789 reg = <0 0x1a0c5000 0 0x0100>; 790 #phy-cells = <1>; 791 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; 792 clock-names = "ref"; 793 }; 794 }; 795 796 pciesys: pciesys@1a100800 { 797 compatible = "mediatek,mt7622-pciesys", 798 "syscon"; 799 reg = <0 0x1a100800 0 0x1000>; 800 #clock-cells = <1>; 801 #reset-cells = <1>; 802 }; 803 804 pciecfg: pciecfg@1a140000 { 805 compatible = "mediatek,generic-pciecfg", "syscon"; 806 reg = <0 0x1a140000 0 0x1000>; 807 }; 808 809 pcie0: pcie@1a143000 { 810 compatible = "mediatek,mt7622-pcie"; 811 device_type = "pci"; 812 reg = <0 0x1a143000 0 0x1000>; 813 reg-names = "port0"; 814 linux,pci-domain = <0>; 815 #address-cells = <3>; 816 #size-cells = <2>; 817 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 818 interrupt-names = "pcie_irq"; 819 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, 820 <&pciesys CLK_PCIE_P0_AHB_EN>, 821 <&pciesys CLK_PCIE_P0_AUX_EN>, 822 <&pciesys CLK_PCIE_P0_AXI_EN>, 823 <&pciesys CLK_PCIE_P0_OBFF_EN>, 824 <&pciesys CLK_PCIE_P0_PIPE_EN>; 825 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", 826 "axi_ck0", "obff_ck0", "pipe_ck0"; 827 828 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 829 bus-range = <0x00 0xff>; 830 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; 831 status = "disabled"; 832 833 #interrupt-cells = <1>; 834 interrupt-map-mask = <0 0 0 7>; 835 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 836 <0 0 0 2 &pcie_intc0 1>, 837 <0 0 0 3 &pcie_intc0 2>, 838 <0 0 0 4 &pcie_intc0 3>; 839 pcie_intc0: interrupt-controller { 840 interrupt-controller; 841 #address-cells = <0>; 842 #interrupt-cells = <1>; 843 }; 844 }; 845 846 pcie1: pcie@1a145000 { 847 compatible = "mediatek,mt7622-pcie"; 848 device_type = "pci"; 849 reg = <0 0x1a145000 0 0x1000>; 850 reg-names = "port1"; 851 linux,pci-domain = <1>; 852 #address-cells = <3>; 853 #size-cells = <2>; 854 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 855 interrupt-names = "pcie_irq"; 856 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, 857 /* designer has connect RC1 with p0_ahb clock */ 858 <&pciesys CLK_PCIE_P0_AHB_EN>, 859 <&pciesys CLK_PCIE_P1_AUX_EN>, 860 <&pciesys CLK_PCIE_P1_AXI_EN>, 861 <&pciesys CLK_PCIE_P1_OBFF_EN>, 862 <&pciesys CLK_PCIE_P1_PIPE_EN>; 863 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", 864 "axi_ck1", "obff_ck1", "pipe_ck1"; 865 866 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 867 bus-range = <0x00 0xff>; 868 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; 869 status = "disabled"; 870 871 #interrupt-cells = <1>; 872 interrupt-map-mask = <0 0 0 7>; 873 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 874 <0 0 0 2 &pcie_intc1 1>, 875 <0 0 0 3 &pcie_intc1 2>, 876 <0 0 0 4 &pcie_intc1 3>; 877 pcie_intc1: interrupt-controller { 878 interrupt-controller; 879 #address-cells = <0>; 880 #interrupt-cells = <1>; 881 }; 882 }; 883 884 sata: sata@1a200000 { 885 compatible = "mediatek,mt7622-ahci", 886 "mediatek,mtk-ahci"; 887 reg = <0 0x1a200000 0 0x1100>; 888 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "hostc"; 890 clocks = <&pciesys CLK_SATA_AHB_EN>, 891 <&pciesys CLK_SATA_AXI_EN>, 892 <&pciesys CLK_SATA_ASIC_EN>, 893 <&pciesys CLK_SATA_RBC_EN>, 894 <&pciesys CLK_SATA_PM_EN>; 895 clock-names = "ahb", "axi", "asic", "rbc", "pm"; 896 phys = <&sata_port PHY_TYPE_SATA>; 897 phy-names = "sata-phy"; 898 ports-implemented = <0x1>; 899 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 900 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, 901 <&pciesys MT7622_SATA_PHY_SW_RST>, 902 <&pciesys MT7622_SATA_PHY_REG_RST>; 903 reset-names = "axi", "sw", "reg"; 904 mediatek,phy-mode = <&pciesys>; 905 status = "disabled"; 906 }; 907 908 sata_phy: t-phy@1a243000 { 909 compatible = "mediatek,mt7622-tphy", 910 "mediatek,generic-tphy-v1"; 911 #address-cells = <2>; 912 #size-cells = <2>; 913 ranges; 914 status = "disabled"; 915 916 sata_port: sata-phy@1a243000 { 917 reg = <0 0x1a243000 0 0x0100>; 918 clocks = <&topckgen CLK_TOP_ETH_500M>; 919 clock-names = "ref"; 920 #phy-cells = <1>; 921 }; 922 }; 923 924 hifsys: syscon@1af00000 { 925 compatible = "mediatek,mt7622-hifsys", "syscon"; 926 reg = <0 0x1af00000 0 0x70>; 927 }; 928 929 ethsys: syscon@1b000000 { 930 compatible = "mediatek,mt7622-ethsys", 931 "syscon"; 932 reg = <0 0x1b000000 0 0x1000>; 933 #clock-cells = <1>; 934 #reset-cells = <1>; 935 }; 936 937 hsdma: dma-controller@1b007000 { 938 compatible = "mediatek,mt7622-hsdma"; 939 reg = <0 0x1b007000 0 0x1000>; 940 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>; 941 clocks = <ðsys CLK_ETH_HSDMA_EN>; 942 clock-names = "hsdma"; 943 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 944 #dma-cells = <1>; 945 dma-requests = <3>; 946 }; 947 948 pcie_mirror: pcie-mirror@10000400 { 949 compatible = "mediatek,mt7622-pcie-mirror", 950 "syscon"; 951 reg = <0 0x10000400 0 0x10>; 952 }; 953 954 wed0: wed@1020a000 { 955 compatible = "mediatek,mt7622-wed", 956 "syscon"; 957 reg = <0 0x1020a000 0 0x1000>; 958 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; 959 }; 960 961 wed1: wed@1020b000 { 962 compatible = "mediatek,mt7622-wed", 963 "syscon"; 964 reg = <0 0x1020b000 0 0x1000>; 965 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>; 966 }; 967 968 eth: ethernet@1b100000 { 969 compatible = "mediatek,mt7622-eth", 970 "mediatek,mt2701-eth", 971 "syscon"; 972 reg = <0 0x1b100000 0 0x20000>; 973 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>, 974 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>, 975 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 976 clocks = <&topckgen CLK_TOP_ETH_SEL>, 977 <ðsys CLK_ETH_ESW_EN>, 978 <ðsys CLK_ETH_GP0_EN>, 979 <ðsys CLK_ETH_GP1_EN>, 980 <ðsys CLK_ETH_GP2_EN>, 981 <&sgmiisys CLK_SGMII_TX250M_EN>, 982 <&sgmiisys CLK_SGMII_RX250M_EN>, 983 <&sgmiisys CLK_SGMII_CDR_REF>, 984 <&sgmiisys CLK_SGMII_CDR_FB>, 985 <&topckgen CLK_TOP_SGMIIPLL>, 986 <&apmixedsys CLK_APMIXED_ETH2PLL>; 987 clock-names = "ethif", "esw", "gp0", "gp1", "gp2", 988 "sgmii_tx250m", "sgmii_rx250m", 989 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", 990 "eth2pll"; 991 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 992 mediatek,ethsys = <ðsys>; 993 mediatek,sgmiisys = <&sgmiisys>; 994 cci-control-port = <&cci_control2>; 995 mediatek,wed = <&wed0>, <&wed1>; 996 mediatek,pcie-mirror = <&pcie_mirror>; 997 mediatek,hifsys = <&hifsys>; 998 dma-coherent; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 sgmiisys: sgmiisys@1b128000 { 1005 compatible = "mediatek,mt7622-sgmiisys", 1006 "syscon"; 1007 reg = <0 0x1b128000 0 0x3000>; 1008 #clock-cells = <1>; 1009 }; 1010}; 1011