xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts (revision db33c6f3ae9d1231087710068ee4ea5398aacca7) 
1/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "Bananapi BPI-R64";
18	chassis-type = "embedded";
19	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	chosen {
26		stdout-path = "serial0:115200n8";
27		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
28	};
29
30	cpus {
31		cpu@0 {
32			proc-supply = <&mt6380_vcpu_reg>;
33			sram-supply = <&mt6380_vm_reg>;
34		};
35
36		cpu@1 {
37			proc-supply = <&mt6380_vcpu_reg>;
38			sram-supply = <&mt6380_vm_reg>;
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		factory-key {
46			label = "factory";
47			linux,code = <BTN_0>;
48			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
49		};
50
51		wps-key {
52			label = "wps";
53			linux,code = <KEY_WPS_BUTTON>;
54			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
55		};
56	};
57
58	leds {
59		compatible = "gpio-leds";
60
61		led-0 {
62			label = "bpi-r64:pio:green";
63			color = <LED_COLOR_ID_GREEN>;
64			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
65			default-state = "off";
66		};
67
68		led-1 {
69			label = "bpi-r64:pio:red";
70			color = <LED_COLOR_ID_RED>;
71			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
72			default-state = "off";
73		};
74	};
75
76	memory@40000000 {
77		reg = <0 0x40000000 0 0x40000000>;
78	};
79
80	reg_1p8v: regulator-1p8v {
81		compatible = "regulator-fixed";
82		regulator-name = "fixed-1.8V";
83		regulator-min-microvolt = <1800000>;
84		regulator-max-microvolt = <1800000>;
85		regulator-always-on;
86	};
87
88	reg_3p3v: regulator-3p3v {
89		compatible = "regulator-fixed";
90		regulator-name = "fixed-3.3V";
91		regulator-min-microvolt = <3300000>;
92		regulator-max-microvolt = <3300000>;
93		regulator-boot-on;
94		regulator-always-on;
95	};
96
97	reg_5v: regulator-5v {
98		compatible = "regulator-fixed";
99		regulator-name = "fixed-5V";
100		regulator-min-microvolt = <5000000>;
101		regulator-max-microvolt = <5000000>;
102		regulator-boot-on;
103		regulator-always-on;
104	};
105};
106
107&bch {
108	status = "disabled";
109};
110
111&btif {
112	status = "okay";
113};
114
115&cir {
116	pinctrl-names = "default";
117	pinctrl-0 = <&irrx_pins>;
118	status = "okay";
119};
120
121&eth {
122	status = "okay";
123	gmac0: mac@0 {
124		compatible = "mediatek,eth-mac";
125		reg = <0>;
126		phy-mode = "2500base-x";
127
128		fixed-link {
129			speed = <2500>;
130			full-duplex;
131			pause;
132		};
133	};
134
135	gmac1: mac@1 {
136		compatible = "mediatek,eth-mac";
137		reg = <1>;
138		phy-mode = "rgmii";
139
140		fixed-link {
141			speed = <1000>;
142			full-duplex;
143			pause;
144		};
145	};
146
147	mdio: mdio-bus {
148		#address-cells = <1>;
149		#size-cells = <0>;
150
151		switch@0 {
152			compatible = "mediatek,mt7531";
153			reg = <0>;
154			interrupt-controller;
155			#interrupt-cells = <1>;
156			interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>;
157			reset-gpios = <&pio 54 0>;
158
159			ports {
160				#address-cells = <1>;
161				#size-cells = <0>;
162
163				port@0 {
164					reg = <0>;
165					label = "wan";
166				};
167
168				port@1 {
169					reg = <1>;
170					label = "lan0";
171				};
172
173				port@2 {
174					reg = <2>;
175					label = "lan1";
176				};
177
178				port@3 {
179					reg = <3>;
180					label = "lan2";
181				};
182
183				port@4 {
184					reg = <4>;
185					label = "lan3";
186				};
187
188				port@6 {
189					reg = <6>;
190					label = "cpu";
191					ethernet = <&gmac0>;
192					phy-mode = "2500base-x";
193
194					fixed-link {
195						speed = <2500>;
196						full-duplex;
197						pause;
198					};
199				};
200			};
201		};
202
203	};
204};
205
206&i2c1 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&i2c1_pins>;
209	status = "okay";
210};
211
212&i2c2 {
213	pinctrl-names = "default";
214	pinctrl-0 = <&i2c2_pins>;
215	status = "okay";
216};
217
218&mmc0 {
219	pinctrl-names = "default", "state_uhs";
220	pinctrl-0 = <&emmc_pins_default>;
221	pinctrl-1 = <&emmc_pins_uhs>;
222	status = "okay";
223	bus-width = <8>;
224	max-frequency = <50000000>;
225	cap-mmc-highspeed;
226	mmc-hs200-1_8v;
227	vmmc-supply = <&reg_3p3v>;
228	vqmmc-supply = <&reg_1p8v>;
229	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
230	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
231	non-removable;
232};
233
234&mmc1 {
235	pinctrl-names = "default", "state_uhs";
236	pinctrl-0 = <&sd0_pins_default>;
237	pinctrl-1 = <&sd0_pins_uhs>;
238	status = "okay";
239	bus-width = <4>;
240	max-frequency = <50000000>;
241	cap-sd-highspeed;
242	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
243	vmmc-supply = <&reg_3p3v>;
244	vqmmc-supply = <&reg_3p3v>;
245	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
246	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
247};
248
249&nandc {
250	pinctrl-names = "default";
251	pinctrl-0 = <&parallel_nand_pins>;
252	status = "disabled";
253};
254
255&bch {
256	status = "okay";
257};
258
259&snfi {
260	pinctrl-names = "default";
261	pinctrl-0 = <&serial_nand_pins>;
262	status = "okay";
263	flash@0 {
264		compatible = "spi-nand";
265		reg = <0>;
266		spi-tx-bus-width = <4>;
267		spi-rx-bus-width = <4>;
268		nand-ecc-engine = <&snfi>;
269		partitions {
270			compatible = "fixed-partitions";
271			#address-cells = <1>;
272			#size-cells = <1>;
273
274			partition@0 {
275				label = "bl2";
276				reg = <0x0 0x80000>;
277				read-only;
278			};
279
280			partition@80000 {
281				label = "fip";
282				reg = <0x80000 0x200000>;
283				read-only;
284			};
285
286			ubi: partition@280000 {
287				label = "ubi";
288				reg = <0x280000 0x7d80000>;
289			};
290		};
291	};
292};
293
294&pcie0 {
295	pinctrl-names = "default";
296	pinctrl-0 = <&pcie0_pins>;
297	status = "okay";
298};
299
300&pcie1 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&pcie1_pins>;
303	status = "okay";
304};
305
306&pio {
307	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
308	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
309	 */
310	asm_sel {
311		gpio-hog;
312		gpios = <90 GPIO_ACTIVE_HIGH>;
313		output-high;
314	};
315
316	/* eMMC is shared pin with parallel NAND */
317	emmc_pins_default: emmc-pins-default {
318		mux {
319			function = "emmc", "emmc_rst";
320			groups = "emmc";
321		};
322
323		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
324		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
325		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
326		 */
327		conf-cmd-dat {
328			pins = "NDL0", "NDL1", "NDL2",
329			       "NDL3", "NDL4", "NDL5",
330			       "NDL6", "NDL7", "NRB";
331			input-enable;
332			bias-pull-up;
333		};
334
335		conf-clk {
336			pins = "NCLE";
337			bias-pull-down;
338		};
339	};
340
341	emmc_pins_uhs: emmc-pins-uhs {
342		mux {
343			function = "emmc";
344			groups = "emmc";
345		};
346
347		conf-cmd-dat {
348			pins = "NDL0", "NDL1", "NDL2",
349			       "NDL3", "NDL4", "NDL5",
350			       "NDL6", "NDL7", "NRB";
351			input-enable;
352			drive-strength = <4>;
353			bias-pull-up;
354		};
355
356		conf-clk {
357			pins = "NCLE";
358			drive-strength = <4>;
359			bias-pull-down;
360		};
361	};
362
363	eth_pins: eth-pins {
364		mux {
365			function = "eth";
366			groups = "mdc_mdio", "rgmii_via_gmac2";
367		};
368	};
369
370	i2c1_pins: i2c1-pins {
371		mux {
372			function = "i2c";
373			groups = "i2c1_0";
374		};
375	};
376
377	i2c2_pins: i2c2-pins {
378		mux {
379			function = "i2c";
380			groups = "i2c2_0";
381		};
382	};
383
384	i2s1_pins: i2s1-pins {
385		mux {
386			function = "i2s";
387			groups = "i2s_out_mclk_bclk_ws",
388				 "i2s1_in_data",
389				 "i2s1_out_data";
390		};
391
392		conf {
393			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
394			       "I2S_WS", "I2S_MCLK";
395			drive-strength = <12>;
396			bias-pull-down;
397		};
398	};
399
400	irrx_pins: irrx-pins {
401		mux {
402			function = "ir";
403			groups = "ir_1_rx";
404		};
405	};
406
407	irtx_pins: irtx-pins {
408		mux {
409			function = "ir";
410			groups = "ir_1_tx";
411		};
412	};
413
414	/* Parallel nand is shared pin with eMMC */
415	parallel_nand_pins: parallel-nand-pins {
416		mux {
417			function = "flash";
418			groups = "par_nand";
419		};
420	};
421
422	pcie0_pins: pcie0-pins {
423		mux {
424			function = "pcie";
425			groups = "pcie0_pad_perst",
426				 "pcie0_1_waken",
427				 "pcie0_1_clkreq";
428		};
429	};
430
431	pcie1_pins: pcie1-pins {
432		mux {
433			function = "pcie";
434			groups = "pcie1_pad_perst",
435				 "pcie1_0_waken",
436				 "pcie1_0_clkreq";
437		};
438	};
439
440	pmic_bus_pins: pmic-bus-pins {
441		mux {
442			function = "pmic";
443			groups = "pmic_bus";
444		};
445	};
446
447	pwm_pins: pwm-pins {
448		mux {
449			function = "pwm";
450			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
451				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
452				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
453				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
454				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
455				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
456		};
457	};
458
459	wled_pins: wled-pins {
460		mux {
461			function = "led";
462			groups = "wled";
463		};
464	};
465
466	sd0_pins_default: sd0-pins-default {
467		mux {
468			function = "sd";
469			groups = "sd_0";
470		};
471
472		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
473		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
474		 *  DAT2, DAT3, CMD, CLK for SD respectively.
475		 */
476		conf-cmd-data {
477			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
478			       "I2S2_IN","I2S4_OUT";
479			input-enable;
480			drive-strength = <8>;
481			bias-pull-up;
482		};
483		conf-clk {
484			pins = "I2S3_OUT";
485			drive-strength = <12>;
486			bias-pull-down;
487		};
488		conf-cd {
489			pins = "TXD3";
490			bias-pull-up;
491		};
492	};
493
494	sd0_pins_uhs: sd0-pins-uhs {
495		mux {
496			function = "sd";
497			groups = "sd_0";
498		};
499
500		conf-cmd-data {
501			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
502			       "I2S2_IN","I2S4_OUT";
503			input-enable;
504			bias-pull-up;
505		};
506
507		conf-clk {
508			pins = "I2S3_OUT";
509			bias-pull-down;
510		};
511	};
512
513	/* Serial NAND is shared pin with SPI-NOR */
514	serial_nand_pins: serial-nand-pins {
515		mux {
516			function = "flash";
517			groups = "snfi";
518		};
519	};
520
521	spic0_pins: spic0-pins {
522		mux {
523			function = "spi";
524			groups = "spic0_0";
525		};
526	};
527
528	spic1_pins: spic1-pins {
529		mux {
530			function = "spi";
531			groups = "spic1_0";
532		};
533	};
534
535	/* SPI-NOR is shared pin with serial NAND */
536	spi_nor_pins: spi-nor-pins {
537		mux {
538			function = "flash";
539			groups = "spi_nor";
540		};
541	};
542
543	/* serial NAND is shared pin with SPI-NOR */
544	serial_nand_pins: serial-nand-pins {
545		mux {
546			function = "flash";
547			groups = "snfi";
548		};
549	};
550
551	uart0_pins: uart0-pins {
552		mux {
553			function = "uart";
554			groups = "uart0_0_tx_rx" ;
555		};
556	};
557
558	uart2_pins: uart2-pins {
559		mux {
560			function = "uart";
561			groups = "uart2_1_tx_rx" ;
562		};
563	};
564
565	watchdog_pins: watchdog-pins {
566		mux {
567			function = "watchdog";
568			groups = "watchdog";
569		};
570	};
571};
572
573&pwm {
574	pinctrl-names = "default";
575	pinctrl-0 = <&pwm_pins>;
576	status = "okay";
577};
578
579&pwrap {
580	pinctrl-names = "default";
581	pinctrl-0 = <&pmic_bus_pins>;
582
583	status = "okay";
584};
585
586&sata {
587	status = "disabled";
588};
589
590&sata_phy {
591	status = "disabled";
592};
593
594&spi0 {
595	pinctrl-names = "default";
596	pinctrl-0 = <&spic0_pins>;
597	status = "okay";
598};
599
600&spi1 {
601	pinctrl-names = "default";
602	pinctrl-0 = <&spic1_pins>;
603};
604
605&ssusb {
606	vusb33-supply = <&reg_3p3v>;
607	vbus-supply = <&reg_5v>;
608	status = "okay";
609};
610
611&u3phy {
612	status = "okay";
613};
614
615&uart0 {
616	pinctrl-names = "default";
617	pinctrl-0 = <&uart0_pins>;
618	status = "okay";
619};
620
621&uart2 {
622	pinctrl-names = "default";
623	pinctrl-0 = <&uart2_pins>;
624};
625
626&watchdog {
627	pinctrl-names = "default";
628	pinctrl-0 = <&watchdog_pins>;
629	status = "okay";
630};
631
632&wmac {
633	status = "okay";
634};
635