xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts (revision 8cc087a1eee9ec1ca9f7ac1e63ad51bdb5a682eb) 
1/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/gpio/gpio.h>
11
12#include "mt7622.dtsi"
13#include "mt6380.dtsi"
14
15/ {
16	model = "Bananapi BPI-R64";
17	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
18
19	aliases {
20		serial0 = &uart0;
21	};
22
23	chosen {
24		stdout-path = "serial0:115200n8";
25		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
26	};
27
28	cpus {
29		cpu@0 {
30			proc-supply = <&mt6380_vcpu_reg>;
31			sram-supply = <&mt6380_vm_reg>;
32		};
33
34		cpu@1 {
35			proc-supply = <&mt6380_vcpu_reg>;
36			sram-supply = <&mt6380_vm_reg>;
37		};
38	};
39
40	gpio-keys {
41		compatible = "gpio-keys";
42
43		factory {
44			label = "factory";
45			linux,code = <BTN_0>;
46			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
47		};
48
49		wps {
50			label = "wps";
51			linux,code = <KEY_WPS_BUTTON>;
52			gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
53		};
54	};
55
56	leds {
57		compatible = "gpio-leds";
58
59		green {
60			label = "bpi-r64:pio:green";
61			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
62			default-state = "off";
63		};
64
65		red {
66			label = "bpi-r64:pio:red";
67			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
68			default-state = "off";
69		};
70	};
71
72	memory {
73		reg = <0 0x40000000 0 0x40000000>;
74	};
75
76	reg_1p8v: regulator-1p8v {
77		compatible = "regulator-fixed";
78		regulator-name = "fixed-1.8V";
79		regulator-min-microvolt = <1800000>;
80		regulator-max-microvolt = <1800000>;
81		regulator-always-on;
82	};
83
84	reg_3p3v: regulator-3p3v {
85		compatible = "regulator-fixed";
86		regulator-name = "fixed-3.3V";
87		regulator-min-microvolt = <3300000>;
88		regulator-max-microvolt = <3300000>;
89		regulator-boot-on;
90		regulator-always-on;
91	};
92
93	reg_5v: regulator-5v {
94		compatible = "regulator-fixed";
95		regulator-name = "fixed-5V";
96		regulator-min-microvolt = <5000000>;
97		regulator-max-microvolt = <5000000>;
98		regulator-boot-on;
99		regulator-always-on;
100	};
101};
102
103&bch {
104	status = "disabled";
105};
106
107&btif {
108	status = "okay";
109};
110
111&cir {
112	pinctrl-names = "default";
113	pinctrl-0 = <&irrx_pins>;
114	status = "okay";
115};
116
117&eth {
118	status = "okay";
119	gmac0: mac@0 {
120		compatible = "mediatek,eth-mac";
121		reg = <0>;
122		phy-mode = "2500base-x";
123
124		fixed-link {
125			speed = <2500>;
126			full-duplex;
127			pause;
128		};
129	};
130
131	gmac1: mac@1 {
132		compatible = "mediatek,eth-mac";
133		reg = <1>;
134		phy-mode = "rgmii";
135
136		fixed-link {
137			speed = <1000>;
138			full-duplex;
139			pause;
140		};
141	};
142
143	mdio: mdio-bus {
144		#address-cells = <1>;
145		#size-cells = <0>;
146
147		switch@0 {
148			compatible = "mediatek,mt7531";
149			reg = <0>;
150			reset-gpios = <&pio 54 0>;
151
152			ports {
153				#address-cells = <1>;
154				#size-cells = <0>;
155
156				port@0 {
157					reg = <0>;
158					label = "wan";
159				};
160
161				port@1 {
162					reg = <1>;
163					label = "lan0";
164				};
165
166				port@2 {
167					reg = <2>;
168					label = "lan1";
169				};
170
171				port@3 {
172					reg = <3>;
173					label = "lan2";
174				};
175
176				port@4 {
177					reg = <4>;
178					label = "lan3";
179				};
180
181				port@6 {
182					reg = <6>;
183					label = "cpu";
184					ethernet = <&gmac0>;
185					phy-mode = "2500base-x";
186
187					fixed-link {
188						speed = <2500>;
189						full-duplex;
190						pause;
191					};
192				};
193			};
194		};
195
196	};
197};
198
199&i2c1 {
200	pinctrl-names = "default";
201	pinctrl-0 = <&i2c1_pins>;
202	status = "okay";
203};
204
205&i2c2 {
206	pinctrl-names = "default";
207	pinctrl-0 = <&i2c2_pins>;
208	status = "okay";
209};
210
211&mmc0 {
212	pinctrl-names = "default", "state_uhs";
213	pinctrl-0 = <&emmc_pins_default>;
214	pinctrl-1 = <&emmc_pins_uhs>;
215	status = "okay";
216	bus-width = <8>;
217	max-frequency = <50000000>;
218	cap-mmc-highspeed;
219	mmc-hs200-1_8v;
220	vmmc-supply = <&reg_3p3v>;
221	vqmmc-supply = <&reg_1p8v>;
222	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
223	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
224	non-removable;
225};
226
227&mmc1 {
228	pinctrl-names = "default", "state_uhs";
229	pinctrl-0 = <&sd0_pins_default>;
230	pinctrl-1 = <&sd0_pins_uhs>;
231	status = "okay";
232	bus-width = <4>;
233	max-frequency = <50000000>;
234	cap-sd-highspeed;
235	r_smpl = <1>;
236	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
237	vmmc-supply = <&reg_3p3v>;
238	vqmmc-supply = <&reg_3p3v>;
239	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
240	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
241};
242
243&nandc {
244	pinctrl-names = "default";
245	pinctrl-0 = <&parallel_nand_pins>;
246	status = "disabled";
247};
248
249&nor_flash {
250	pinctrl-names = "default";
251	pinctrl-0 = <&spi_nor_pins>;
252	status = "disabled";
253
254	flash@0 {
255		compatible = "jedec,spi-nor";
256		reg = <0>;
257	};
258};
259
260&pcie0 {
261	pinctrl-names = "default";
262	pinctrl-0 = <&pcie0_pins>;
263	status = "okay";
264};
265
266&pcie1 {
267	pinctrl-names = "default";
268	pinctrl-0 = <&pcie1_pins>;
269	status = "okay";
270};
271
272&pio {
273	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
274	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
275	 */
276	asm_sel {
277		gpio-hog;
278		gpios = <90 GPIO_ACTIVE_HIGH>;
279		output-high;
280	};
281
282	/* eMMC is shared pin with parallel NAND */
283	emmc_pins_default: emmc-pins-default {
284		mux {
285			function = "emmc", "emmc_rst";
286			groups = "emmc";
287		};
288
289		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
290		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
291		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
292		 */
293		conf-cmd-dat {
294			pins = "NDL0", "NDL1", "NDL2",
295			       "NDL3", "NDL4", "NDL5",
296			       "NDL6", "NDL7", "NRB";
297			input-enable;
298			bias-pull-up;
299		};
300
301		conf-clk {
302			pins = "NCLE";
303			bias-pull-down;
304		};
305	};
306
307	emmc_pins_uhs: emmc-pins-uhs {
308		mux {
309			function = "emmc";
310			groups = "emmc";
311		};
312
313		conf-cmd-dat {
314			pins = "NDL0", "NDL1", "NDL2",
315			       "NDL3", "NDL4", "NDL5",
316			       "NDL6", "NDL7", "NRB";
317			input-enable;
318			drive-strength = <4>;
319			bias-pull-up;
320		};
321
322		conf-clk {
323			pins = "NCLE";
324			drive-strength = <4>;
325			bias-pull-down;
326		};
327	};
328
329	eth_pins: eth-pins {
330		mux {
331			function = "eth";
332			groups = "mdc_mdio", "rgmii_via_gmac2";
333		};
334	};
335
336	i2c1_pins: i2c1-pins {
337		mux {
338			function = "i2c";
339			groups =  "i2c1_0";
340		};
341	};
342
343	i2c2_pins: i2c2-pins {
344		mux {
345			function = "i2c";
346			groups =  "i2c2_0";
347		};
348	};
349
350	i2s1_pins: i2s1-pins {
351		mux {
352			function = "i2s";
353			groups =  "i2s_out_mclk_bclk_ws",
354				  "i2s1_in_data",
355				  "i2s1_out_data";
356		};
357
358		conf {
359			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
360			       "I2S_WS", "I2S_MCLK";
361			drive-strength = <12>;
362			bias-pull-down;
363		};
364	};
365
366	irrx_pins: irrx-pins {
367		mux {
368			function = "ir";
369			groups =  "ir_1_rx";
370		};
371	};
372
373	irtx_pins: irtx-pins {
374		mux {
375			function = "ir";
376			groups =  "ir_1_tx";
377		};
378	};
379
380	/* Parallel nand is shared pin with eMMC */
381	parallel_nand_pins: parallel-nand-pins {
382		mux {
383			function = "flash";
384			groups = "par_nand";
385		};
386	};
387
388	pcie0_pins: pcie0-pins {
389		mux {
390			function = "pcie";
391			groups = "pcie0_pad_perst",
392				 "pcie0_1_waken",
393				 "pcie0_1_clkreq";
394		};
395	};
396
397	pcie1_pins: pcie1-pins {
398		mux {
399			function = "pcie";
400			groups = "pcie1_pad_perst",
401				 "pcie1_0_waken",
402				 "pcie1_0_clkreq";
403		};
404	};
405
406	pmic_bus_pins: pmic-bus-pins {
407		mux {
408			function = "pmic";
409			groups = "pmic_bus";
410		};
411	};
412
413	pwm_pins: pwm-pins {
414		mux {
415			function = "pwm";
416			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
417				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
418				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
419				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
420				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
421				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
422		};
423	};
424
425	wled_pins: wled-pins {
426		mux {
427			function = "led";
428			groups = "wled";
429		};
430	};
431
432	sd0_pins_default: sd0-pins-default {
433		mux {
434			function = "sd";
435			groups = "sd_0";
436		};
437
438		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
439		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
440		 *  DAT2, DAT3, CMD, CLK for SD respectively.
441		 */
442		conf-cmd-data {
443			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
444			       "I2S2_IN","I2S4_OUT";
445			input-enable;
446			drive-strength = <8>;
447			bias-pull-up;
448		};
449		conf-clk {
450			pins = "I2S3_OUT";
451			drive-strength = <12>;
452			bias-pull-down;
453		};
454		conf-cd {
455			pins = "TXD3";
456			bias-pull-up;
457		};
458	};
459
460	sd0_pins_uhs: sd0-pins-uhs {
461		mux {
462			function = "sd";
463			groups = "sd_0";
464		};
465
466		conf-cmd-data {
467			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
468			       "I2S2_IN","I2S4_OUT";
469			input-enable;
470			bias-pull-up;
471		};
472
473		conf-clk {
474			pins = "I2S3_OUT";
475			bias-pull-down;
476		};
477	};
478
479	/* Serial NAND is shared pin with SPI-NOR */
480	serial_nand_pins: serial-nand-pins {
481		mux {
482			function = "flash";
483			groups = "snfi";
484		};
485	};
486
487	spic0_pins: spic0-pins {
488		mux {
489			function = "spi";
490			groups = "spic0_0";
491		};
492	};
493
494	spic1_pins: spic1-pins {
495		mux {
496			function = "spi";
497			groups = "spic1_0";
498		};
499	};
500
501	/* SPI-NOR is shared pin with serial NAND */
502	spi_nor_pins: spi-nor-pins {
503		mux {
504			function = "flash";
505			groups = "spi_nor";
506		};
507	};
508
509	/* serial NAND is shared pin with SPI-NOR */
510	serial_nand_pins: serial-nand-pins {
511		mux {
512			function = "flash";
513			groups = "snfi";
514		};
515	};
516
517	uart0_pins: uart0-pins {
518		mux {
519			function = "uart";
520			groups = "uart0_0_tx_rx" ;
521		};
522	};
523
524	uart2_pins: uart2-pins {
525		mux {
526			function = "uart";
527			groups = "uart2_1_tx_rx" ;
528		};
529	};
530
531	watchdog_pins: watchdog-pins {
532		mux {
533			function = "watchdog";
534			groups = "watchdog";
535		};
536	};
537};
538
539&pwm {
540	pinctrl-names = "default";
541	pinctrl-0 = <&pwm_pins>;
542	status = "okay";
543};
544
545&pwrap {
546	pinctrl-names = "default";
547	pinctrl-0 = <&pmic_bus_pins>;
548
549	status = "okay";
550};
551
552&sata {
553	status = "disable";
554};
555
556&sata_phy {
557	status = "disable";
558};
559
560&spi0 {
561	pinctrl-names = "default";
562	pinctrl-0 = <&spic0_pins>;
563	status = "okay";
564};
565
566&spi1 {
567	pinctrl-names = "default";
568	pinctrl-0 = <&spic1_pins>;
569};
570
571&ssusb {
572	vusb33-supply = <&reg_3p3v>;
573	vbus-supply = <&reg_5v>;
574	status = "okay";
575};
576
577&u3phy {
578	status = "okay";
579};
580
581&uart0 {
582	pinctrl-names = "default";
583	pinctrl-0 = <&uart0_pins>;
584	status = "okay";
585};
586
587&uart2 {
588	pinctrl-names = "default";
589	pinctrl-0 = <&uart2_pins>;
590};
591
592&watchdog {
593	pinctrl-names = "default";
594	pinctrl-0 = <&watchdog_pins>;
595	status = "okay";
596};
597
598&wmac {
599	status = "okay";
600};
601