xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "Bananapi BPI-R64";
18	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
27	};
28
29	cpus {
30		cpu@0 {
31			proc-supply = <&mt6380_vcpu_reg>;
32			sram-supply = <&mt6380_vm_reg>;
33		};
34
35		cpu@1 {
36			proc-supply = <&mt6380_vcpu_reg>;
37			sram-supply = <&mt6380_vm_reg>;
38		};
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43
44		factory-key {
45			label = "factory";
46			linux,code = <BTN_0>;
47			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
48		};
49
50		wps-key {
51			label = "wps";
52			linux,code = <KEY_WPS_BUTTON>;
53			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
54		};
55	};
56
57	leds {
58		compatible = "gpio-leds";
59
60		led-0 {
61			label = "bpi-r64:pio:green";
62			color = <LED_COLOR_ID_GREEN>;
63			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
64			default-state = "off";
65		};
66
67		led-1 {
68			label = "bpi-r64:pio:red";
69			color = <LED_COLOR_ID_RED>;
70			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
71			default-state = "off";
72		};
73	};
74
75	memory {
76		reg = <0 0x40000000 0 0x40000000>;
77	};
78
79	reg_1p8v: regulator-1p8v {
80		compatible = "regulator-fixed";
81		regulator-name = "fixed-1.8V";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <1800000>;
84		regulator-always-on;
85	};
86
87	reg_3p3v: regulator-3p3v {
88		compatible = "regulator-fixed";
89		regulator-name = "fixed-3.3V";
90		regulator-min-microvolt = <3300000>;
91		regulator-max-microvolt = <3300000>;
92		regulator-boot-on;
93		regulator-always-on;
94	};
95
96	reg_5v: regulator-5v {
97		compatible = "regulator-fixed";
98		regulator-name = "fixed-5V";
99		regulator-min-microvolt = <5000000>;
100		regulator-max-microvolt = <5000000>;
101		regulator-boot-on;
102		regulator-always-on;
103	};
104};
105
106&bch {
107	status = "disabled";
108};
109
110&btif {
111	status = "okay";
112};
113
114&cir {
115	pinctrl-names = "default";
116	pinctrl-0 = <&irrx_pins>;
117	status = "okay";
118};
119
120&eth {
121	status = "okay";
122	gmac0: mac@0 {
123		compatible = "mediatek,eth-mac";
124		reg = <0>;
125		phy-mode = "2500base-x";
126
127		fixed-link {
128			speed = <2500>;
129			full-duplex;
130			pause;
131		};
132	};
133
134	gmac1: mac@1 {
135		compatible = "mediatek,eth-mac";
136		reg = <1>;
137		phy-mode = "rgmii";
138
139		fixed-link {
140			speed = <1000>;
141			full-duplex;
142			pause;
143		};
144	};
145
146	mdio: mdio-bus {
147		#address-cells = <1>;
148		#size-cells = <0>;
149
150		switch@0 {
151			compatible = "mediatek,mt7531";
152			reg = <0>;
153			reset-gpios = <&pio 54 0>;
154
155			ports {
156				#address-cells = <1>;
157				#size-cells = <0>;
158
159				port@0 {
160					reg = <0>;
161					label = "wan";
162				};
163
164				port@1 {
165					reg = <1>;
166					label = "lan0";
167				};
168
169				port@2 {
170					reg = <2>;
171					label = "lan1";
172				};
173
174				port@3 {
175					reg = <3>;
176					label = "lan2";
177				};
178
179				port@4 {
180					reg = <4>;
181					label = "lan3";
182				};
183
184				port@6 {
185					reg = <6>;
186					label = "cpu";
187					ethernet = <&gmac0>;
188					phy-mode = "2500base-x";
189
190					fixed-link {
191						speed = <2500>;
192						full-duplex;
193						pause;
194					};
195				};
196			};
197		};
198
199	};
200};
201
202&i2c1 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&i2c1_pins>;
205	status = "okay";
206};
207
208&i2c2 {
209	pinctrl-names = "default";
210	pinctrl-0 = <&i2c2_pins>;
211	status = "okay";
212};
213
214&mmc0 {
215	pinctrl-names = "default", "state_uhs";
216	pinctrl-0 = <&emmc_pins_default>;
217	pinctrl-1 = <&emmc_pins_uhs>;
218	status = "okay";
219	bus-width = <8>;
220	max-frequency = <50000000>;
221	cap-mmc-highspeed;
222	mmc-hs200-1_8v;
223	vmmc-supply = <&reg_3p3v>;
224	vqmmc-supply = <&reg_1p8v>;
225	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
226	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
227	non-removable;
228};
229
230&mmc1 {
231	pinctrl-names = "default", "state_uhs";
232	pinctrl-0 = <&sd0_pins_default>;
233	pinctrl-1 = <&sd0_pins_uhs>;
234	status = "okay";
235	bus-width = <4>;
236	max-frequency = <50000000>;
237	cap-sd-highspeed;
238	r_smpl = <1>;
239	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
240	vmmc-supply = <&reg_3p3v>;
241	vqmmc-supply = <&reg_3p3v>;
242	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
243	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
244};
245
246&nandc {
247	pinctrl-names = "default";
248	pinctrl-0 = <&parallel_nand_pins>;
249	status = "disabled";
250};
251
252&nor_flash {
253	pinctrl-names = "default";
254	pinctrl-0 = <&spi_nor_pins>;
255	status = "disabled";
256
257	flash@0 {
258		compatible = "jedec,spi-nor";
259		reg = <0>;
260	};
261};
262
263&pcie0 {
264	pinctrl-names = "default";
265	pinctrl-0 = <&pcie0_pins>;
266	status = "okay";
267};
268
269&pcie1 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pcie1_pins>;
272	status = "okay";
273};
274
275&pio {
276	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
277	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
278	 */
279	asm_sel {
280		gpio-hog;
281		gpios = <90 GPIO_ACTIVE_HIGH>;
282		output-high;
283	};
284
285	/* eMMC is shared pin with parallel NAND */
286	emmc_pins_default: emmc-pins-default {
287		mux {
288			function = "emmc", "emmc_rst";
289			groups = "emmc";
290		};
291
292		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
293		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
294		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
295		 */
296		conf-cmd-dat {
297			pins = "NDL0", "NDL1", "NDL2",
298			       "NDL3", "NDL4", "NDL5",
299			       "NDL6", "NDL7", "NRB";
300			input-enable;
301			bias-pull-up;
302		};
303
304		conf-clk {
305			pins = "NCLE";
306			bias-pull-down;
307		};
308	};
309
310	emmc_pins_uhs: emmc-pins-uhs {
311		mux {
312			function = "emmc";
313			groups = "emmc";
314		};
315
316		conf-cmd-dat {
317			pins = "NDL0", "NDL1", "NDL2",
318			       "NDL3", "NDL4", "NDL5",
319			       "NDL6", "NDL7", "NRB";
320			input-enable;
321			drive-strength = <4>;
322			bias-pull-up;
323		};
324
325		conf-clk {
326			pins = "NCLE";
327			drive-strength = <4>;
328			bias-pull-down;
329		};
330	};
331
332	eth_pins: eth-pins {
333		mux {
334			function = "eth";
335			groups = "mdc_mdio", "rgmii_via_gmac2";
336		};
337	};
338
339	i2c1_pins: i2c1-pins {
340		mux {
341			function = "i2c";
342			groups = "i2c1_0";
343		};
344	};
345
346	i2c2_pins: i2c2-pins {
347		mux {
348			function = "i2c";
349			groups = "i2c2_0";
350		};
351	};
352
353	i2s1_pins: i2s1-pins {
354		mux {
355			function = "i2s";
356			groups =  "i2s_out_mclk_bclk_ws",
357				  "i2s1_in_data",
358				  "i2s1_out_data";
359		};
360
361		conf {
362			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
363			       "I2S_WS", "I2S_MCLK";
364			drive-strength = <12>;
365			bias-pull-down;
366		};
367	};
368
369	irrx_pins: irrx-pins {
370		mux {
371			function = "ir";
372			groups = "ir_1_rx";
373		};
374	};
375
376	irtx_pins: irtx-pins {
377		mux {
378			function = "ir";
379			groups = "ir_1_tx";
380		};
381	};
382
383	/* Parallel nand is shared pin with eMMC */
384	parallel_nand_pins: parallel-nand-pins {
385		mux {
386			function = "flash";
387			groups = "par_nand";
388		};
389	};
390
391	pcie0_pins: pcie0-pins {
392		mux {
393			function = "pcie";
394			groups = "pcie0_pad_perst",
395				 "pcie0_1_waken",
396				 "pcie0_1_clkreq";
397		};
398	};
399
400	pcie1_pins: pcie1-pins {
401		mux {
402			function = "pcie";
403			groups = "pcie1_pad_perst",
404				 "pcie1_0_waken",
405				 "pcie1_0_clkreq";
406		};
407	};
408
409	pmic_bus_pins: pmic-bus-pins {
410		mux {
411			function = "pmic";
412			groups = "pmic_bus";
413		};
414	};
415
416	pwm_pins: pwm-pins {
417		mux {
418			function = "pwm";
419			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
420				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
421				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
422				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
423				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
424				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
425		};
426	};
427
428	wled_pins: wled-pins {
429		mux {
430			function = "led";
431			groups = "wled";
432		};
433	};
434
435	sd0_pins_default: sd0-pins-default {
436		mux {
437			function = "sd";
438			groups = "sd_0";
439		};
440
441		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
442		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
443		 *  DAT2, DAT3, CMD, CLK for SD respectively.
444		 */
445		conf-cmd-data {
446			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
447			       "I2S2_IN","I2S4_OUT";
448			input-enable;
449			drive-strength = <8>;
450			bias-pull-up;
451		};
452		conf-clk {
453			pins = "I2S3_OUT";
454			drive-strength = <12>;
455			bias-pull-down;
456		};
457		conf-cd {
458			pins = "TXD3";
459			bias-pull-up;
460		};
461	};
462
463	sd0_pins_uhs: sd0-pins-uhs {
464		mux {
465			function = "sd";
466			groups = "sd_0";
467		};
468
469		conf-cmd-data {
470			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
471			       "I2S2_IN","I2S4_OUT";
472			input-enable;
473			bias-pull-up;
474		};
475
476		conf-clk {
477			pins = "I2S3_OUT";
478			bias-pull-down;
479		};
480	};
481
482	/* Serial NAND is shared pin with SPI-NOR */
483	serial_nand_pins: serial-nand-pins {
484		mux {
485			function = "flash";
486			groups = "snfi";
487		};
488	};
489
490	spic0_pins: spic0-pins {
491		mux {
492			function = "spi";
493			groups = "spic0_0";
494		};
495	};
496
497	spic1_pins: spic1-pins {
498		mux {
499			function = "spi";
500			groups = "spic1_0";
501		};
502	};
503
504	/* SPI-NOR is shared pin with serial NAND */
505	spi_nor_pins: spi-nor-pins {
506		mux {
507			function = "flash";
508			groups = "spi_nor";
509		};
510	};
511
512	/* serial NAND is shared pin with SPI-NOR */
513	serial_nand_pins: serial-nand-pins {
514		mux {
515			function = "flash";
516			groups = "snfi";
517		};
518	};
519
520	uart0_pins: uart0-pins {
521		mux {
522			function = "uart";
523			groups = "uart0_0_tx_rx" ;
524		};
525	};
526
527	uart2_pins: uart2-pins {
528		mux {
529			function = "uart";
530			groups = "uart2_1_tx_rx" ;
531		};
532	};
533
534	watchdog_pins: watchdog-pins {
535		mux {
536			function = "watchdog";
537			groups = "watchdog";
538		};
539	};
540};
541
542&pwm {
543	pinctrl-names = "default";
544	pinctrl-0 = <&pwm_pins>;
545	status = "okay";
546};
547
548&pwrap {
549	pinctrl-names = "default";
550	pinctrl-0 = <&pmic_bus_pins>;
551
552	status = "okay";
553};
554
555&sata {
556	status = "disable";
557};
558
559&sata_phy {
560	status = "disable";
561};
562
563&spi0 {
564	pinctrl-names = "default";
565	pinctrl-0 = <&spic0_pins>;
566	status = "okay";
567};
568
569&spi1 {
570	pinctrl-names = "default";
571	pinctrl-0 = <&spic1_pins>;
572};
573
574&ssusb {
575	vusb33-supply = <&reg_3p3v>;
576	vbus-supply = <&reg_5v>;
577	status = "okay";
578};
579
580&u3phy {
581	status = "okay";
582};
583
584&uart0 {
585	pinctrl-names = "default";
586	pinctrl-0 = <&uart0_pins>;
587	status = "okay";
588};
589
590&uart2 {
591	pinctrl-names = "default";
592	pinctrl-0 = <&uart2_pins>;
593};
594
595&watchdog {
596	pinctrl-names = "default";
597	pinctrl-0 = <&watchdog_pins>;
598	status = "okay";
599};
600
601&wmac {
602	status = "okay";
603};
604