xref: /freebsd/sys/contrib/device-tree/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8/dts-v1/;
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/leds/common.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "Bananapi BPI-R64";
18	compatible = "bananapi,bpi-r64", "mediatek,mt7622";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
27	};
28
29	cpus {
30		cpu@0 {
31			proc-supply = <&mt6380_vcpu_reg>;
32			sram-supply = <&mt6380_vm_reg>;
33		};
34
35		cpu@1 {
36			proc-supply = <&mt6380_vcpu_reg>;
37			sram-supply = <&mt6380_vm_reg>;
38		};
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43
44		factory-key {
45			label = "factory";
46			linux,code = <BTN_0>;
47			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
48		};
49
50		wps-key {
51			label = "wps";
52			linux,code = <KEY_WPS_BUTTON>;
53			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
54		};
55	};
56
57	leds {
58		compatible = "gpio-leds";
59
60		led-0 {
61			label = "bpi-r64:pio:green";
62			color = <LED_COLOR_ID_GREEN>;
63			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
64			default-state = "off";
65		};
66
67		led-1 {
68			label = "bpi-r64:pio:red";
69			color = <LED_COLOR_ID_RED>;
70			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
71			default-state = "off";
72		};
73	};
74
75	memory {
76		reg = <0 0x40000000 0 0x40000000>;
77	};
78
79	reg_1p8v: regulator-1p8v {
80		compatible = "regulator-fixed";
81		regulator-name = "fixed-1.8V";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <1800000>;
84		regulator-always-on;
85	};
86
87	reg_3p3v: regulator-3p3v {
88		compatible = "regulator-fixed";
89		regulator-name = "fixed-3.3V";
90		regulator-min-microvolt = <3300000>;
91		regulator-max-microvolt = <3300000>;
92		regulator-boot-on;
93		regulator-always-on;
94	};
95
96	reg_5v: regulator-5v {
97		compatible = "regulator-fixed";
98		regulator-name = "fixed-5V";
99		regulator-min-microvolt = <5000000>;
100		regulator-max-microvolt = <5000000>;
101		regulator-boot-on;
102		regulator-always-on;
103	};
104};
105
106&bch {
107	status = "disabled";
108};
109
110&btif {
111	status = "okay";
112};
113
114&cir {
115	pinctrl-names = "default";
116	pinctrl-0 = <&irrx_pins>;
117	status = "okay";
118};
119
120&eth {
121	status = "okay";
122	gmac0: mac@0 {
123		compatible = "mediatek,eth-mac";
124		reg = <0>;
125		phy-mode = "2500base-x";
126
127		fixed-link {
128			speed = <2500>;
129			full-duplex;
130			pause;
131		};
132	};
133
134	gmac1: mac@1 {
135		compatible = "mediatek,eth-mac";
136		reg = <1>;
137		phy-mode = "rgmii";
138
139		fixed-link {
140			speed = <1000>;
141			full-duplex;
142			pause;
143		};
144	};
145
146	mdio: mdio-bus {
147		#address-cells = <1>;
148		#size-cells = <0>;
149
150		switch@0 {
151			compatible = "mediatek,mt7531";
152			reg = <0>;
153			reset-gpios = <&pio 54 0>;
154
155			ports {
156				#address-cells = <1>;
157				#size-cells = <0>;
158
159				port@0 {
160					reg = <0>;
161					label = "wan";
162				};
163
164				port@1 {
165					reg = <1>;
166					label = "lan0";
167				};
168
169				port@2 {
170					reg = <2>;
171					label = "lan1";
172				};
173
174				port@3 {
175					reg = <3>;
176					label = "lan2";
177				};
178
179				port@4 {
180					reg = <4>;
181					label = "lan3";
182				};
183
184				port@6 {
185					reg = <6>;
186					label = "cpu";
187					ethernet = <&gmac0>;
188					phy-mode = "2500base-x";
189
190					fixed-link {
191						speed = <2500>;
192						full-duplex;
193						pause;
194					};
195				};
196			};
197		};
198
199	};
200};
201
202&i2c1 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&i2c1_pins>;
205	status = "okay";
206};
207
208&i2c2 {
209	pinctrl-names = "default";
210	pinctrl-0 = <&i2c2_pins>;
211	status = "okay";
212};
213
214&mmc0 {
215	pinctrl-names = "default", "state_uhs";
216	pinctrl-0 = <&emmc_pins_default>;
217	pinctrl-1 = <&emmc_pins_uhs>;
218	status = "okay";
219	bus-width = <8>;
220	max-frequency = <50000000>;
221	cap-mmc-highspeed;
222	mmc-hs200-1_8v;
223	vmmc-supply = <&reg_3p3v>;
224	vqmmc-supply = <&reg_1p8v>;
225	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
226	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
227	non-removable;
228};
229
230&mmc1 {
231	pinctrl-names = "default", "state_uhs";
232	pinctrl-0 = <&sd0_pins_default>;
233	pinctrl-1 = <&sd0_pins_uhs>;
234	status = "okay";
235	bus-width = <4>;
236	max-frequency = <50000000>;
237	cap-sd-highspeed;
238	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
239	vmmc-supply = <&reg_3p3v>;
240	vqmmc-supply = <&reg_3p3v>;
241	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
242	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
243};
244
245&nandc {
246	pinctrl-names = "default";
247	pinctrl-0 = <&parallel_nand_pins>;
248	status = "disabled";
249};
250
251&nor_flash {
252	pinctrl-names = "default";
253	pinctrl-0 = <&spi_nor_pins>;
254	status = "disabled";
255
256	flash@0 {
257		compatible = "jedec,spi-nor";
258		reg = <0>;
259	};
260};
261
262&pcie0 {
263	pinctrl-names = "default";
264	pinctrl-0 = <&pcie0_pins>;
265	status = "okay";
266};
267
268&pcie1 {
269	pinctrl-names = "default";
270	pinctrl-0 = <&pcie1_pins>;
271	status = "okay";
272};
273
274&pio {
275	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
276	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
277	 */
278	asm_sel {
279		gpio-hog;
280		gpios = <90 GPIO_ACTIVE_HIGH>;
281		output-high;
282	};
283
284	/* eMMC is shared pin with parallel NAND */
285	emmc_pins_default: emmc-pins-default {
286		mux {
287			function = "emmc", "emmc_rst";
288			groups = "emmc";
289		};
290
291		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
292		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
293		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
294		 */
295		conf-cmd-dat {
296			pins = "NDL0", "NDL1", "NDL2",
297			       "NDL3", "NDL4", "NDL5",
298			       "NDL6", "NDL7", "NRB";
299			input-enable;
300			bias-pull-up;
301		};
302
303		conf-clk {
304			pins = "NCLE";
305			bias-pull-down;
306		};
307	};
308
309	emmc_pins_uhs: emmc-pins-uhs {
310		mux {
311			function = "emmc";
312			groups = "emmc";
313		};
314
315		conf-cmd-dat {
316			pins = "NDL0", "NDL1", "NDL2",
317			       "NDL3", "NDL4", "NDL5",
318			       "NDL6", "NDL7", "NRB";
319			input-enable;
320			drive-strength = <4>;
321			bias-pull-up;
322		};
323
324		conf-clk {
325			pins = "NCLE";
326			drive-strength = <4>;
327			bias-pull-down;
328		};
329	};
330
331	eth_pins: eth-pins {
332		mux {
333			function = "eth";
334			groups = "mdc_mdio", "rgmii_via_gmac2";
335		};
336	};
337
338	i2c1_pins: i2c1-pins {
339		mux {
340			function = "i2c";
341			groups = "i2c1_0";
342		};
343	};
344
345	i2c2_pins: i2c2-pins {
346		mux {
347			function = "i2c";
348			groups = "i2c2_0";
349		};
350	};
351
352	i2s1_pins: i2s1-pins {
353		mux {
354			function = "i2s";
355			groups =  "i2s_out_mclk_bclk_ws",
356				  "i2s1_in_data",
357				  "i2s1_out_data";
358		};
359
360		conf {
361			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
362			       "I2S_WS", "I2S_MCLK";
363			drive-strength = <12>;
364			bias-pull-down;
365		};
366	};
367
368	irrx_pins: irrx-pins {
369		mux {
370			function = "ir";
371			groups = "ir_1_rx";
372		};
373	};
374
375	irtx_pins: irtx-pins {
376		mux {
377			function = "ir";
378			groups = "ir_1_tx";
379		};
380	};
381
382	/* Parallel nand is shared pin with eMMC */
383	parallel_nand_pins: parallel-nand-pins {
384		mux {
385			function = "flash";
386			groups = "par_nand";
387		};
388	};
389
390	pcie0_pins: pcie0-pins {
391		mux {
392			function = "pcie";
393			groups = "pcie0_pad_perst",
394				 "pcie0_1_waken",
395				 "pcie0_1_clkreq";
396		};
397	};
398
399	pcie1_pins: pcie1-pins {
400		mux {
401			function = "pcie";
402			groups = "pcie1_pad_perst",
403				 "pcie1_0_waken",
404				 "pcie1_0_clkreq";
405		};
406	};
407
408	pmic_bus_pins: pmic-bus-pins {
409		mux {
410			function = "pmic";
411			groups = "pmic_bus";
412		};
413	};
414
415	pwm_pins: pwm-pins {
416		mux {
417			function = "pwm";
418			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
419				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
420				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
421				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
422				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
423				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
424		};
425	};
426
427	wled_pins: wled-pins {
428		mux {
429			function = "led";
430			groups = "wled";
431		};
432	};
433
434	sd0_pins_default: sd0-pins-default {
435		mux {
436			function = "sd";
437			groups = "sd_0";
438		};
439
440		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
441		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
442		 *  DAT2, DAT3, CMD, CLK for SD respectively.
443		 */
444		conf-cmd-data {
445			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
446			       "I2S2_IN","I2S4_OUT";
447			input-enable;
448			drive-strength = <8>;
449			bias-pull-up;
450		};
451		conf-clk {
452			pins = "I2S3_OUT";
453			drive-strength = <12>;
454			bias-pull-down;
455		};
456		conf-cd {
457			pins = "TXD3";
458			bias-pull-up;
459		};
460	};
461
462	sd0_pins_uhs: sd0-pins-uhs {
463		mux {
464			function = "sd";
465			groups = "sd_0";
466		};
467
468		conf-cmd-data {
469			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
470			       "I2S2_IN","I2S4_OUT";
471			input-enable;
472			bias-pull-up;
473		};
474
475		conf-clk {
476			pins = "I2S3_OUT";
477			bias-pull-down;
478		};
479	};
480
481	/* Serial NAND is shared pin with SPI-NOR */
482	serial_nand_pins: serial-nand-pins {
483		mux {
484			function = "flash";
485			groups = "snfi";
486		};
487	};
488
489	spic0_pins: spic0-pins {
490		mux {
491			function = "spi";
492			groups = "spic0_0";
493		};
494	};
495
496	spic1_pins: spic1-pins {
497		mux {
498			function = "spi";
499			groups = "spic1_0";
500		};
501	};
502
503	/* SPI-NOR is shared pin with serial NAND */
504	spi_nor_pins: spi-nor-pins {
505		mux {
506			function = "flash";
507			groups = "spi_nor";
508		};
509	};
510
511	/* serial NAND is shared pin with SPI-NOR */
512	serial_nand_pins: serial-nand-pins {
513		mux {
514			function = "flash";
515			groups = "snfi";
516		};
517	};
518
519	uart0_pins: uart0-pins {
520		mux {
521			function = "uart";
522			groups = "uart0_0_tx_rx" ;
523		};
524	};
525
526	uart2_pins: uart2-pins {
527		mux {
528			function = "uart";
529			groups = "uart2_1_tx_rx" ;
530		};
531	};
532
533	watchdog_pins: watchdog-pins {
534		mux {
535			function = "watchdog";
536			groups = "watchdog";
537		};
538	};
539};
540
541&pwm {
542	pinctrl-names = "default";
543	pinctrl-0 = <&pwm_pins>;
544	status = "okay";
545};
546
547&pwrap {
548	pinctrl-names = "default";
549	pinctrl-0 = <&pmic_bus_pins>;
550
551	status = "okay";
552};
553
554&sata {
555	status = "disable";
556};
557
558&sata_phy {
559	status = "disable";
560};
561
562&spi0 {
563	pinctrl-names = "default";
564	pinctrl-0 = <&spic0_pins>;
565	status = "okay";
566};
567
568&spi1 {
569	pinctrl-names = "default";
570	pinctrl-0 = <&spic1_pins>;
571};
572
573&ssusb {
574	vusb33-supply = <&reg_3p3v>;
575	vbus-supply = <&reg_5v>;
576	status = "okay";
577};
578
579&u3phy {
580	status = "okay";
581};
582
583&uart0 {
584	pinctrl-names = "default";
585	pinctrl-0 = <&uart0_pins>;
586	status = "okay";
587};
588
589&uart2 {
590	pinctrl-names = "default";
591	pinctrl-0 = <&uart2_pins>;
592};
593
594&watchdog {
595	pinctrl-names = "default";
596	pinctrl-0 = <&watchdog_pins>;
597	status = "okay";
598};
599
600&wmac {
601	status = "okay";
602};
603