1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Copyright (C) 2023 Collabora Ltd. 5 * Authors: Mars.C <mars.cheng@mediatek.com> 6 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/mediatek,mt6795-clk.h> 12#include <dt-bindings/gce/mediatek,mt6795-gce.h> 13#include <dt-bindings/memory/mt6795-larb-port.h> 14#include <dt-bindings/pinctrl/mt6795-pinfunc.h> 15#include <dt-bindings/power/mt6795-power.h> 16#include <dt-bindings/reset/mediatek,mt6795-resets.h> 17 18/ { 19 compatible = "mediatek,mt6795"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl1 = &ovl1; 27 rdma0 = &rdma0; 28 rdma1 = &rdma1; 29 rdma2 = &rdma2; 30 wdma0 = &wdma0; 31 wdma1 = &wdma1; 32 color0 = &color0; 33 color1 = &color1; 34 split0 = &split0; 35 split1 = &split1; 36 dpi0 = &dpi0; 37 dsi0 = &dsi0; 38 dsi1 = &dsi1; 39 }; 40 41 psci { 42 compatible = "arm,psci-0.2"; 43 method = "smc"; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 enable-method = "psci"; 54 reg = <0x000>; 55 cci-control-port = <&cci_control2>; 56 next-level-cache = <&l2_0>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x001>; 64 cci-control-port = <&cci_control2>; 65 i-cache-size = <32768>; 66 i-cache-line-size = <64>; 67 i-cache-sets = <256>; 68 d-cache-size = <32768>; 69 d-cache-line-size = <64>; 70 d-cache-sets = <128>; 71 next-level-cache = <&l2_0>; 72 }; 73 74 cpu2: cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 enable-method = "psci"; 78 reg = <0x002>; 79 cci-control-port = <&cci_control2>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <256>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_0>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 enable-method = "psci"; 93 reg = <0x003>; 94 cci-control-port = <&cci_control2>; 95 i-cache-size = <32768>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <32768>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&l2_0>; 102 }; 103 104 cpu4: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 enable-method = "psci"; 108 reg = <0x100>; 109 cci-control-port = <&cci_control1>; 110 i-cache-size = <32768>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; 113 d-cache-size = <32768>; 114 d-cache-line-size = <64>; 115 d-cache-sets = <128>; 116 next-level-cache = <&l2_1>; 117 }; 118 119 cpu5: cpu@101 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a53"; 122 enable-method = "psci"; 123 reg = <0x101>; 124 cci-control-port = <&cci_control1>; 125 i-cache-size = <32768>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <256>; 128 d-cache-size = <32768>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&l2_1>; 132 }; 133 134 cpu6: cpu@102 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 enable-method = "psci"; 138 reg = <0x102>; 139 cci-control-port = <&cci_control1>; 140 i-cache-size = <32768>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <32768>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <128>; 146 next-level-cache = <&l2_1>; 147 }; 148 149 cpu7: cpu@103 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a53"; 152 enable-method = "psci"; 153 reg = <0x103>; 154 cci-control-port = <&cci_control1>; 155 i-cache-size = <32768>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <256>; 158 d-cache-size = <32768>; 159 d-cache-line-size = <64>; 160 d-cache-sets = <128>; 161 next-level-cache = <&l2_1>; 162 }; 163 164 cpu-map { 165 cluster0 { 166 core0 { 167 cpu = <&cpu0>; 168 }; 169 170 core1 { 171 cpu = <&cpu1>; 172 }; 173 174 core2 { 175 cpu = <&cpu2>; 176 }; 177 178 core3 { 179 cpu = <&cpu3>; 180 }; 181 }; 182 183 cluster1 { 184 core0 { 185 cpu = <&cpu4>; 186 }; 187 188 core1 { 189 cpu = <&cpu5>; 190 }; 191 192 core2 { 193 cpu = <&cpu6>; 194 }; 195 196 core3 { 197 cpu = <&cpu7>; 198 }; 199 }; 200 }; 201 202 l2_0: l2-cache0 { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-size = <1048576>; 206 cache-line-size = <64>; 207 cache-sets = <1024>; 208 cache-unified; 209 }; 210 211 l2_1: l2-cache1 { 212 compatible = "cache"; 213 cache-level = <2>; 214 cache-size = <1048576>; 215 cache-line-size = <64>; 216 cache-sets = <1024>; 217 cache-unified; 218 }; 219 }; 220 221 clk26m: oscillator-26m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <26000000>; 225 clock-output-names = "clk26m"; 226 }; 227 228 clk32k: oscillator-32k { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <32000>; 232 clock-output-names = "clk32k"; 233 }; 234 235 system_clk: dummy13m { 236 compatible = "fixed-clock"; 237 clock-frequency = <13000000>; 238 #clock-cells = <0>; 239 }; 240 241 pmu { 242 compatible = "arm,cortex-a53-pmu"; 243 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 244 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 245 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 246 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 247 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 248 }; 249 250 timer { 251 compatible = "arm,armv8-timer"; 252 interrupt-parent = <&gic>; 253 interrupts = <GIC_PPI 13 254 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 255 <GIC_PPI 14 256 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 257 <GIC_PPI 11 258 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 259 <GIC_PPI 10 260 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 261 }; 262 263 soc { 264 #address-cells = <2>; 265 #size-cells = <2>; 266 compatible = "simple-bus"; 267 ranges; 268 269 topckgen: syscon@10000000 { 270 compatible = "mediatek,mt6795-topckgen", "syscon"; 271 reg = <0 0x10000000 0 0x1000>; 272 #clock-cells = <1>; 273 }; 274 275 infracfg: syscon@10001000 { 276 compatible = "mediatek,mt6795-infracfg", "syscon"; 277 reg = <0 0x10001000 0 0x1000>; 278 #clock-cells = <1>; 279 #reset-cells = <1>; 280 }; 281 282 pericfg: syscon@10003000 { 283 compatible = "mediatek,mt6795-pericfg", "syscon"; 284 reg = <0 0x10003000 0 0x1000>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 }; 288 289 scpsys: syscon@10006000 { 290 compatible = "syscon", "simple-mfd"; 291 reg = <0 0x10006000 0 0x1000>; 292 #power-domain-cells = <1>; 293 294 /* System Power Manager */ 295 spm: power-controller { 296 compatible = "mediatek,mt6795-power-controller"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 #power-domain-cells = <1>; 300 301 /* power domains of the SoC */ 302 power-domain@MT6795_POWER_DOMAIN_VDEC { 303 reg = <MT6795_POWER_DOMAIN_VDEC>; 304 clocks = <&topckgen CLK_TOP_MM_SEL>; 305 clock-names = "mm"; 306 #power-domain-cells = <0>; 307 }; 308 power-domain@MT6795_POWER_DOMAIN_VENC { 309 reg = <MT6795_POWER_DOMAIN_VENC>; 310 clocks = <&topckgen CLK_TOP_MM_SEL>, 311 <&topckgen CLK_TOP_VENC_SEL>; 312 clock-names = "mm", "venc"; 313 #power-domain-cells = <0>; 314 }; 315 power-domain@MT6795_POWER_DOMAIN_ISP { 316 reg = <MT6795_POWER_DOMAIN_ISP>; 317 clocks = <&topckgen CLK_TOP_MM_SEL>; 318 clock-names = "mm"; 319 #power-domain-cells = <0>; 320 }; 321 322 power-domain@MT6795_POWER_DOMAIN_MM { 323 reg = <MT6795_POWER_DOMAIN_MM>; 324 clocks = <&topckgen CLK_TOP_MM_SEL>; 325 clock-names = "mm"; 326 #power-domain-cells = <0>; 327 mediatek,infracfg = <&infracfg>; 328 }; 329 330 power-domain@MT6795_POWER_DOMAIN_MJC { 331 reg = <MT6795_POWER_DOMAIN_MJC>; 332 clocks = <&topckgen CLK_TOP_MM_SEL>, 333 <&topckgen CLK_TOP_MJC_SEL>; 334 clock-names = "mm", "mjc"; 335 #power-domain-cells = <0>; 336 }; 337 338 power-domain@MT6795_POWER_DOMAIN_AUDIO { 339 reg = <MT6795_POWER_DOMAIN_AUDIO>; 340 #power-domain-cells = <0>; 341 }; 342 343 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { 344 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; 345 clocks = <&clk26m>; 346 clock-names = "mfg"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 #power-domain-cells = <1>; 350 351 power-domain@MT6795_POWER_DOMAIN_MFG_2D { 352 reg = <MT6795_POWER_DOMAIN_MFG_2D>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 #power-domain-cells = <1>; 356 357 power-domain@MT6795_POWER_DOMAIN_MFG { 358 reg = <MT6795_POWER_DOMAIN_MFG>; 359 #power-domain-cells = <0>; 360 mediatek,infracfg = <&infracfg>; 361 }; 362 }; 363 }; 364 }; 365 }; 366 367 pio: pinctrl@10005000 { 368 compatible = "mediatek,mt6795-pinctrl"; 369 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 370 reg-names = "base", "eint"; 371 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 gpio-ranges = <&pio 0 0 196>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 380 watchdog: watchdog@10007000 { 381 compatible = "mediatek,mt6795-wdt"; 382 reg = <0 0x10007000 0 0x100>; 383 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 384 #reset-cells = <1>; 385 timeout-sec = <20>; 386 }; 387 388 timer: timer@10008000 { 389 compatible = "mediatek,mt6795-timer", 390 "mediatek,mt6577-timer"; 391 reg = <0 0x10008000 0 0x1000>; 392 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 393 clocks = <&system_clk>, <&clk32k>; 394 }; 395 396 pwrap: pwrap@1000d000 { 397 compatible = "mediatek,mt6795-pwrap"; 398 reg = <0 0x1000d000 0 0x1000>; 399 reg-names = "pwrap"; 400 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 401 resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>; 402 reset-names = "pwrap"; 403 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>; 404 clock-names = "spi", "wrap"; 405 }; 406 407 sysirq: intpol-controller@10200620 { 408 compatible = "mediatek,mt6795-sysirq", 409 "mediatek,mt6577-sysirq"; 410 interrupt-controller; 411 #interrupt-cells = <3>; 412 interrupt-parent = <&gic>; 413 reg = <0 0x10200620 0 0x20>; 414 }; 415 416 systimer: timer@10200670 { 417 compatible = "mediatek,mt6795-systimer"; 418 reg = <0 0x10200670 0 0x10>; 419 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&system_clk>; 421 clock-names = "clk13m"; 422 }; 423 424 iommu: iommu@10205000 { 425 compatible = "mediatek,mt6795-m4u"; 426 reg = <0 0x10205000 0 0x1000>; 427 clocks = <&infracfg CLK_INFRA_M4U>; 428 clock-names = "bclk"; 429 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; 430 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; 431 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 432 #iommu-cells = <1>; 433 }; 434 435 apmixedsys: syscon@10209000 { 436 compatible = "mediatek,mt6795-apmixedsys", "syscon"; 437 reg = <0 0x10209000 0 0x1000>; 438 #clock-cells = <1>; 439 }; 440 441 fhctl: clock-controller@10209f00 { 442 compatible = "mediatek,mt6795-fhctl"; 443 reg = <0 0x10209f00 0 0x100>; 444 status = "disabled"; 445 }; 446 447 gce: mailbox@10212000 { 448 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; 449 reg = <0 0x10212000 0 0x1000>; 450 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 451 clocks = <&infracfg CLK_INFRA_GCE>; 452 clock-names = "gce"; 453 #mbox-cells = <2>; 454 }; 455 456 mipi_tx0: dsi-phy@10215000 { 457 compatible = "mediatek,mt8173-mipi-tx"; 458 reg = <0 0x10215000 0 0x1000>; 459 clocks = <&clk26m>; 460 clock-output-names = "mipi_tx0_pll"; 461 #clock-cells = <0>; 462 #phy-cells = <0>; 463 status = "disabled"; 464 }; 465 466 mipi_tx1: dsi-phy@10216000 { 467 compatible = "mediatek,mt8173-mipi-tx"; 468 reg = <0 0x10216000 0 0x1000>; 469 clocks = <&clk26m>; 470 clock-output-names = "mipi_tx1_pll"; 471 #clock-cells = <0>; 472 #phy-cells = <0>; 473 status = "disabled"; 474 }; 475 476 gic: interrupt-controller@10221000 { 477 compatible = "arm,gic-400"; 478 #interrupt-cells = <3>; 479 interrupt-parent = <&gic>; 480 interrupt-controller; 481 reg = <0 0x10221000 0 0x1000>, 482 <0 0x10222000 0 0x2000>, 483 <0 0x10224000 0 0x2000>, 484 <0 0x10226000 0 0x2000>; 485 interrupts = <GIC_PPI 9 486 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 487 }; 488 489 cci: cci@10390000 { 490 compatible = "arm,cci-400"; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 reg = <0 0x10390000 0 0x1000>; 494 ranges = <0 0 0x10390000 0x10000>; 495 496 cci_control0: slave-if@1000 { 497 compatible = "arm,cci-400-ctrl-if"; 498 interface-type = "ace-lite"; 499 reg = <0x1000 0x1000>; 500 }; 501 502 cci_control1: slave-if@4000 { 503 compatible = "arm,cci-400-ctrl-if"; 504 interface-type = "ace"; 505 reg = <0x4000 0x1000>; 506 }; 507 508 cci_control2: slave-if@5000 { 509 compatible = "arm,cci-400-ctrl-if"; 510 interface-type = "ace"; 511 reg = <0x5000 0x1000>; 512 }; 513 514 pmu@9000 { 515 compatible = "arm,cci-400-pmu,r1"; 516 reg = <0x9000 0x5000>; 517 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 522 }; 523 }; 524 525 uart0: serial@11002000 { 526 compatible = "mediatek,mt6795-uart", 527 "mediatek,mt6577-uart"; 528 reg = <0 0x11002000 0 0x400>; 529 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 530 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 531 clock-names = "baud", "bus"; 532 dmas = <&apdma 0>, <&apdma 1>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 uart1: serial@11003000 { 538 compatible = "mediatek,mt6795-uart", 539 "mediatek,mt6577-uart"; 540 reg = <0 0x11003000 0 0x400>; 541 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 543 clock-names = "baud", "bus"; 544 dmas = <&apdma 2>, <&apdma 3>; 545 dma-names = "tx", "rx"; 546 status = "disabled"; 547 }; 548 549 apdma: dma-controller@11000380 { 550 compatible = "mediatek,mt6795-uart-dma", 551 "mediatek,mt6577-uart-dma"; 552 reg = <0 0x11000380 0 0x60>, 553 <0 0x11000400 0 0x60>, 554 <0 0x11000480 0 0x60>, 555 <0 0x11000500 0 0x60>, 556 <0 0x11000580 0 0x60>, 557 <0 0x11000600 0 0x60>, 558 <0 0x11000680 0 0x60>, 559 <0 0x11000700 0 0x60>; 560 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 561 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 562 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 563 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 564 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 565 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 566 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 567 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 568 dma-requests = <8>; 569 clocks = <&pericfg CLK_PERI_AP_DMA>; 570 clock-names = "apdma"; 571 mediatek,dma-33bits; 572 #dma-cells = <1>; 573 }; 574 575 uart2: serial@11004000 { 576 compatible = "mediatek,mt6795-uart", 577 "mediatek,mt6577-uart"; 578 reg = <0 0x11004000 0 0x400>; 579 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 580 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 581 clock-names = "baud", "bus"; 582 dmas = <&apdma 4>, <&apdma 5>; 583 dma-names = "tx", "rx"; 584 status = "disabled"; 585 }; 586 587 uart3: serial@11005000 { 588 compatible = "mediatek,mt6795-uart", 589 "mediatek,mt6577-uart"; 590 reg = <0 0x11005000 0 0x400>; 591 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 592 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 593 clock-names = "baud", "bus"; 594 dmas = <&apdma 6>, <&apdma 7>; 595 dma-names = "tx", "rx"; 596 status = "disabled"; 597 }; 598 599 pwm2: pwm@11006000 { 600 compatible = "mediatek,mt6795-pwm"; 601 reg = <0 0x11006000 0 0x1000>; 602 #pwm-cells = <2>; 603 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 604 clocks = <&topckgen CLK_TOP_PWM_SEL>, 605 <&pericfg CLK_PERI_PWM>, 606 <&pericfg CLK_PERI_PWM1>, 607 <&pericfg CLK_PERI_PWM2>, 608 <&pericfg CLK_PERI_PWM3>, 609 <&pericfg CLK_PERI_PWM4>, 610 <&pericfg CLK_PERI_PWM5>, 611 <&pericfg CLK_PERI_PWM6>, 612 <&pericfg CLK_PERI_PWM7>; 613 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 614 "pwm4", "pwm5", "pwm6", "pwm7"; 615 status = "disabled"; 616 }; 617 618 i2c0: i2c@11007000 { 619 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 620 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; 621 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 622 clock-div = <16>; 623 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 624 clock-names = "main", "dma"; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 630 i2c1: i2c@11008000 { 631 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 632 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; 633 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 634 clock-div = <16>; 635 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 636 clock-names = "main", "dma"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 status = "disabled"; 640 }; 641 642 i2c2: i2c@11009000 { 643 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 644 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; 645 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 646 clock-div = <16>; 647 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 648 clock-names = "main", "dma"; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 status = "disabled"; 652 }; 653 654 i2c3: i2c@11010000 { 655 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 656 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; 657 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 658 clock-div = <16>; 659 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; 660 clock-names = "main", "dma"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "disabled"; 664 }; 665 666 i2c4: i2c@11011000 { 667 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 668 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; 669 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 670 clock-div = <16>; 671 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; 672 clock-names = "main", "dma"; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 status = "disabled"; 676 }; 677 678 mmc0: mmc@11230000 { 679 compatible = "mediatek,mt6795-mmc"; 680 reg = <0 0x11230000 0 0x1000>; 681 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 682 clocks = <&pericfg CLK_PERI_MSDC30_0>, 683 <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 684 <&topckgen CLK_TOP_MSDC50_0_SEL>; 685 clock-names = "source", "hclk", "source_cg"; 686 status = "disabled"; 687 }; 688 689 mmc1: mmc@11240000 { 690 compatible = "mediatek,mt6795-mmc"; 691 reg = <0 0x11240000 0 0x1000>; 692 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 693 clocks = <&pericfg CLK_PERI_MSDC30_1>, 694 <&topckgen CLK_TOP_AXI_SEL>; 695 clock-names = "source", "hclk"; 696 status = "disabled"; 697 }; 698 699 mmc2: mmc@11250000 { 700 compatible = "mediatek,mt6795-mmc"; 701 reg = <0 0x11250000 0 0x1000>; 702 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 703 clocks = <&pericfg CLK_PERI_MSDC30_2>, 704 <&topckgen CLK_TOP_AXI_SEL>; 705 clock-names = "source", "hclk"; 706 status = "disabled"; 707 }; 708 709 mmc3: mmc@11260000 { 710 compatible = "mediatek,mt6795-mmc"; 711 reg = <0 0x11260000 0 0x1000>; 712 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 713 clocks = <&pericfg CLK_PERI_MSDC30_3>, 714 <&topckgen CLK_TOP_AXI_SEL>; 715 clock-names = "source", "hclk"; 716 status = "disabled"; 717 }; 718 719 mmsys: syscon@14000000 { 720 compatible = "mediatek,mt6795-mmsys", "syscon"; 721 reg = <0 0x14000000 0 0x1000>; 722 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 723 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 724 assigned-clock-rates = <400000000>; 725 #clock-cells = <1>; 726 #reset-cells = <1>; 727 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 728 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 729 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 730 }; 731 732 ovl0: ovl@1400c000 { 733 compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; 734 reg = <0 0x1400c000 0 0x1000>; 735 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 736 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 737 clocks = <&mmsys CLK_MM_DISP_OVL0>; 738 iommus = <&iommu M4U_PORT_DISP_OVL0>; 739 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 740 }; 741 742 ovl1: ovl@1400d000 { 743 compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; 744 reg = <0 0x1400d000 0 0x1000>; 745 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 746 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 747 clocks = <&mmsys CLK_MM_DISP_OVL1>; 748 iommus = <&iommu M4U_PORT_DISP_OVL1>; 749 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 750 }; 751 752 rdma0: rdma@1400e000 { 753 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; 754 reg = <0 0x1400e000 0 0x1000>; 755 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 756 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 757 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 758 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 759 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 760 }; 761 762 rdma1: rdma@1400f000 { 763 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; 764 reg = <0 0x1400f000 0 0x1000>; 765 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 766 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 767 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 768 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 769 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 770 }; 771 772 rdma2: rdma@14010000 { 773 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; 774 reg = <0 0x14010000 0 0x1000>; 775 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 776 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 777 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 778 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 779 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 780 }; 781 782 wdma0: wdma@14011000 { 783 compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; 784 reg = <0 0x14011000 0 0x1000>; 785 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 786 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 787 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 788 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 789 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 790 }; 791 792 wdma1: wdma@14012000 { 793 compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; 794 reg = <0 0x14012000 0 0x1000>; 795 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 796 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 797 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 798 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 799 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 800 }; 801 802 color0: color@14013000 { 803 compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; 804 reg = <0 0x14013000 0 0x1000>; 805 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 806 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 807 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 808 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 809 }; 810 811 color1: color@14014000 { 812 compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; 813 reg = <0 0x14014000 0 0x1000>; 814 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; 815 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 816 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 817 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 818 }; 819 820 aal@14015000 { 821 compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal"; 822 reg = <0 0x14015000 0 0x1000>; 823 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 824 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 825 clocks = <&mmsys CLK_MM_DISP_AAL>; 826 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 827 }; 828 829 gamma@14016000 { 830 compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma"; 831 reg = <0 0x14016000 0 0x1000>; 832 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 833 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 834 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 835 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 836 }; 837 838 merge@14017000 { 839 compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge"; 840 reg = <0 0x14017000 0 0x1000>; 841 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 842 clocks = <&mmsys CLK_MM_DISP_MERGE>; 843 }; 844 845 split0: split@14018000 { 846 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; 847 reg = <0 0x14018000 0 0x1000>; 848 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 849 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 850 }; 851 852 split1: split@14019000 { 853 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; 854 reg = <0 0x14019000 0 0x1000>; 855 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 856 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 857 }; 858 859 ufoe@1401a000 { 860 compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe"; 861 reg = <0 0x1401a000 0 0x1000>; 862 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>; 863 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 864 clocks = <&mmsys CLK_MM_DISP_UFOE>; 865 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 866 }; 867 868 dsi0: dsi@1401b000 { 869 compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; 870 reg = <0 0x1401b000 0 0x1000>; 871 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; 872 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 873 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 874 <&mmsys CLK_MM_DSI0_DIGITAL>, 875 <&mipi_tx0>; 876 clock-names = "engine", "digital", "hs"; 877 phys = <&mipi_tx0>; 878 phy-names = "dphy"; 879 status = "disabled"; 880 }; 881 882 dsi1: dsi@1401c000 { 883 compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; 884 reg = <0 0x1401c000 0 0x1000>; 885 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>; 886 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 887 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 888 <&mmsys CLK_MM_DSI1_DIGITAL>, 889 <&mipi_tx1>; 890 clock-names = "engine", "digital", "hs"; 891 phys = <&mipi_tx1>; 892 phy-names = "dphy"; 893 status = "disabled"; 894 }; 895 896 dpi0: dpi@1401d000 { 897 compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi"; 898 reg = <0 0x1401d000 0 0x1000>; 899 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 900 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 901 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 902 <&mmsys CLK_MM_DPI_ENGINE>, 903 <&apmixedsys CLK_APMIXED_TVDPLL>; 904 clock-names = "pixel", "engine", "pll"; 905 status = "disabled"; 906 }; 907 908 pwm0: pwm@1401e000 { 909 compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; 910 reg = <0 0x1401e000 0 0x1000>; 911 #pwm-cells = <2>; 912 clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; 913 clock-names = "main", "mm"; 914 status = "disabled"; 915 }; 916 917 pwm1: pwm@1401f000 { 918 compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; 919 reg = <0 0x1401f000 0 0x1000>; 920 #pwm-cells = <2>; 921 clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>; 922 clock-names = "main", "mm"; 923 status = "disabled"; 924 }; 925 926 mutex: mutex@14020000 { 927 compatible = "mediatek,mt8173-disp-mutex"; 928 reg = <0 0x14020000 0 0x1000>; 929 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>; 930 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 931 clocks = <&mmsys CLK_MM_MUTEX_32K>; 932 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 933 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 934 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 935 }; 936 937 larb0: larb@14021000 { 938 compatible = "mediatek,mt6795-smi-larb"; 939 reg = <0 0x14021000 0 0x1000>; 940 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; 941 clock-names = "apb", "smi"; 942 mediatek,smi = <&smi_common>; 943 mediatek,larb-id = <0>; 944 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 945 }; 946 947 smi_common: smi@14022000 { 948 compatible = "mediatek,mt6795-smi-common"; 949 reg = <0 0x14022000 0 0x1000>; 950 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 951 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; 952 clock-names = "apb", "smi"; 953 }; 954 955 od@14023000 { 956 compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od"; 957 reg = <0 0x14023000 0 0x1000>; 958 clocks = <&mmsys CLK_MM_DISP_OD>; 959 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 960 }; 961 962 larb2: larb@15001000 { 963 compatible = "mediatek,mt6795-smi-larb"; 964 reg = <0 0x15001000 0 0x1000>; 965 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; 966 clock-names = "apb", "smi"; 967 mediatek,smi = <&smi_common>; 968 mediatek,larb-id = <2>; 969 power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; 970 }; 971 972 vdecsys: clock-controller@16000000 { 973 compatible = "mediatek,mt6795-vdecsys"; 974 reg = <0 0x16000000 0 0x1000>; 975 #clock-cells = <1>; 976 }; 977 978 larb1: larb@16010000 { 979 compatible = "mediatek,mt6795-smi-larb"; 980 reg = <0 0x16010000 0 0x1000>; 981 mediatek,smi = <&smi_common>; 982 mediatek,larb-id = <1>; 983 clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; 984 clock-names = "apb", "smi"; 985 power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; 986 }; 987 988 vencsys: clock-controller@18000000 { 989 compatible = "mediatek,mt6795-vencsys"; 990 reg = <0 0x18000000 0 0x1000>; 991 #clock-cells = <1>; 992 }; 993 994 larb3: larb@18001000 { 995 compatible = "mediatek,mt6795-smi-larb"; 996 reg = <0 0x18001000 0 0x1000>; 997 clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; 998 clock-names = "apb", "smi"; 999 mediatek,smi = <&smi_common>; 1000 mediatek,larb-id = <3>; 1001 power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; 1002 }; 1003 }; 1004}; 1005