1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Mars.C <mars.cheng@mediatek.com> 5 * 6 */ 7 8#include <dt-bindings/clock/mt6779-clk.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/mt6779-pinfunc.h> 12 13/ { 14 compatible = "mediatek,mt6779"; 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 psci { 20 compatible = "arm,psci-0.2"; 21 method = "smc"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a55"; 31 enable-method = "psci"; 32 reg = <0x000>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a55"; 38 enable-method = "psci"; 39 reg = <0x100>; 40 }; 41 42 cpu2: cpu@2 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a55"; 45 enable-method = "psci"; 46 reg = <0x200>; 47 }; 48 49 cpu3: cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 enable-method = "psci"; 53 reg = <0x300>; 54 }; 55 56 cpu4: cpu@4 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 enable-method = "psci"; 60 reg = <0x400>; 61 }; 62 63 cpu5: cpu@5 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 enable-method = "psci"; 67 reg = <0x500>; 68 }; 69 70 cpu6: cpu@6 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a75"; 73 enable-method = "psci"; 74 reg = <0x600>; 75 }; 76 77 cpu7: cpu@7 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a75"; 80 enable-method = "psci"; 81 reg = <0x700>; 82 }; 83 }; 84 85 pmu { 86 compatible = "arm,armv8-pmuv3"; 87 interrupt-parent = <&gic>; 88 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; 89 }; 90 91 clk26m: oscillator@0 { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <26000000>; 95 clock-output-names = "clk26m"; 96 }; 97 98 clk32k: oscillator@1 { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <32768>; 102 clock-output-names = "clk32k"; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupt-parent = <&gic>; 108 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 109 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 110 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 111 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 112 }; 113 114 soc { 115 #address-cells = <2>; 116 #size-cells = <2>; 117 compatible = "simple-bus"; 118 ranges; 119 120 gic: interrupt-controller@0c000000 { 121 compatible = "arm,gic-v3"; 122 #interrupt-cells = <4>; 123 interrupt-parent = <&gic>; 124 interrupt-controller; 125 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 126 <0 0x0c040000 0 0x200000>; /* GICR */ 127 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 128 129 ppi-partitions { 130 ppi_cluster0: interrupt-partition-0 { 131 affinity = <&cpu0 &cpu1 \ 132 &cpu2 &cpu3 &cpu4 &cpu5>; 133 }; 134 ppi_cluster1: interrupt-partition-1 { 135 affinity = <&cpu6 &cpu7>; 136 }; 137 }; 138 139 }; 140 141 sysirq: intpol-controller@0c53a650 { 142 compatible = "mediatek,mt6779-sysirq", 143 "mediatek,mt6577-sysirq"; 144 interrupt-controller; 145 #interrupt-cells = <3>; 146 interrupt-parent = <&gic>; 147 reg = <0 0x0c53a650 0 0x50>; 148 }; 149 150 topckgen: clock-controller@10000000 { 151 compatible = "mediatek,mt6779-topckgen", "syscon"; 152 reg = <0 0x10000000 0 0x1000>; 153 #clock-cells = <1>; 154 }; 155 156 infracfg_ao: clock-controller@10001000 { 157 compatible = "mediatek,mt6779-infracfg_ao", "syscon"; 158 reg = <0 0x10001000 0 0x1000>; 159 #clock-cells = <1>; 160 }; 161 162 pio: pinctrl@10005000 { 163 compatible = "mediatek,mt6779-pinctrl", "syscon"; 164 reg = <0 0x10005000 0 0x1000>, 165 <0 0x11c20000 0 0x1000>, 166 <0 0x11d10000 0 0x1000>, 167 <0 0x11e20000 0 0x1000>, 168 <0 0x11e70000 0 0x1000>, 169 <0 0x11ea0000 0 0x1000>, 170 <0 0x11f20000 0 0x1000>, 171 <0 0x11f30000 0 0x1000>, 172 <0 0x1000b000 0 0x1000>; 173 reg-names = "gpio", "iocfg_rm", 174 "iocfg_br", "iocfg_lm", 175 "iocfg_lb", "iocfg_rt", 176 "iocfg_lt", "iocfg_tl", 177 "eint"; 178 gpio-controller; 179 #gpio-cells = <2>; 180 gpio-ranges = <&pio 0 0 210>; 181 interrupt-controller; 182 #interrupt-cells = <2>; 183 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 186 apmixed: clock-controller@1000c000 { 187 compatible = "mediatek,mt6779-apmixed", "syscon"; 188 reg = <0 0x1000c000 0 0xe00>; 189 #clock-cells = <1>; 190 }; 191 192 pwrap: pwrap@1000d000 { 193 compatible = "mediatek,mt6779-pwrap"; 194 reg = <0 0x1000d000 0 0x1000>; 195 reg-names = "pwrap"; 196 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>; 198 clock-names = "spi", "wrap"; 199 }; 200 201 devapc: devapc@10207000 { 202 compatible = "mediatek,mt6779-devapc"; 203 reg = <0 0x10207000 0 0x1000>; 204 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 205 clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>; 206 clock-names = "devapc-infra-clock"; 207 }; 208 209 uart0: serial@11002000 { 210 compatible = "mediatek,mt6779-uart", 211 "mediatek,mt6577-uart"; 212 reg = <0 0x11002000 0 0x400>; 213 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 214 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; 215 clock-names = "baud", "bus"; 216 status = "disabled"; 217 }; 218 219 uart1: serial@11003000 { 220 compatible = "mediatek,mt6779-uart", 221 "mediatek,mt6577-uart"; 222 reg = <0 0x11003000 0 0x400>; 223 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; 224 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; 225 clock-names = "baud", "bus"; 226 status = "disabled"; 227 }; 228 229 uart2: serial@11004000 { 230 compatible = "mediatek,mt6779-uart", 231 "mediatek,mt6577-uart"; 232 reg = <0 0x11004000 0 0x400>; 233 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; 234 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; 235 clock-names = "baud", "bus"; 236 status = "disabled"; 237 }; 238 239 audio: clock-controller@11210000 { 240 compatible = "mediatek,mt6779-audio", "syscon"; 241 reg = <0 0x11210000 0 0x1000>; 242 #clock-cells = <1>; 243 }; 244 245 mfgcfg: clock-controller@13fbf000 { 246 compatible = "mediatek,mt6779-mfgcfg", "syscon"; 247 reg = <0 0x13fbf000 0 0x1000>; 248 #clock-cells = <1>; 249 }; 250 251 mmsys: syscon@14000000 { 252 compatible = "mediatek,mt6779-mmsys", "syscon"; 253 reg = <0 0x14000000 0 0x1000>; 254 #clock-cells = <1>; 255 }; 256 257 imgsys: clock-controller@15020000 { 258 compatible = "mediatek,mt6779-imgsys", "syscon"; 259 reg = <0 0x15020000 0 0x1000>; 260 #clock-cells = <1>; 261 }; 262 263 vdecsys: clock-controller@16000000 { 264 compatible = "mediatek,mt6779-vdecsys", "syscon"; 265 reg = <0 0x16000000 0 0x1000>; 266 #clock-cells = <1>; 267 }; 268 269 vencsys: clock-controller@17000000 { 270 compatible = "mediatek,mt6779-vencsys", "syscon"; 271 reg = <0 0x17000000 0 0x1000>; 272 #clock-cells = <1>; 273 }; 274 275 camsys: clock-controller@1a000000 { 276 compatible = "mediatek,mt6779-camsys", "syscon"; 277 reg = <0 0x1a000000 0 0x10000>; 278 #clock-cells = <1>; 279 }; 280 281 ipesys: clock-controller@1b000000 { 282 compatible = "mediatek,mt6779-ipesys", "syscon"; 283 reg = <0 0x1b000000 0 0x1000>; 284 #clock-cells = <1>; 285 }; 286 287 }; 288}; 289