1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada CP11x. 6 */ 7 8#include <dt-bindings/interrupt-controller/mvebu-icu.h> 9#include <dt-bindings/thermal/thermal.h> 10 11#include "armada-common.dtsi" 12 13#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) 14 15/ { 16 /* 17 * The contents of the node are defined below, in order to 18 * save one indentation level 19 */ 20 CP11X_NAME: CP11X_NAME { }; 21 22 /* 23 * CPs only have one sensor in the thermal IC. 24 * 25 * The cooling maps are empty as there are no cooling devices. 26 */ 27 thermal-zones { 28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { 29 polling-delay-passive = <0>; /* Interrupt driven */ 30 polling-delay = <0>; /* Interrupt driven */ 31 32 thermal-sensors = <&CP11X_LABEL(thermal) 0>; 33 34 trips { 35 CP11X_LABEL(crit): crit { 36 temperature = <100000>; /* mC degrees */ 37 hysteresis = <2000>; /* mC degrees */ 38 type = "critical"; 39 }; 40 }; 41 42 cooling-maps { }; 43 }; 44 }; 45}; 46 47&CP11X_NAME { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 compatible = "simple-bus"; 51 interrupt-parent = <&CP11X_LABEL(icu_nsr)>; 52 ranges; 53 54 config-space@CP11X_BASE { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 compatible = "simple-bus"; 58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; 59 60 CP11X_LABEL(ethernet): ethernet@0 { 61 compatible = "marvell,armada-7k-pp22"; 62 reg = <0x0 0x100000>, <0x129000 0xb000>; 63 clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, 64 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, 65 <&CP11X_LABEL(clk) 1 18>; 66 clock-names = "pp_clk", "gop_clk", 67 "mg_clk", "mg_core_clk", "axi_clk"; 68 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 69 status = "disabled"; 70 dma-coherent; 71 72 CP11X_LABEL(eth0): eth0 { 73 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, 74 <43 IRQ_TYPE_LEVEL_HIGH>, 75 <47 IRQ_TYPE_LEVEL_HIGH>, 76 <51 IRQ_TYPE_LEVEL_HIGH>, 77 <55 IRQ_TYPE_LEVEL_HIGH>, 78 <59 IRQ_TYPE_LEVEL_HIGH>, 79 <63 IRQ_TYPE_LEVEL_HIGH>, 80 <67 IRQ_TYPE_LEVEL_HIGH>, 81 <71 IRQ_TYPE_LEVEL_HIGH>, 82 <129 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-names = "hif0", "hif1", "hif2", 84 "hif3", "hif4", "hif5", "hif6", "hif7", 85 "hif8", "link"; 86 port-id = <0>; 87 gop-port-id = <0>; 88 status = "disabled"; 89 }; 90 91 CP11X_LABEL(eth1): eth1 { 92 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>, 93 <44 IRQ_TYPE_LEVEL_HIGH>, 94 <48 IRQ_TYPE_LEVEL_HIGH>, 95 <52 IRQ_TYPE_LEVEL_HIGH>, 96 <56 IRQ_TYPE_LEVEL_HIGH>, 97 <60 IRQ_TYPE_LEVEL_HIGH>, 98 <64 IRQ_TYPE_LEVEL_HIGH>, 99 <68 IRQ_TYPE_LEVEL_HIGH>, 100 <72 IRQ_TYPE_LEVEL_HIGH>, 101 <128 IRQ_TYPE_LEVEL_HIGH>; 102 interrupt-names = "hif0", "hif1", "hif2", 103 "hif3", "hif4", "hif5", "hif6", "hif7", 104 "hif8", "link"; 105 port-id = <1>; 106 gop-port-id = <2>; 107 status = "disabled"; 108 }; 109 110 CP11X_LABEL(eth2): eth2 { 111 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>, 112 <45 IRQ_TYPE_LEVEL_HIGH>, 113 <49 IRQ_TYPE_LEVEL_HIGH>, 114 <53 IRQ_TYPE_LEVEL_HIGH>, 115 <57 IRQ_TYPE_LEVEL_HIGH>, 116 <61 IRQ_TYPE_LEVEL_HIGH>, 117 <65 IRQ_TYPE_LEVEL_HIGH>, 118 <69 IRQ_TYPE_LEVEL_HIGH>, 119 <73 IRQ_TYPE_LEVEL_HIGH>, 120 <127 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-names = "hif0", "hif1", "hif2", 122 "hif3", "hif4", "hif5", "hif6", "hif7", 123 "hif8", "link"; 124 port-id = <2>; 125 gop-port-id = <3>; 126 status = "disabled"; 127 }; 128 }; 129 130 CP11X_LABEL(comphy): phy@120000 { 131 compatible = "marvell,comphy-cp110"; 132 reg = <0x120000 0x6000>; 133 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 134 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>, 135 <&CP11X_LABEL(clk) 1 18>; 136 clock-names = "mg_clk", "mg_core_clk", "axi_clk"; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 CP11X_LABEL(comphy0): phy@0 { 141 reg = <0>; 142 #phy-cells = <1>; 143 }; 144 145 CP11X_LABEL(comphy1): phy@1 { 146 reg = <1>; 147 #phy-cells = <1>; 148 }; 149 150 CP11X_LABEL(comphy2): phy@2 { 151 reg = <2>; 152 #phy-cells = <1>; 153 }; 154 155 CP11X_LABEL(comphy3): phy@3 { 156 reg = <3>; 157 #phy-cells = <1>; 158 }; 159 160 CP11X_LABEL(comphy4): phy@4 { 161 reg = <4>; 162 #phy-cells = <1>; 163 }; 164 165 CP11X_LABEL(comphy5): phy@5 { 166 reg = <5>; 167 #phy-cells = <1>; 168 }; 169 }; 170 171 CP11X_LABEL(mdio): mdio@12a200 { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 compatible = "marvell,orion-mdio"; 175 reg = <0x12a200 0x10>; 176 clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>, 177 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; 178 status = "disabled"; 179 }; 180 181 CP11X_LABEL(xmdio): mdio@12a600 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "marvell,xmdio"; 185 reg = <0x12a600 0x10>; 186 clocks = <&CP11X_LABEL(clk) 1 5>, 187 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>; 188 status = "disabled"; 189 }; 190 191 CP11X_LABEL(icu): interrupt-controller@1e0000 { 192 compatible = "marvell,cp110-icu"; 193 reg = <0x1e0000 0x440>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 197 CP11X_LABEL(icu_nsr): interrupt-controller@10 { 198 compatible = "marvell,cp110-icu-nsr"; 199 reg = <0x10 0x20>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 msi-parent = <&gicp>; 203 }; 204 205 CP11X_LABEL(icu_sei): interrupt-controller@50 { 206 compatible = "marvell,cp110-icu-sei"; 207 reg = <0x50 0x10>; 208 #interrupt-cells = <2>; 209 interrupt-controller; 210 msi-parent = <&sei>; 211 }; 212 }; 213 214 CP11X_LABEL(rtc): rtc@284000 { 215 compatible = "marvell,armada-8k-rtc"; 216 reg = <0x284000 0x20>, <0x284080 0x24>; 217 reg-names = "rtc", "rtc-soc"; 218 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>; 219 }; 220 221 CP11X_LABEL(syscon0): system-controller@440000 { 222 compatible = "syscon", "simple-mfd"; 223 reg = <0x440000 0x2000>; 224 225 CP11X_LABEL(clk): clock { 226 compatible = "marvell,cp110-clock"; 227 #clock-cells = <2>; 228 }; 229 230 CP11X_LABEL(gpio1): gpio@100 { 231 compatible = "marvell,armada-8k-gpio"; 232 offset = <0x100>; 233 ngpios = <32>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; 237 interrupt-controller; 238 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, 239 <85 IRQ_TYPE_LEVEL_HIGH>, 240 <84 IRQ_TYPE_LEVEL_HIGH>, 241 <83 IRQ_TYPE_LEVEL_HIGH>; 242 #interrupt-cells = <2>; 243 status = "disabled"; 244 }; 245 246 CP11X_LABEL(gpio2): gpio@140 { 247 compatible = "marvell,armada-8k-gpio"; 248 offset = <0x140>; 249 ngpios = <31>; 250 gpio-controller; 251 #gpio-cells = <2>; 252 gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; 253 interrupt-controller; 254 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, 255 <81 IRQ_TYPE_LEVEL_HIGH>, 256 <80 IRQ_TYPE_LEVEL_HIGH>, 257 <79 IRQ_TYPE_LEVEL_HIGH>; 258 #interrupt-cells = <2>; 259 status = "disabled"; 260 }; 261 }; 262 263 CP11X_LABEL(syscon1): system-controller@400000 { 264 compatible = "syscon", "simple-mfd"; 265 reg = <0x400000 0x1000>; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 269 CP11X_LABEL(thermal): thermal-sensor@70 { 270 compatible = "marvell,armada-cp110-thermal"; 271 reg = <0x70 0x10>; 272 interrupts-extended = 273 <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; 274 #thermal-sensor-cells = <1>; 275 }; 276 }; 277 278 CP11X_LABEL(usb3_0): usb3@500000 { 279 compatible = "marvell,armada-8k-xhci", 280 "generic-xhci"; 281 reg = <0x500000 0x4000>; 282 dma-coherent; 283 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>; 284 clock-names = "core", "reg"; 285 clocks = <&CP11X_LABEL(clk) 1 22>, 286 <&CP11X_LABEL(clk) 1 16>; 287 status = "disabled"; 288 }; 289 290 CP11X_LABEL(usb3_1): usb3@510000 { 291 compatible = "marvell,armada-8k-xhci", 292 "generic-xhci"; 293 reg = <0x510000 0x4000>; 294 dma-coherent; 295 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>; 296 clock-names = "core", "reg"; 297 clocks = <&CP11X_LABEL(clk) 1 23>, 298 <&CP11X_LABEL(clk) 1 16>; 299 status = "disabled"; 300 }; 301 302 CP11X_LABEL(sata0): sata@540000 { 303 compatible = "marvell,armada-8k-ahci", 304 "generic-ahci"; 305 reg = <0x540000 0x30000>; 306 dma-coherent; 307 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&CP11X_LABEL(clk) 1 15>, 309 <&CP11X_LABEL(clk) 1 16>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 314 sata-port@0 { 315 reg = <0>; 316 }; 317 318 sata-port@1 { 319 reg = <1>; 320 }; 321 }; 322 323 CP11X_LABEL(xor0): xor@6a0000 { 324 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 325 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; 326 dma-coherent; 327 msi-parent = <&gic_v2m0>; 328 clock-names = "core", "reg"; 329 clocks = <&CP11X_LABEL(clk) 1 8>, 330 <&CP11X_LABEL(clk) 1 14>; 331 }; 332 333 CP11X_LABEL(xor1): xor@6c0000 { 334 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 335 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; 336 dma-coherent; 337 msi-parent = <&gic_v2m0>; 338 clock-names = "core", "reg"; 339 clocks = <&CP11X_LABEL(clk) 1 7>, 340 <&CP11X_LABEL(clk) 1 14>; 341 }; 342 343 CP11X_LABEL(spi0): spi@700600 { 344 compatible = "marvell,armada-380-spi"; 345 reg = <0x700600 0x50>; 346 #address-cells = <0x1>; 347 #size-cells = <0x0>; 348 clock-names = "core", "axi"; 349 clocks = <&CP11X_LABEL(clk) 1 21>, 350 <&CP11X_LABEL(clk) 1 17>; 351 status = "disabled"; 352 }; 353 354 CP11X_LABEL(spi1): spi@700680 { 355 compatible = "marvell,armada-380-spi"; 356 reg = <0x700680 0x50>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clock-names = "core", "axi"; 360 clocks = <&CP11X_LABEL(clk) 1 21>, 361 <&CP11X_LABEL(clk) 1 17>; 362 status = "disabled"; 363 }; 364 365 CP11X_LABEL(i2c0): i2c@701000 { 366 compatible = "marvell,mv78230-i2c"; 367 reg = <0x701000 0x20>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>; 371 clock-names = "core", "reg"; 372 clocks = <&CP11X_LABEL(clk) 1 21>, 373 <&CP11X_LABEL(clk) 1 17>; 374 status = "disabled"; 375 }; 376 377 CP11X_LABEL(i2c1): i2c@701100 { 378 compatible = "marvell,mv78230-i2c"; 379 reg = <0x701100 0x20>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>; 383 clock-names = "core", "reg"; 384 clocks = <&CP11X_LABEL(clk) 1 21>, 385 <&CP11X_LABEL(clk) 1 17>; 386 status = "disabled"; 387 }; 388 389 CP11X_LABEL(uart0): serial@702000 { 390 compatible = "snps,dw-apb-uart"; 391 reg = <0x702000 0x100>; 392 reg-shift = <2>; 393 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>; 394 reg-io-width = <1>; 395 clock-names = "baudclk", "apb_pclk"; 396 clocks = <&CP11X_LABEL(clk) 1 21>, 397 <&CP11X_LABEL(clk) 1 17>; 398 status = "disabled"; 399 }; 400 401 CP11X_LABEL(uart1): serial@702100 { 402 compatible = "snps,dw-apb-uart"; 403 reg = <0x702100 0x100>; 404 reg-shift = <2>; 405 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; 406 reg-io-width = <1>; 407 clock-names = "baudclk", "apb_pclk"; 408 clocks = <&CP11X_LABEL(clk) 1 21>, 409 <&CP11X_LABEL(clk) 1 17>; 410 status = "disabled"; 411 }; 412 413 CP11X_LABEL(uart2): serial@702200 { 414 compatible = "snps,dw-apb-uart"; 415 reg = <0x702200 0x100>; 416 reg-shift = <2>; 417 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>; 418 reg-io-width = <1>; 419 clock-names = "baudclk", "apb_pclk"; 420 clocks = <&CP11X_LABEL(clk) 1 21>, 421 <&CP11X_LABEL(clk) 1 17>; 422 status = "disabled"; 423 }; 424 425 CP11X_LABEL(uart3): serial@702300 { 426 compatible = "snps,dw-apb-uart"; 427 reg = <0x702300 0x100>; 428 reg-shift = <2>; 429 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; 430 reg-io-width = <1>; 431 clock-names = "baudclk", "apb_pclk"; 432 clocks = <&CP11X_LABEL(clk) 1 21>, 433 <&CP11X_LABEL(clk) 1 17>; 434 status = "disabled"; 435 }; 436 437 CP11X_LABEL(nand_controller): nand@720000 { 438 /* 439 * Due to the limitation of the pins available 440 * this controller is only usable on the CPM 441 * for A7K and on the CPS for A8K. 442 */ 443 compatible = "marvell,armada-8k-nand-controller", 444 "marvell,armada370-nand-controller"; 445 reg = <0x720000 0x54>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; 449 clock-names = "core", "reg"; 450 clocks = <&CP11X_LABEL(clk) 1 2>, 451 <&CP11X_LABEL(clk) 1 17>; 452 marvell,system-controller = <&CP11X_LABEL(syscon0)>; 453 status = "disabled"; 454 }; 455 456 CP11X_LABEL(trng): trng@760000 { 457 compatible = "marvell,armada-8k-rng", 458 "inside-secure,safexcel-eip76"; 459 reg = <0x760000 0x7d>; 460 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; 461 clock-names = "core", "reg"; 462 clocks = <&CP11X_LABEL(clk) 1 25>, 463 <&CP11X_LABEL(clk) 1 17>; 464 status = "okay"; 465 }; 466 467 CP11X_LABEL(sdhci0): sdhci@780000 { 468 compatible = "marvell,armada-cp110-sdhci"; 469 reg = <0x780000 0x300>; 470 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 471 clock-names = "core", "axi"; 472 clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>; 473 dma-coherent; 474 status = "disabled"; 475 }; 476 477 CP11X_LABEL(crypto): crypto@800000 { 478 compatible = "inside-secure,safexcel-eip197b"; 479 reg = <0x800000 0x200000>; 480 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>, 481 <88 IRQ_TYPE_LEVEL_HIGH>, 482 <89 IRQ_TYPE_LEVEL_HIGH>, 483 <90 IRQ_TYPE_LEVEL_HIGH>, 484 <91 IRQ_TYPE_LEVEL_HIGH>, 485 <92 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "mem", "ring0", "ring1", 487 "ring2", "ring3", "eip"; 488 clock-names = "core", "reg"; 489 clocks = <&CP11X_LABEL(clk) 1 26>, 490 <&CP11X_LABEL(clk) 1 17>; 491 dma-coherent; 492 }; 493 }; 494 495 CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { 496 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 497 reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>, 498 <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>; 499 reg-names = "ctrl", "config"; 500 #address-cells = <3>; 501 #size-cells = <2>; 502 #interrupt-cells = <1>; 503 device_type = "pci"; 504 dma-coherent; 505 msi-parent = <&gic_v2m0>; 506 507 bus-range = <0 0xff>; 508 /* non-prefetchable memory */ 509 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>; 510 interrupt-map-mask = <0 0 0 0>; 511 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>; 512 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 513 num-lanes = <1>; 514 clock-names = "core", "reg"; 515 clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; 516 status = "disabled"; 517 }; 518 519 CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { 520 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 521 reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>, 522 <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>; 523 reg-names = "ctrl", "config"; 524 #address-cells = <3>; 525 #size-cells = <2>; 526 #interrupt-cells = <1>; 527 device_type = "pci"; 528 dma-coherent; 529 msi-parent = <&gic_v2m0>; 530 531 bus-range = <0 0xff>; 532 /* non-prefetchable memory */ 533 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>; 534 interrupt-map-mask = <0 0 0 0>; 535 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>; 536 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 537 538 num-lanes = <1>; 539 clock-names = "core", "reg"; 540 clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; 541 status = "disabled"; 542 }; 543 544 CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { 545 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 546 reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>, 547 <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>; 548 reg-names = "ctrl", "config"; 549 #address-cells = <3>; 550 #size-cells = <2>; 551 #interrupt-cells = <1>; 552 device_type = "pci"; 553 dma-coherent; 554 msi-parent = <&gic_v2m0>; 555 556 bus-range = <0 0xff>; 557 /* non-prefetchable memory */ 558 ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>; 559 interrupt-map-mask = <0 0 0 0>; 560 interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>; 561 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 562 563 num-lanes = <1>; 564 clock-names = "core", "reg"; 565 clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; 566 status = "disabled"; 567 }; 568}; 569