xref: /freebsd/sys/contrib/device-tree/src/arm64/marvell/armada-ap80x.dtsi (revision 6be3386466ab79a84b48429ae66244f21526d3df) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP80x.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/thermal/thermal.h>
10
11/dts-v1/;
12
13/ {
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	aliases {
18		serial0 = &uart0;
19		serial1 = &uart1;
20		gpio0 = &ap_gpio;
21		spi0 = &spi0;
22	};
23
24	psci {
25		compatible = "arm,psci-0.2";
26		method = "smc";
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		/*
35		 * This area matches the mapping done with a
36		 * mainline U-Boot, and should be updated by the
37		 * bootloader.
38		 */
39
40		psci-area@4000000 {
41			reg = <0x0 0x4000000 0x0 0x200000>;
42			no-map;
43		};
44	};
45
46	AP_NAME {
47		#address-cells = <2>;
48		#size-cells = <2>;
49		compatible = "simple-bus";
50		interrupt-parent = <&gic>;
51		ranges;
52
53		config-space@f0000000 {
54			#address-cells = <1>;
55			#size-cells = <1>;
56			compatible = "simple-bus";
57			ranges = <0x0 0x0 0xf0000000 0x1000000>;
58
59			smmu: iommu@5000000 {
60				compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
61				reg = <0x100000 0x100000>;
62				dma-coherent;
63				#iommu-cells = <1>;
64				#global-interrupts = <1>;
65				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
66					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
67					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
68					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
69					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
70					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
72					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
73					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
74				status = "disabled";
75			};
76
77			gic: interrupt-controller@210000 {
78				compatible = "arm,gic-400";
79				#interrupt-cells = <3>;
80				#address-cells = <1>;
81				#size-cells = <1>;
82				ranges;
83				interrupt-controller;
84				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
85				reg = <0x210000 0x10000>,
86				      <0x220000 0x20000>,
87				      <0x240000 0x20000>,
88				      <0x260000 0x20000>;
89
90				gic_v2m0: v2m@280000 {
91					compatible = "arm,gic-v2m-frame";
92					msi-controller;
93					reg = <0x280000 0x1000>;
94					arm,msi-base-spi = <160>;
95					arm,msi-num-spis = <32>;
96				};
97				gic_v2m1: v2m@290000 {
98					compatible = "arm,gic-v2m-frame";
99					msi-controller;
100					reg = <0x290000 0x1000>;
101					arm,msi-base-spi = <192>;
102					arm,msi-num-spis = <32>;
103				};
104				gic_v2m2: v2m@2a0000 {
105					compatible = "arm,gic-v2m-frame";
106					msi-controller;
107					reg = <0x2a0000 0x1000>;
108					arm,msi-base-spi = <224>;
109					arm,msi-num-spis = <32>;
110				};
111				gic_v2m3: v2m@2b0000 {
112					compatible = "arm,gic-v2m-frame";
113					msi-controller;
114					reg = <0x2b0000 0x1000>;
115					arm,msi-base-spi = <256>;
116					arm,msi-num-spis = <32>;
117				};
118			};
119
120			timer {
121				compatible = "arm,armv8-timer";
122				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
123					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
124					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
126			};
127
128			pmu {
129				compatible = "arm,cortex-a72-pmu";
130				interrupt-parent = <&pic>;
131				interrupts = <17>;
132			};
133
134			odmi: odmi@300000 {
135				compatible = "marvell,odmi-controller";
136				interrupt-controller;
137				msi-controller;
138				marvell,odmi-frames = <4>;
139				reg = <0x300000 0x4000>,
140				      <0x304000 0x4000>,
141				      <0x308000 0x4000>,
142				      <0x30C000 0x4000>;
143				marvell,spi-base = <128>, <136>, <144>, <152>;
144			};
145
146			gicp: gicp@3f0040 {
147				compatible = "marvell,ap806-gicp";
148				reg = <0x3f0040 0x10>;
149				marvell,spi-ranges = <64 64>, <288 64>;
150				msi-controller;
151			};
152
153			pic: interrupt-controller@3f0100 {
154				compatible = "marvell,armada-8k-pic";
155				reg = <0x3f0100 0x10>;
156				#interrupt-cells = <1>;
157				interrupt-controller;
158				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
159			};
160
161			sei: interrupt-controller@3f0200 {
162				compatible = "marvell,ap806-sei";
163				reg = <0x3f0200 0x40>;
164				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
165				#interrupt-cells = <1>;
166				interrupt-controller;
167				msi-controller;
168			};
169
170			xor@400000 {
171				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
172				reg = <0x400000 0x1000>,
173				      <0x410000 0x1000>;
174				msi-parent = <&gic_v2m0>;
175				clocks = <&ap_clk 3>;
176				dma-coherent;
177			};
178
179			xor@420000 {
180				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
181				reg = <0x420000 0x1000>,
182				      <0x430000 0x1000>;
183				msi-parent = <&gic_v2m0>;
184				clocks = <&ap_clk 3>;
185				dma-coherent;
186			};
187
188			xor@440000 {
189				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
190				reg = <0x440000 0x1000>,
191				      <0x450000 0x1000>;
192				msi-parent = <&gic_v2m0>;
193				clocks = <&ap_clk 3>;
194				dma-coherent;
195			};
196
197			xor@460000 {
198				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
199				reg = <0x460000 0x1000>,
200				      <0x470000 0x1000>;
201				msi-parent = <&gic_v2m0>;
202				clocks = <&ap_clk 3>;
203				dma-coherent;
204			};
205
206			spi0: spi@510600 {
207				compatible = "marvell,armada-380-spi";
208				reg = <0x510600 0x50>;
209				#address-cells = <1>;
210				#size-cells = <0>;
211				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
212				clocks = <&ap_clk 3>;
213				status = "disabled";
214			};
215
216			i2c0: i2c@511000 {
217				compatible = "marvell,mv78230-i2c";
218				reg = <0x511000 0x20>;
219				#address-cells = <1>;
220				#size-cells = <0>;
221				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
222				clocks = <&ap_clk 3>;
223				status = "disabled";
224			};
225
226			uart0: serial@512000 {
227				compatible = "snps,dw-apb-uart";
228				reg = <0x512000 0x100>;
229				reg-shift = <2>;
230				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
231				reg-io-width = <1>;
232				clocks = <&ap_clk 3>;
233				status = "disabled";
234			};
235
236			uart1: serial@512100 {
237				compatible = "snps,dw-apb-uart";
238				reg = <0x512100 0x100>;
239				reg-shift = <2>;
240				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
241				reg-io-width = <1>;
242				clocks = <&ap_clk 3>;
243				status = "disabled";
244
245			};
246
247			watchdog: watchdog@610000 {
248				compatible = "arm,sbsa-gwdt";
249				reg = <0x610000 0x1000>, <0x600000 0x1000>;
250				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
251			};
252
253			ap_sdhci0: sdhci@6e0000 {
254				compatible = "marvell,armada-ap806-sdhci";
255				reg = <0x6e0000 0x300>;
256				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
257				clock-names = "core";
258				clocks = <&ap_clk 4>;
259				dma-coherent;
260				marvell,xenon-phy-slow-mode;
261				status = "disabled";
262			};
263
264			ap_syscon0: system-controller@6f4000 {
265				compatible = "syscon", "simple-mfd";
266				reg = <0x6f4000 0x2000>;
267
268				ap_pinctrl: pinctrl {
269					compatible = "marvell,ap806-pinctrl";
270
271					uart0_pins: uart0-pins {
272						marvell,pins = "mpp11", "mpp19";
273						marvell,function = "uart0";
274					};
275				};
276
277				ap_gpio: gpio@1040 {
278					compatible = "marvell,armada-8k-gpio";
279					offset = <0x1040>;
280					ngpios = <20>;
281					gpio-controller;
282					#gpio-cells = <2>;
283					gpio-ranges = <&ap_pinctrl 0 0 20>;
284				};
285			};
286
287			ap_syscon1: system-controller@6f8000 {
288				compatible = "syscon", "simple-mfd";
289				reg = <0x6f8000 0x1000>;
290				#address-cells = <1>;
291				#size-cells = <1>;
292
293				ap_thermal: thermal-sensor@80 {
294					compatible = "marvell,armada-ap806-thermal";
295					reg = <0x80 0x10>;
296					interrupt-parent = <&sei>;
297					interrupts = <18>;
298					#thermal-sensor-cells = <1>;
299				};
300			};
301		};
302	};
303
304	/*
305	 * The thermal IP features one internal sensor plus, if applicable, one
306	 * remote channel wired to one sensor per CPU.
307	 *
308	 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
309	 * first one that will have a critical trip point will be chosen.
310	 */
311	thermal-zones {
312		ap_thermal_ic: ap-thermal-ic {
313			polling-delay-passive = <0>; /* Interrupt driven */
314			polling-delay = <0>; /* Interrupt driven */
315
316			thermal-sensors = <&ap_thermal 0>;
317
318			trips {
319				ap_crit: ap-crit {
320					temperature = <100000>; /* mC degrees */
321					hysteresis = <2000>; /* mC degrees */
322					type = "critical";
323				};
324			};
325
326			cooling-maps { };
327		};
328
329		ap_thermal_cpu0: ap-thermal-cpu0 {
330			polling-delay-passive = <1000>;
331			polling-delay = <1000>;
332
333			thermal-sensors = <&ap_thermal 1>;
334
335			trips {
336				cpu0_hot: cpu0-hot {
337					temperature = <85000>;
338					hysteresis = <2000>;
339					type = "passive";
340				};
341				cpu0_emerg: cpu0-emerg {
342					temperature = <95000>;
343					hysteresis = <2000>;
344					type = "passive";
345				};
346			};
347
348			cooling-maps {
349				map0_hot: map0-hot {
350					trip = <&cpu0_hot>;
351					cooling-device = <&cpu0 1 2>,
352						<&cpu1 1 2>;
353				};
354				map0_emerg: map0-ermerg {
355					trip = <&cpu0_emerg>;
356					cooling-device = <&cpu0 3 3>,
357						<&cpu1 3 3>;
358				};
359			};
360		};
361
362		ap_thermal_cpu1: ap-thermal-cpu1 {
363			polling-delay-passive = <1000>;
364			polling-delay = <1000>;
365
366			thermal-sensors = <&ap_thermal 2>;
367
368			trips {
369				cpu1_hot: cpu1-hot {
370					temperature = <85000>;
371					hysteresis = <2000>;
372					type = "passive";
373				};
374				cpu1_emerg: cpu1-emerg {
375					temperature = <95000>;
376					hysteresis = <2000>;
377					type = "passive";
378				};
379			};
380
381			cooling-maps {
382				map1_hot: map1-hot {
383					trip = <&cpu1_hot>;
384					cooling-device = <&cpu0 1 2>,
385						<&cpu1 1 2>;
386				};
387				map1_emerg: map1-emerg {
388					trip = <&cpu1_emerg>;
389					cooling-device = <&cpu0 3 3>,
390						<&cpu1 3 3>;
391				};
392			};
393		};
394
395		ap_thermal_cpu2: ap-thermal-cpu2 {
396			polling-delay-passive = <1000>;
397			polling-delay = <1000>;
398
399			thermal-sensors = <&ap_thermal 3>;
400
401			trips {
402				cpu2_hot: cpu2-hot {
403					temperature = <85000>;
404					hysteresis = <2000>;
405					type = "passive";
406				};
407				cpu2_emerg: cpu2-emerg {
408					temperature = <95000>;
409					hysteresis = <2000>;
410					type = "passive";
411				};
412			};
413
414			cooling-maps {
415				map2_hot: map2-hot {
416					trip = <&cpu2_hot>;
417					cooling-device = <&cpu2 1 2>,
418						<&cpu3 1 2>;
419				};
420				map2_emerg: map2-emerg {
421					trip = <&cpu2_emerg>;
422					cooling-device = <&cpu2 3 3>,
423						<&cpu3 3 3>;
424				};
425			};
426		};
427
428		ap_thermal_cpu3: ap-thermal-cpu3 {
429			polling-delay-passive = <1000>;
430			polling-delay = <1000>;
431
432			thermal-sensors = <&ap_thermal 4>;
433
434			trips {
435				cpu3_hot: cpu3-hot {
436					temperature = <85000>;
437					hysteresis = <2000>;
438					type = "passive";
439				};
440				cpu3_emerg: cpu3-emerg {
441					temperature = <95000>;
442					hysteresis = <2000>;
443					type = "passive";
444				};
445			};
446
447			cooling-maps {
448				map3_hot: map3-bhot {
449					trip = <&cpu3_hot>;
450					cooling-device = <&cpu2 1 2>,
451						<&cpu3 1 2>;
452				};
453				map3_emerg: map3-emerg {
454					trip = <&cpu3_emerg>;
455					cooling-device = <&cpu2 3 3>,
456						<&cpu3 3 3>;
457				};
458			};
459		};
460	};
461};
462