1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for MACCHIATOBin Armada 8040 community board platform 6 */ 7 8#include "armada-8040.dtsi" 9 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 model = "Marvell 8040 MACCHIATOBin"; 14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040", 15 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@0 { 22 device_type = "memory"; 23 reg = <0x0 0x0 0x0 0x80000000>; 24 }; 25 26 aliases { 27 ethernet0 = &cp0_eth0; 28 ethernet1 = &cp1_eth0; 29 ethernet2 = &cp1_eth1; 30 ethernet3 = &cp1_eth2; 31 }; 32 33 /* Regulator labels correspond with schematics */ 34 v_3_3: regulator-3-3v { 35 compatible = "regulator-fixed"; 36 regulator-name = "v_3_3"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 regulator-always-on; 40 status = "okay"; 41 }; 42 43 v_vddo_h: regulator-1-8v { 44 compatible = "regulator-fixed"; 45 regulator-name = "v_vddo_h"; 46 regulator-min-microvolt = <1800000>; 47 regulator-max-microvolt = <1800000>; 48 regulator-always-on; 49 status = "okay"; 50 }; 51 52 v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { 53 compatible = "regulator-fixed"; 54 enable-active-high; 55 gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&cp0_xhci_vbus_pins>; 58 regulator-name = "v_5v0_usb3_hst_vbus"; 59 regulator-min-microvolt = <5000000>; 60 regulator-max-microvolt = <5000000>; 61 status = "okay"; 62 }; 63 64 sfp_eth0: sfp-eth0 { 65 /* CON15,16 - CPM lane 4 */ 66 compatible = "sff,sfp"; 67 i2c-bus = <&sfpp0_i2c>; 68 los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; 69 mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; 70 tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; 71 tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&cp1_sfpp0_pins>; 74 maximum-power-milliwatt = <2000>; 75 }; 76 77 sfp_eth1: sfp-eth1 { 78 /* CON17,18 - CPS lane 4 */ 79 compatible = "sff,sfp"; 80 i2c-bus = <&sfpp1_i2c>; 81 los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; 82 mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; 83 tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; 84 tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; 87 maximum-power-milliwatt = <2000>; 88 }; 89 90 sfp_eth3: sfp-eth3 { 91 /* CON13,14 - CPS lane 5 */ 92 compatible = "sff,sfp"; 93 i2c-bus = <&sfp_1g_i2c>; 94 los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; 95 mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; 96 tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; 97 tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; 100 maximum-power-milliwatt = <2000>; 101 }; 102}; 103 104&uart0 { 105 status = "okay"; 106 pinctrl-0 = <&uart0_pins>; 107 pinctrl-names = "default"; 108}; 109 110&ap_sdhci0 { 111 bus-width = <8>; 112 /* 113 * Not stable in HS modes - phy needs "more calibration", so add 114 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. 115 */ 116 marvell,xenon-phy-slow-mode; 117 no-1-8-v; 118 no-sd; 119 no-sdio; 120 non-removable; 121 status = "okay"; 122 vqmmc-supply = <&v_vddo_h>; 123}; 124 125&cp0_i2c0 { 126 clock-frequency = <100000>; 127 pinctrl-names = "default"; 128 pinctrl-0 = <&cp0_i2c0_pins>; 129 status = "okay"; 130}; 131 132&cp0_i2c1 { 133 clock-frequency = <100000>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&cp0_i2c1_pins>; 136 status = "okay"; 137 138 i2c-switch@70 { 139 compatible = "nxp,pca9548"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 reg = <0x70>; 143 144 sfpp0_i2c: i2c@0 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 reg = <0>; 148 }; 149 sfpp1_i2c: i2c@1 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 reg = <1>; 153 }; 154 sfp_1g_i2c: i2c@2 { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 reg = <2>; 158 }; 159 }; 160}; 161 162/* J25 UART header */ 163&cp0_uart1 { 164 pinctrl-names = "default"; 165 pinctrl-0 = <&cp0_uart1_pins>; 166 status = "okay"; 167}; 168 169&cp0_mdio { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&cp0_ge_mdio_pins>; 172 status = "okay"; 173 174 ge_phy: ethernet-phy@0 { 175 reg = <0>; 176 }; 177}; 178 179&cp0_pcie0 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&cp0_pcie_pins>; 182 num-lanes = <4>; 183 num-viewport = <8>; 184 reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; 185 ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; 186 phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, 187 <&cp0_comphy2 0>, <&cp0_comphy3 0>; 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy", 189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy"; 190 status = "okay"; 191}; 192 193&cp0_pinctrl { 194 cp0_ge_mdio_pins: ge-mdio-pins { 195 marvell,pins = "mpp32", "mpp34"; 196 marvell,function = "ge"; 197 }; 198 cp0_i2c1_pins: i2c1-pins { 199 marvell,pins = "mpp35", "mpp36"; 200 marvell,function = "i2c1"; 201 }; 202 cp0_i2c0_pins: i2c0-pins { 203 marvell,pins = "mpp37", "mpp38"; 204 marvell,function = "i2c0"; 205 }; 206 cp0_uart1_pins: uart1-pins { 207 marvell,pins = "mpp40", "mpp41"; 208 marvell,function = "uart1"; 209 }; 210 cp0_xhci_vbus_pins: xhci0-vbus-pins { 211 marvell,pins = "mpp47"; 212 marvell,function = "gpio"; 213 }; 214 cp0_sfp_1g_pins: sfp-1g-pins { 215 marvell,pins = "mpp51", "mpp53", "mpp54"; 216 marvell,function = "gpio"; 217 }; 218 cp0_pcie_pins: pcie-pins { 219 marvell,pins = "mpp52"; 220 marvell,function = "gpio"; 221 }; 222 cp0_sdhci_pins: sdhci-pins { 223 marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", 224 "mpp60", "mpp61"; 225 marvell,function = "sdio"; 226 }; 227 cp0_sfpp1_pins: sfpp1-pins { 228 marvell,pins = "mpp62"; 229 marvell,function = "gpio"; 230 }; 231}; 232 233&cp0_ethernet { 234 status = "okay"; 235}; 236 237&cp0_eth0 { 238 /* Generic PHY, providing serdes lanes */ 239 phys = <&cp0_comphy4 0>; 240}; 241 242&cp0_sata0 { 243 status = "okay"; 244 245 /* CPM Lane 5 - U29 */ 246 sata-port@1 { 247 phys = <&cp0_comphy5 1>; 248 phy-names = "cp0-sata0-1-phy"; 249 }; 250}; 251 252&cp0_sdhci0 { 253 /* U6 */ 254 broken-cd; 255 bus-width = <4>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&cp0_sdhci_pins>; 258 status = "okay"; 259 vqmmc-supply = <&v_3_3>; 260}; 261 262&cp0_utmi { 263 status = "okay"; 264}; 265 266&cp0_usb3_0 { 267 /* J38? - USB2.0 only */ 268 phys = <&cp0_utmi0>; 269 phy-names = "utmi"; 270 dr_mode = "host"; 271 status = "okay"; 272}; 273 274&cp0_usb3_1 { 275 /* J38? - USB2.0 only */ 276 phys = <&cp0_utmi1>; 277 phy-names = "utmi"; 278 dr_mode = "host"; 279 status = "okay"; 280}; 281 282&cp1_ethernet { 283 status = "okay"; 284}; 285 286&cp1_eth0 { 287 /* Generic PHY, providing serdes lanes */ 288 phys = <&cp1_comphy4 0>; 289}; 290 291&cp1_eth1 { 292 /* CPS Lane 0 - J5 (Gigabit RJ45) */ 293 status = "okay"; 294 /* Network PHY */ 295 phy = <&ge_phy>; 296 phy-mode = "sgmii"; 297 /* Generic PHY, providing serdes lanes */ 298 phys = <&cp1_comphy0 1>; 299}; 300 301&cp1_eth2 { 302 /* CPS Lane 5 */ 303 status = "okay"; 304 /* Network PHY */ 305 phy-mode = "2500base-x"; 306 managed = "in-band-status"; 307 /* Generic PHY, providing serdes lanes */ 308 phys = <&cp1_comphy5 2>; 309 sfp = <&sfp_eth3>; 310}; 311 312&cp1_pinctrl { 313 cp1_sfpp1_pins: sfpp1-pins { 314 marvell,pins = "mpp8", "mpp10", "mpp11"; 315 marvell,function = "gpio"; 316 }; 317 cp1_spi1_pins: spi1-pins { 318 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; 319 marvell,function = "spi1"; 320 }; 321 cp1_uart0_pins: uart0-pins { 322 marvell,pins = "mpp6", "mpp7"; 323 marvell,function = "uart0"; 324 }; 325 cp1_sfp_1g_pins: sfp-1g-pins { 326 marvell,pins = "mpp24"; 327 marvell,function = "gpio"; 328 }; 329 cp1_sfpp0_pins: sfpp0-pins { 330 marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; 331 marvell,function = "gpio"; 332 }; 333}; 334 335/* J27 UART header */ 336&cp1_uart0 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&cp1_uart0_pins>; 339 status = "okay"; 340}; 341 342&cp1_sata0 { 343 status = "okay"; 344 345 /* CPS Lane 1 - U32 */ 346 sata-port@0 { 347 phys = <&cp1_comphy1 0>; 348 phy-names = "cp1-sata0-0-phy"; 349 }; 350 351 /* CPS Lane 3 - U31 */ 352 sata-port@1 { 353 phys = <&cp1_comphy3 1>; 354 phy-names = "cp1-sata0-1-phy"; 355 }; 356}; 357 358&cp1_spi1 { 359 pinctrl-names = "default"; 360 pinctrl-0 = <&cp1_spi1_pins>; 361 status = "okay"; 362 363 flash@0 { 364 compatible = "st,w25q32"; 365 spi-max-frequency = <50000000>; 366 reg = <0>; 367 }; 368}; 369 370&cp1_comphy2 { 371 cp1_usbh0_con: connector { 372 compatible = "usb-a-connector"; 373 phy-supply = <&v_5v0_usb3_hst_vbus>; 374 }; 375}; 376 377&cp1_utmi { 378 status = "okay"; 379}; 380 381&cp1_usb3_0 { 382 /* CPS Lane 2 - CON7 */ 383 phys = <&cp1_comphy2 0>, <&cp1_utmi0>; 384 phy-names = "cp1-usb3h0-comphy", "utmi"; 385 dr_mode = "host"; 386 status = "okay"; 387}; 388