1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 4 * 5 * Copyright (C) 2016 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/ { 14 model = "Marvell Armada 37xx SoC"; 15 compatible = "marvell,armada3700"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 }; 24 25 reserved-memory { 26 #address-cells = <2>; 27 #size-cells = <2>; 28 ranges; 29 30 /* 31 * The PSCI firmware region depicted below is the default one 32 * and should be updated by the bootloader. 33 */ 34 psci-area@4000000 { 35 reg = <0 0x4000000 0 0x200000>; 36 no-map; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0>; 47 clocks = <&nb_periph_clk 16>; 48 enable-method = "psci"; 49 }; 50 }; 51 52 psci { 53 compatible = "arm,psci-0.2"; 54 method = "smc"; 55 }; 56 57 timer { 58 compatible = "arm,armv8-timer"; 59 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 63 }; 64 65 pmu { 66 compatible = "arm,armv8-pmuv3"; 67 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 68 }; 69 70 soc { 71 compatible = "simple-bus"; 72 #address-cells = <2>; 73 #size-cells = <2>; 74 ranges; 75 76 internal-regs@d0000000 { 77 #address-cells = <1>; 78 #size-cells = <1>; 79 compatible = "simple-bus"; 80 /* 32M internal register @ 0xd000_0000 */ 81 ranges = <0x0 0x0 0xd0000000 0x2000000>; 82 83 wdt: watchdog@8300 { 84 compatible = "marvell,armada-3700-wdt"; 85 reg = <0x8300 0x40>; 86 marvell,system-controller = <&cpu_misc>; 87 clocks = <&xtalclk>; 88 }; 89 90 cpu_misc: system-controller@d000 { 91 compatible = "marvell,armada-3700-cpu-misc", 92 "syscon"; 93 reg = <0xd000 0x1000>; 94 }; 95 96 spi0: spi@10600 { 97 compatible = "marvell,armada-3700-spi"; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 reg = <0x10600 0xA00>; 101 clocks = <&nb_periph_clk 7>; 102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 103 num-cs = <4>; 104 status = "disabled"; 105 }; 106 107 i2c0: i2c@11000 { 108 compatible = "marvell,armada-3700-i2c"; 109 reg = <0x11000 0x24>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clocks = <&nb_periph_clk 10>; 113 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 114 mrvl,i2c-fast-mode; 115 status = "disabled"; 116 }; 117 118 i2c1: i2c@11080 { 119 compatible = "marvell,armada-3700-i2c"; 120 reg = <0x11080 0x24>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 clocks = <&nb_periph_clk 9>; 124 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 125 mrvl,i2c-fast-mode; 126 status = "disabled"; 127 }; 128 129 avs: avs@11500 { 130 compatible = "marvell,armada-3700-avs", 131 "syscon"; 132 reg = <0x11500 0x40>; 133 }; 134 135 uart0: serial@12000 { 136 compatible = "marvell,armada-3700-uart"; 137 reg = <0x12000 0x200>; 138 clocks = <&xtalclk>; 139 interrupts = 140 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 143 interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 144 status = "disabled"; 145 }; 146 147 uart1: serial@12200 { 148 compatible = "marvell,armada-3700-uart-ext"; 149 reg = <0x12200 0x30>; 150 clocks = <&xtalclk>; 151 interrupts = 152 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 153 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 154 interrupt-names = "uart-tx", "uart-rx"; 155 status = "disabled"; 156 }; 157 158 nb_periph_clk: nb-periph-clk@13000 { 159 compatible = "marvell,armada-3700-periph-clock-nb"; 160 reg = <0x13000 0x100>; 161 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 162 <&tbg 3>, <&xtalclk>; 163 #clock-cells = <1>; 164 }; 165 166 sb_periph_clk: sb-periph-clk@18000 { 167 compatible = "marvell,armada-3700-periph-clock-sb"; 168 reg = <0x18000 0x100>; 169 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 170 <&tbg 3>, <&xtalclk>; 171 #clock-cells = <1>; 172 }; 173 174 tbg: tbg@13200 { 175 compatible = "marvell,armada-3700-tbg-clock"; 176 reg = <0x13200 0x100>; 177 clocks = <&xtalclk>; 178 #clock-cells = <1>; 179 }; 180 181 pinctrl_nb: pinctrl@13800 { 182 compatible = "marvell,armada3710-nb-pinctrl", 183 "syscon", "simple-mfd"; 184 reg = <0x13800 0x100>, <0x13C00 0x20>; 185 /* MPP1[19:0] */ 186 gpionb: gpio { 187 #gpio-cells = <2>; 188 gpio-ranges = <&pinctrl_nb 0 0 36>; 189 gpio-controller; 190 interrupt-controller; 191 #interrupt-cells = <2>; 192 interrupts = 193 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 205 }; 206 207 xtalclk: xtal-clk { 208 compatible = "marvell,armada-3700-xtal-clock"; 209 clock-output-names = "xtal"; 210 #clock-cells = <0>; 211 }; 212 213 spi_quad_pins: spi-quad-pins { 214 groups = "spi_quad"; 215 function = "spi"; 216 }; 217 218 spi_cs1_pins: spi-cs1-pins { 219 groups = "spi_cs1"; 220 function = "spi"; 221 }; 222 223 i2c1_pins: i2c1-pins { 224 groups = "i2c1"; 225 function = "i2c"; 226 }; 227 228 i2c2_pins: i2c2-pins { 229 groups = "i2c2"; 230 function = "i2c"; 231 }; 232 233 uart1_pins: uart1-pins { 234 groups = "uart1"; 235 function = "uart"; 236 }; 237 238 uart2_pins: uart2-pins { 239 groups = "uart2"; 240 function = "uart"; 241 }; 242 243 mmc_pins: mmc-pins { 244 groups = "emmc_nb"; 245 function = "emmc"; 246 }; 247 }; 248 249 nb_pm: syscon@14000 { 250 compatible = "marvell,armada-3700-nb-pm", 251 "syscon"; 252 reg = <0x14000 0x60>; 253 }; 254 255 comphy: phy@18300 { 256 compatible = "marvell,comphy-a3700"; 257 reg = <0x18300 0x300>, 258 <0x1F000 0x400>, 259 <0x5C000 0x400>, 260 <0xe0178 0x8>; 261 reg-names = "comphy", 262 "lane1_pcie_gbe", 263 "lane0_usb3_gbe", 264 "lane2_sata_usb3"; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 268 comphy0: phy@0 { 269 reg = <0>; 270 #phy-cells = <1>; 271 }; 272 273 comphy1: phy@1 { 274 reg = <1>; 275 #phy-cells = <1>; 276 }; 277 278 comphy2: phy@2 { 279 reg = <2>; 280 #phy-cells = <1>; 281 }; 282 }; 283 284 pinctrl_sb: pinctrl@18800 { 285 compatible = "marvell,armada3710-sb-pinctrl", 286 "syscon", "simple-mfd"; 287 reg = <0x18800 0x100>, <0x18C00 0x20>; 288 /* MPP2[23:0] */ 289 gpiosb: gpio { 290 #gpio-cells = <2>; 291 gpio-ranges = <&pinctrl_sb 0 0 30>; 292 gpio-controller; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 interrupts = 296 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 301 }; 302 303 rgmii_pins: mii-pins { 304 groups = "rgmii"; 305 function = "mii"; 306 }; 307 308 smi_pins: smi-pins { 309 groups = "smi"; 310 function = "smi"; 311 }; 312 313 sdio_pins: sdio-pins { 314 groups = "sdio_sb"; 315 function = "sdio"; 316 }; 317 318 pcie_reset_pins: pcie-reset-pins { 319 groups = "pcie1"; /* this actually controls "pcie1_reset" */ 320 function = "gpio"; 321 }; 322 323 pcie_clkreq_pins: pcie-clkreq-pins { 324 groups = "pcie1_clkreq"; 325 function = "pcie"; 326 }; 327 }; 328 329 eth0: ethernet@30000 { 330 compatible = "marvell,armada-3700-neta"; 331 reg = <0x30000 0x4000>; 332 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&sb_periph_clk 8>; 334 status = "disabled"; 335 }; 336 337 mdio: mdio@32004 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 compatible = "marvell,orion-mdio"; 341 reg = <0x32004 0x4>; 342 }; 343 344 eth1: ethernet@40000 { 345 compatible = "marvell,armada-3700-neta"; 346 reg = <0x40000 0x4000>; 347 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&sb_periph_clk 7>; 349 status = "disabled"; 350 }; 351 352 usb3: usb@58000 { 353 compatible = "marvell,armada3700-xhci", 354 "generic-xhci"; 355 reg = <0x58000 0x4000>; 356 marvell,usb-misc-reg = <&usb32_syscon>; 357 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&sb_periph_clk 12>; 359 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; 360 phy-names = "usb3-phy", "usb2-utmi-otg-phy"; 361 status = "disabled"; 362 }; 363 364 usb2_utmi_otg_phy: phy@5d000 { 365 compatible = "marvell,a3700-utmi-otg-phy"; 366 reg = <0x5d000 0x800>; 367 marvell,usb-misc-reg = <&usb32_syscon>; 368 #phy-cells = <0>; 369 }; 370 371 usb32_syscon: system-controller@5d800 { 372 compatible = "marvell,armada-3700-usb2-host-device-misc", 373 "syscon"; 374 reg = <0x5d800 0x800>; 375 }; 376 377 usb2: usb@5e000 { 378 compatible = "marvell,armada-3700-ehci"; 379 reg = <0x5e000 0x1000>; 380 marvell,usb-misc-reg = <&usb2_syscon>; 381 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 382 phys = <&usb2_utmi_host_phy>; 383 phy-names = "usb2-utmi-host-phy"; 384 status = "disabled"; 385 }; 386 387 usb2_utmi_host_phy: phy@5f000 { 388 compatible = "marvell,a3700-utmi-host-phy"; 389 reg = <0x5f000 0x800>; 390 marvell,usb-misc-reg = <&usb2_syscon>; 391 #phy-cells = <0>; 392 }; 393 394 usb2_syscon: system-controller@5f800 { 395 compatible = "marvell,armada-3700-usb2-host-misc", 396 "syscon"; 397 reg = <0x5f800 0x800>; 398 }; 399 400 xor@60900 { 401 compatible = "marvell,armada-3700-xor"; 402 reg = <0x60900 0x100>, 403 <0x60b00 0x100>; 404 405 xor10 { 406 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 407 }; 408 xor11 { 409 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 }; 412 413 crypto: crypto@90000 { 414 compatible = "inside-secure,safexcel-eip97ies"; 415 reg = <0x90000 0x20000>; 416 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-names = "mem", "ring0", "ring1", 423 "ring2", "ring3", "eip"; 424 clocks = <&nb_periph_clk 15>; 425 }; 426 427 rwtm: mailbox@b0000 { 428 compatible = "marvell,armada-3700-rwtm-mailbox"; 429 reg = <0xb0000 0x100>; 430 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 431 #mbox-cells = <1>; 432 }; 433 434 sdhci1: sdhci@d0000 { 435 compatible = "marvell,armada-3700-sdhci", 436 "marvell,sdhci-xenon"; 437 reg = <0xd0000 0x300>, 438 <0x1e808 0x4>; 439 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&nb_periph_clk 0>; 441 clock-names = "core"; 442 status = "disabled"; 443 }; 444 445 sdhci0: sdhci@d8000 { 446 compatible = "marvell,armada-3700-sdhci", 447 "marvell,sdhci-xenon"; 448 reg = <0xd8000 0x300>, 449 <0x17808 0x4>; 450 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&nb_periph_clk 0>; 452 clock-names = "core"; 453 status = "disabled"; 454 }; 455 456 sata: sata@e0000 { 457 compatible = "marvell,armada-3700-ahci"; 458 reg = <0xe0000 0x178>; 459 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&nb_periph_clk 1>; 461 status = "disabled"; 462 }; 463 464 gic: interrupt-controller@1d00000 { 465 compatible = "arm,gic-v3"; 466 #interrupt-cells = <3>; 467 interrupt-controller; 468 reg = <0x1d00000 0x10000>, /* GICD */ 469 <0x1d40000 0x40000>, /* GICR */ 470 <0x1d80000 0x2000>, /* GICC */ 471 <0x1d90000 0x2000>, /* GICH */ 472 <0x1da0000 0x20000>; /* GICV */ 473 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 474 }; 475 }; 476 477 pcie0: pcie@d0070000 { 478 compatible = "marvell,armada-3700-pcie"; 479 device_type = "pci"; 480 status = "disabled"; 481 reg = <0 0xd0070000 0 0x20000>; 482 #address-cells = <3>; 483 #size-cells = <2>; 484 bus-range = <0x00 0xff>; 485 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 486 #interrupt-cells = <1>; 487 msi-parent = <&pcie0>; 488 msi-controller; 489 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 490 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 491 interrupt-map-mask = <0 0 0 7>; 492 interrupt-map = <0 0 0 1 &pcie_intc 0>, 493 <0 0 0 2 &pcie_intc 1>, 494 <0 0 0 3 &pcie_intc 2>, 495 <0 0 0 4 &pcie_intc 3>; 496 max-link-speed = <2>; 497 phys = <&comphy1 0>; 498 pcie_intc: interrupt-controller { 499 interrupt-controller; 500 #interrupt-cells = <1>; 501 }; 502 }; 503 }; 504}; 505