1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for CZ.NIC Turris Mox Board 4 * 2019 by Marek Behún <kabel@kernel.org> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/bus/moxtet.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include "armada-372x.dtsi" 13 14/ { 15 model = "CZ.NIC Turris Mox Board"; 16 compatible = "cznic,turris-mox", "marvell,armada3720", 17 "marvell,armada3710"; 18 19 aliases { 20 spi0 = &spi0; 21 ethernet1 = ð1; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 memory@0 { 29 device_type = "memory"; 30 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 31 }; 32 33 leds { 34 compatible = "gpio-leds"; 35 red { 36 label = "mox:red:activity"; 37 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 38 linux,default-trigger = "default-on"; 39 }; 40 }; 41 42 gpio-keys { 43 compatible = "gpio-keys"; 44 45 reset { 46 label = "reset"; 47 linux,code = <KEY_RESTART>; 48 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 49 debounce-interval = <60>; 50 }; 51 }; 52 53 exp_usb3_vbus: usb3-vbus { 54 compatible = "regulator-fixed"; 55 regulator-name = "usb3-vbus"; 56 regulator-min-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>; 58 enable-active-high; 59 regulator-always-on; 60 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 61 }; 62 63 vsdc_reg: vsdc-reg { 64 compatible = "regulator-gpio"; 65 regulator-name = "vsdc"; 66 regulator-min-microvolt = <1800000>; 67 regulator-max-microvolt = <3300000>; 68 regulator-boot-on; 69 70 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 71 gpios-states = <0>; 72 states = <1800000 0x1 73 3300000 0x0>; 74 enable-active-high; 75 }; 76 77 vsdio_reg: vsdio-reg { 78 compatible = "regulator-gpio"; 79 regulator-name = "vsdio"; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <3300000>; 82 regulator-boot-on; 83 84 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 85 gpios-states = <0>; 86 states = <1800000 0x1 87 3300000 0x0>; 88 enable-active-high; 89 }; 90 91 sdhci1_pwrseq: sdhci1-pwrseq { 92 compatible = "mmc-pwrseq-simple"; 93 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 94 status = "okay"; 95 }; 96 97 sfp: sfp { 98 compatible = "sff,sfp"; 99 i2c-bus = <&i2c0>; 100 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 101 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 102 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 103 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 104 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 105 maximum-power-milliwatt = <3000>; 106 107 /* enabled by U-Boot if SFP module is present */ 108 status = "disabled"; 109 }; 110 111 firmware { 112 turris-mox-rwtm { 113 compatible = "cznic,turris-mox-rwtm"; 114 mboxes = <&rwtm 0>; 115 status = "okay"; 116 }; 117 }; 118}; 119 120&i2c0 { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&i2c1_pins>; 123 clock-frequency = <100000>; 124 status = "okay"; 125 126 rtc@6f { 127 compatible = "microchip,mcp7940x"; 128 reg = <0x6f>; 129 }; 130}; 131 132&pcie0 { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 135 status = "okay"; 136 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 137 138 /* enabled by U-Boot if PCIe module is present */ 139 status = "disabled"; 140}; 141 142&uart0 { 143 status = "okay"; 144}; 145 146ð0 { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&rgmii_pins>; 149 phy-mode = "rgmii-id"; 150 phy-handle = <&phy1>; 151 status = "okay"; 152}; 153 154ð1 { 155 phy-mode = "2500base-x"; 156 managed = "in-band-status"; 157 phys = <&comphy0 1>; 158}; 159 160&sdhci0 { 161 wp-inverted; 162 bus-width = <4>; 163 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 164 vqmmc-supply = <&vsdc_reg>; 165 marvell,pad-type = "sd"; 166 status = "okay"; 167}; 168 169&sdhci1 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&sdio_pins>; 172 non-removable; 173 bus-width = <4>; 174 marvell,pad-type = "sd"; 175 vqmmc-supply = <&vsdio_reg>; 176 mmc-pwrseq = <&sdhci1_pwrseq>; 177 /* forbid SDR104 for FCC purposes */ 178 sdhci-caps-mask = <0x2 0x0>; 179 status = "okay"; 180}; 181 182&spi0 { 183 status = "okay"; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 186 assigned-clocks = <&nb_periph_clk 7>; 187 assigned-clock-parents = <&tbg 1>; 188 assigned-clock-rates = <20000000>; 189 190 spi-flash@0 { 191 #address-cells = <1>; 192 #size-cells = <1>; 193 compatible = "jedec,spi-nor"; 194 reg = <0>; 195 spi-max-frequency = <20000000>; 196 197 partitions { 198 compatible = "fixed-partitions"; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 202 partition@0 { 203 label = "secure-firmware"; 204 reg = <0x0 0x20000>; 205 }; 206 207 partition@20000 { 208 label = "a53-firmware"; 209 reg = <0x20000 0x160000>; 210 }; 211 212 partition@180000 { 213 label = "u-boot-env"; 214 reg = <0x180000 0x10000>; 215 }; 216 217 partition@190000 { 218 label = "Rescue system"; 219 reg = <0x190000 0x660000>; 220 }; 221 222 partition@7f0000 { 223 label = "dtb"; 224 reg = <0x7f0000 0x10000>; 225 }; 226 }; 227 }; 228 229 moxtet: moxtet@1 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "cznic,moxtet"; 233 reg = <1>; 234 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 235 spi-max-frequency = <10000000>; 236 spi-cpol; 237 spi-cpha; 238 interrupt-controller; 239 #interrupt-cells = <1>; 240 interrupt-parent = <&gpiosb>; 241 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 242 status = "okay"; 243 244 moxtet_sfp: gpio@0 { 245 compatible = "cznic,moxtet-gpio"; 246 gpio-controller; 247 #gpio-cells = <2>; 248 reg = <0>; 249 status = "disabled"; 250 }; 251 }; 252}; 253 254&usb2 { 255 status = "okay"; 256}; 257 258&comphy2 { 259 connector { 260 compatible = "usb-a-connector"; 261 phy-supply = <&exp_usb3_vbus>; 262 }; 263}; 264 265&usb3 { 266 status = "okay"; 267 phys = <&comphy2 0>; 268}; 269 270&mdio { 271 pinctrl-names = "default"; 272 pinctrl-0 = <&smi_pins>; 273 status = "okay"; 274 275 phy1: ethernet-phy@1 { 276 reg = <1>; 277 }; 278 279 /* switch nodes are enabled by U-Boot if modules are present */ 280 switch0@10 { 281 compatible = "marvell,mv88e6190"; 282 reg = <0x10 0>; 283 dsa,member = <0 0>; 284 interrupt-parent = <&moxtet>; 285 interrupts = <MOXTET_IRQ_PERIDOT(0)>; 286 status = "disabled"; 287 288 mdio { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 292 switch0phy1: switch0phy1@1 { 293 reg = <0x1>; 294 }; 295 296 switch0phy2: switch0phy2@2 { 297 reg = <0x2>; 298 }; 299 300 switch0phy3: switch0phy3@3 { 301 reg = <0x3>; 302 }; 303 304 switch0phy4: switch0phy4@4 { 305 reg = <0x4>; 306 }; 307 308 switch0phy5: switch0phy5@5 { 309 reg = <0x5>; 310 }; 311 312 switch0phy6: switch0phy6@6 { 313 reg = <0x6>; 314 }; 315 316 switch0phy7: switch0phy7@7 { 317 reg = <0x7>; 318 }; 319 320 switch0phy8: switch0phy8@8 { 321 reg = <0x8>; 322 }; 323 }; 324 325 ports { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 port@1 { 330 reg = <0x1>; 331 label = "lan1"; 332 phy-handle = <&switch0phy1>; 333 }; 334 335 port@2 { 336 reg = <0x2>; 337 label = "lan2"; 338 phy-handle = <&switch0phy2>; 339 }; 340 341 port@3 { 342 reg = <0x3>; 343 label = "lan3"; 344 phy-handle = <&switch0phy3>; 345 }; 346 347 port@4 { 348 reg = <0x4>; 349 label = "lan4"; 350 phy-handle = <&switch0phy4>; 351 }; 352 353 port@5 { 354 reg = <0x5>; 355 label = "lan5"; 356 phy-handle = <&switch0phy5>; 357 }; 358 359 port@6 { 360 reg = <0x6>; 361 label = "lan6"; 362 phy-handle = <&switch0phy6>; 363 }; 364 365 port@7 { 366 reg = <0x7>; 367 label = "lan7"; 368 phy-handle = <&switch0phy7>; 369 }; 370 371 port@8 { 372 reg = <0x8>; 373 label = "lan8"; 374 phy-handle = <&switch0phy8>; 375 }; 376 377 port@9 { 378 reg = <0x9>; 379 label = "cpu"; 380 ethernet = <ð1>; 381 phy-mode = "2500base-x"; 382 managed = "in-band-status"; 383 }; 384 385 switch0port10: port@a { 386 reg = <0xa>; 387 label = "dsa"; 388 phy-mode = "2500base-x"; 389 managed = "in-band-status"; 390 link = <&switch1port9 &switch2port9>; 391 status = "disabled"; 392 }; 393 394 port-sfp@a { 395 reg = <0xa>; 396 label = "sfp"; 397 sfp = <&sfp>; 398 phy-mode = "sgmii"; 399 managed = "in-band-status"; 400 status = "disabled"; 401 }; 402 }; 403 }; 404 405 switch0@2 { 406 compatible = "marvell,mv88e6085"; 407 reg = <0x2 0>; 408 dsa,member = <0 0>; 409 interrupt-parent = <&moxtet>; 410 interrupts = <MOXTET_IRQ_TOPAZ>; 411 status = "disabled"; 412 413 mdio { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 switch0phy1_topaz: switch0phy1@11 { 418 reg = <0x11>; 419 }; 420 421 switch0phy2_topaz: switch0phy2@12 { 422 reg = <0x12>; 423 }; 424 425 switch0phy3_topaz: switch0phy3@13 { 426 reg = <0x13>; 427 }; 428 429 switch0phy4_topaz: switch0phy4@14 { 430 reg = <0x14>; 431 }; 432 }; 433 434 ports { 435 #address-cells = <1>; 436 #size-cells = <0>; 437 438 port@1 { 439 reg = <0x1>; 440 label = "lan1"; 441 phy-handle = <&switch0phy1_topaz>; 442 }; 443 444 port@2 { 445 reg = <0x2>; 446 label = "lan2"; 447 phy-handle = <&switch0phy2_topaz>; 448 }; 449 450 port@3 { 451 reg = <0x3>; 452 label = "lan3"; 453 phy-handle = <&switch0phy3_topaz>; 454 }; 455 456 port@4 { 457 reg = <0x4>; 458 label = "lan4"; 459 phy-handle = <&switch0phy4_topaz>; 460 }; 461 462 port@5 { 463 reg = <0x5>; 464 label = "cpu"; 465 phy-mode = "2500base-x"; 466 managed = "in-band-status"; 467 ethernet = <ð1>; 468 }; 469 }; 470 }; 471 472 switch1@11 { 473 compatible = "marvell,mv88e6190"; 474 reg = <0x11 0>; 475 dsa,member = <0 1>; 476 interrupt-parent = <&moxtet>; 477 interrupts = <MOXTET_IRQ_PERIDOT(1)>; 478 status = "disabled"; 479 480 mdio { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 switch1phy1: switch1phy1@1 { 485 reg = <0x1>; 486 }; 487 488 switch1phy2: switch1phy2@2 { 489 reg = <0x2>; 490 }; 491 492 switch1phy3: switch1phy3@3 { 493 reg = <0x3>; 494 }; 495 496 switch1phy4: switch1phy4@4 { 497 reg = <0x4>; 498 }; 499 500 switch1phy5: switch1phy5@5 { 501 reg = <0x5>; 502 }; 503 504 switch1phy6: switch1phy6@6 { 505 reg = <0x6>; 506 }; 507 508 switch1phy7: switch1phy7@7 { 509 reg = <0x7>; 510 }; 511 512 switch1phy8: switch1phy8@8 { 513 reg = <0x8>; 514 }; 515 }; 516 517 ports { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 521 port@1 { 522 reg = <0x1>; 523 label = "lan9"; 524 phy-handle = <&switch1phy1>; 525 }; 526 527 port@2 { 528 reg = <0x2>; 529 label = "lan10"; 530 phy-handle = <&switch1phy2>; 531 }; 532 533 port@3 { 534 reg = <0x3>; 535 label = "lan11"; 536 phy-handle = <&switch1phy3>; 537 }; 538 539 port@4 { 540 reg = <0x4>; 541 label = "lan12"; 542 phy-handle = <&switch1phy4>; 543 }; 544 545 port@5 { 546 reg = <0x5>; 547 label = "lan13"; 548 phy-handle = <&switch1phy5>; 549 }; 550 551 port@6 { 552 reg = <0x6>; 553 label = "lan14"; 554 phy-handle = <&switch1phy6>; 555 }; 556 557 port@7 { 558 reg = <0x7>; 559 label = "lan15"; 560 phy-handle = <&switch1phy7>; 561 }; 562 563 port@8 { 564 reg = <0x8>; 565 label = "lan16"; 566 phy-handle = <&switch1phy8>; 567 }; 568 569 switch1port9: port@9 { 570 reg = <0x9>; 571 label = "dsa"; 572 phy-mode = "2500base-x"; 573 managed = "in-band-status"; 574 link = <&switch0port10>; 575 }; 576 577 switch1port10: port@a { 578 reg = <0xa>; 579 label = "dsa"; 580 phy-mode = "2500base-x"; 581 managed = "in-band-status"; 582 link = <&switch2port9>; 583 status = "disabled"; 584 }; 585 586 port-sfp@a { 587 reg = <0xa>; 588 label = "sfp"; 589 sfp = <&sfp>; 590 phy-mode = "sgmii"; 591 managed = "in-band-status"; 592 status = "disabled"; 593 }; 594 }; 595 }; 596 597 switch1@2 { 598 compatible = "marvell,mv88e6085"; 599 reg = <0x2 0>; 600 dsa,member = <0 1>; 601 interrupt-parent = <&moxtet>; 602 interrupts = <MOXTET_IRQ_TOPAZ>; 603 status = "disabled"; 604 605 mdio { 606 #address-cells = <1>; 607 #size-cells = <0>; 608 609 switch1phy1_topaz: switch1phy1@11 { 610 reg = <0x11>; 611 }; 612 613 switch1phy2_topaz: switch1phy2@12 { 614 reg = <0x12>; 615 }; 616 617 switch1phy3_topaz: switch1phy3@13 { 618 reg = <0x13>; 619 }; 620 621 switch1phy4_topaz: switch1phy4@14 { 622 reg = <0x14>; 623 }; 624 }; 625 626 ports { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 630 port@1 { 631 reg = <0x1>; 632 label = "lan9"; 633 phy-handle = <&switch1phy1_topaz>; 634 }; 635 636 port@2 { 637 reg = <0x2>; 638 label = "lan10"; 639 phy-handle = <&switch1phy2_topaz>; 640 }; 641 642 port@3 { 643 reg = <0x3>; 644 label = "lan11"; 645 phy-handle = <&switch1phy3_topaz>; 646 }; 647 648 port@4 { 649 reg = <0x4>; 650 label = "lan12"; 651 phy-handle = <&switch1phy4_topaz>; 652 }; 653 654 port@5 { 655 reg = <0x5>; 656 label = "dsa"; 657 phy-mode = "2500base-x"; 658 managed = "in-band-status"; 659 link = <&switch0port10>; 660 }; 661 }; 662 }; 663 664 switch2@12 { 665 compatible = "marvell,mv88e6190"; 666 reg = <0x12 0>; 667 dsa,member = <0 2>; 668 interrupt-parent = <&moxtet>; 669 interrupts = <MOXTET_IRQ_PERIDOT(2)>; 670 status = "disabled"; 671 672 mdio { 673 #address-cells = <1>; 674 #size-cells = <0>; 675 676 switch2phy1: switch2phy1@1 { 677 reg = <0x1>; 678 }; 679 680 switch2phy2: switch2phy2@2 { 681 reg = <0x2>; 682 }; 683 684 switch2phy3: switch2phy3@3 { 685 reg = <0x3>; 686 }; 687 688 switch2phy4: switch2phy4@4 { 689 reg = <0x4>; 690 }; 691 692 switch2phy5: switch2phy5@5 { 693 reg = <0x5>; 694 }; 695 696 switch2phy6: switch2phy6@6 { 697 reg = <0x6>; 698 }; 699 700 switch2phy7: switch2phy7@7 { 701 reg = <0x7>; 702 }; 703 704 switch2phy8: switch2phy8@8 { 705 reg = <0x8>; 706 }; 707 }; 708 709 ports { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 713 port@1 { 714 reg = <0x1>; 715 label = "lan17"; 716 phy-handle = <&switch2phy1>; 717 }; 718 719 port@2 { 720 reg = <0x2>; 721 label = "lan18"; 722 phy-handle = <&switch2phy2>; 723 }; 724 725 port@3 { 726 reg = <0x3>; 727 label = "lan19"; 728 phy-handle = <&switch2phy3>; 729 }; 730 731 port@4 { 732 reg = <0x4>; 733 label = "lan20"; 734 phy-handle = <&switch2phy4>; 735 }; 736 737 port@5 { 738 reg = <0x5>; 739 label = "lan21"; 740 phy-handle = <&switch2phy5>; 741 }; 742 743 port@6 { 744 reg = <0x6>; 745 label = "lan22"; 746 phy-handle = <&switch2phy6>; 747 }; 748 749 port@7 { 750 reg = <0x7>; 751 label = "lan23"; 752 phy-handle = <&switch2phy7>; 753 }; 754 755 port@8 { 756 reg = <0x8>; 757 label = "lan24"; 758 phy-handle = <&switch2phy8>; 759 }; 760 761 switch2port9: port@9 { 762 reg = <0x9>; 763 label = "dsa"; 764 phy-mode = "2500base-x"; 765 managed = "in-band-status"; 766 link = <&switch1port10 &switch0port10>; 767 }; 768 769 port-sfp@a { 770 reg = <0xa>; 771 label = "sfp"; 772 sfp = <&sfp>; 773 phy-mode = "sgmii"; 774 managed = "in-band-status"; 775 status = "disabled"; 776 }; 777 }; 778 }; 779 780 switch2@2 { 781 compatible = "marvell,mv88e6085"; 782 reg = <0x2 0>; 783 dsa,member = <0 2>; 784 interrupt-parent = <&moxtet>; 785 interrupts = <MOXTET_IRQ_TOPAZ>; 786 status = "disabled"; 787 788 mdio { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 792 switch2phy1_topaz: switch2phy1@11 { 793 reg = <0x11>; 794 }; 795 796 switch2phy2_topaz: switch2phy2@12 { 797 reg = <0x12>; 798 }; 799 800 switch2phy3_topaz: switch2phy3@13 { 801 reg = <0x13>; 802 }; 803 804 switch2phy4_topaz: switch2phy4@14 { 805 reg = <0x14>; 806 }; 807 }; 808 809 ports { 810 #address-cells = <1>; 811 #size-cells = <0>; 812 813 port@1 { 814 reg = <0x1>; 815 label = "lan17"; 816 phy-handle = <&switch2phy1_topaz>; 817 }; 818 819 port@2 { 820 reg = <0x2>; 821 label = "lan18"; 822 phy-handle = <&switch2phy2_topaz>; 823 }; 824 825 port@3 { 826 reg = <0x3>; 827 label = "lan19"; 828 phy-handle = <&switch2phy3_topaz>; 829 }; 830 831 port@4 { 832 reg = <0x4>; 833 label = "lan20"; 834 phy-handle = <&switch2phy4_topaz>; 835 }; 836 837 port@5 { 838 reg = <0x5>; 839 label = "dsa"; 840 phy-mode = "2500base-x"; 841 managed = "in-band-status"; 842 link = <&switch1port10 &switch0port10>; 843 }; 844 }; 845 }; 846}; 847