1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for CZ.NIC Turris Mox Board 4 * 2019 by Marek Behún <kabel@kernel.org> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/bus/moxtet.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include "armada-372x.dtsi" 13 14/ { 15 model = "CZ.NIC Turris Mox Board"; 16 compatible = "cznic,turris-mox", "marvell,armada3720", 17 "marvell,armada3710"; 18 19 aliases { 20 spi0 = &spi0; 21 ethernet1 = ð1; 22 mmc0 = &sdhci0; 23 mmc1 = &sdhci1; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@0 { 31 device_type = "memory"; 32 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 33 }; 34 35 leds { 36 compatible = "gpio-leds"; 37 red { 38 label = "mox:red:activity"; 39 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 40 linux,default-trigger = "default-on"; 41 }; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 47 reset { 48 label = "reset"; 49 linux,code = <KEY_RESTART>; 50 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 51 debounce-interval = <60>; 52 }; 53 }; 54 55 exp_usb3_vbus: usb3-vbus { 56 compatible = "regulator-fixed"; 57 regulator-name = "usb3-vbus"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 enable-active-high; 61 regulator-always-on; 62 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 63 }; 64 65 vsdc_reg: vsdc-reg { 66 compatible = "regulator-gpio"; 67 regulator-name = "vsdc"; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <3300000>; 70 regulator-boot-on; 71 72 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 73 gpios-states = <0>; 74 states = <1800000 0x1 75 3300000 0x0>; 76 enable-active-high; 77 }; 78 79 vsdio_reg: vsdio-reg { 80 compatible = "regulator-gpio"; 81 regulator-name = "vsdio"; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <3300000>; 84 regulator-boot-on; 85 86 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 87 gpios-states = <0>; 88 states = <1800000 0x1 89 3300000 0x0>; 90 enable-active-high; 91 }; 92 93 sdhci1_pwrseq: sdhci1-pwrseq { 94 compatible = "mmc-pwrseq-simple"; 95 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 96 status = "okay"; 97 }; 98 99 sfp: sfp { 100 compatible = "sff,sfp"; 101 i2c-bus = <&i2c0>; 102 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 103 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 104 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 105 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 106 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 107 maximum-power-milliwatt = <3000>; 108 109 /* enabled by U-Boot if SFP module is present */ 110 status = "disabled"; 111 }; 112 113 firmware { 114 armada-3700-rwtm { 115 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; 116 }; 117 }; 118}; 119 120&i2c0 { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&i2c1_pins>; 123 clock-frequency = <100000>; 124 /delete-property/ mrvl,i2c-fast-mode; 125 status = "okay"; 126 127 rtc@6f { 128 compatible = "microchip,mcp7940x"; 129 reg = <0x6f>; 130 }; 131}; 132 133&pcie0 { 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 136 status = "okay"; 137 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 138 /* 139 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property 140 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and 141 * 2 size cells and also expects that the second range starts at 16 MB offset. If these 142 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address 143 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window 144 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. 145 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in 146 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): 147 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 148 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf 149 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 150 */ 151 #address-cells = <3>; 152 #size-cells = <2>; 153 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ 154 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ 155 156 /* enabled by U-Boot if PCIe module is present */ 157 status = "disabled"; 158}; 159 160&uart0 { 161 status = "okay"; 162}; 163 164ð0 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&rgmii_pins>; 167 phy-mode = "rgmii-id"; 168 phy-handle = <&phy1>; 169 status = "okay"; 170}; 171 172ð1 { 173 phy-mode = "2500base-x"; 174 managed = "in-band-status"; 175 phys = <&comphy0 1>; 176}; 177 178&sdhci0 { 179 wp-inverted; 180 bus-width = <4>; 181 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 182 vqmmc-supply = <&vsdc_reg>; 183 marvell,pad-type = "sd"; 184 status = "okay"; 185}; 186 187&sdhci1 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&sdio_pins>; 190 non-removable; 191 bus-width = <4>; 192 marvell,pad-type = "sd"; 193 vqmmc-supply = <&vsdio_reg>; 194 mmc-pwrseq = <&sdhci1_pwrseq>; 195 /* forbid SDR104 for FCC purposes */ 196 sdhci-caps-mask = <0x2 0x0>; 197 status = "okay"; 198}; 199 200&spi0 { 201 status = "okay"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 204 assigned-clocks = <&nb_periph_clk 7>; 205 assigned-clock-parents = <&tbg 1>; 206 assigned-clock-rates = <20000000>; 207 208 spi-flash@0 { 209 #address-cells = <1>; 210 #size-cells = <1>; 211 compatible = "jedec,spi-nor"; 212 reg = <0>; 213 spi-max-frequency = <20000000>; 214 215 partitions { 216 compatible = "fixed-partitions"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 220 partition@0 { 221 label = "secure-firmware"; 222 reg = <0x0 0x20000>; 223 }; 224 225 partition@20000 { 226 label = "a53-firmware"; 227 reg = <0x20000 0x160000>; 228 }; 229 230 partition@180000 { 231 label = "u-boot-env"; 232 reg = <0x180000 0x10000>; 233 }; 234 235 partition@190000 { 236 label = "Rescue system"; 237 reg = <0x190000 0x660000>; 238 }; 239 240 partition@7f0000 { 241 label = "dtb"; 242 reg = <0x7f0000 0x10000>; 243 }; 244 }; 245 }; 246 247 moxtet: moxtet@1 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "cznic,moxtet"; 251 reg = <1>; 252 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 253 spi-max-frequency = <10000000>; 254 spi-cpol; 255 spi-cpha; 256 interrupt-controller; 257 #interrupt-cells = <1>; 258 interrupt-parent = <&gpiosb>; 259 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 260 status = "okay"; 261 262 moxtet_sfp: gpio@0 { 263 compatible = "cznic,moxtet-gpio"; 264 gpio-controller; 265 #gpio-cells = <2>; 266 reg = <0>; 267 status = "disabled"; 268 }; 269 }; 270}; 271 272&usb2 { 273 status = "okay"; 274}; 275 276&comphy2 { 277 connector { 278 compatible = "usb-a-connector"; 279 phy-supply = <&exp_usb3_vbus>; 280 }; 281}; 282 283&usb3 { 284 status = "okay"; 285 phys = <&comphy2 0>; 286}; 287 288&mdio { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&smi_pins>; 291 status = "okay"; 292 293 phy1: ethernet-phy@1 { 294 reg = <1>; 295 }; 296 297 /* switch nodes are enabled by U-Boot if modules are present */ 298 switch0@10 { 299 compatible = "marvell,mv88e6190"; 300 reg = <0x10 0>; 301 dsa,member = <0 0>; 302 interrupt-parent = <&moxtet>; 303 interrupts = <MOXTET_IRQ_PERIDOT(0)>; 304 status = "disabled"; 305 306 mdio { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 310 switch0phy1: switch0phy1@1 { 311 reg = <0x1>; 312 }; 313 314 switch0phy2: switch0phy2@2 { 315 reg = <0x2>; 316 }; 317 318 switch0phy3: switch0phy3@3 { 319 reg = <0x3>; 320 }; 321 322 switch0phy4: switch0phy4@4 { 323 reg = <0x4>; 324 }; 325 326 switch0phy5: switch0phy5@5 { 327 reg = <0x5>; 328 }; 329 330 switch0phy6: switch0phy6@6 { 331 reg = <0x6>; 332 }; 333 334 switch0phy7: switch0phy7@7 { 335 reg = <0x7>; 336 }; 337 338 switch0phy8: switch0phy8@8 { 339 reg = <0x8>; 340 }; 341 }; 342 343 ports { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 347 port@1 { 348 reg = <0x1>; 349 label = "lan1"; 350 phy-handle = <&switch0phy1>; 351 }; 352 353 port@2 { 354 reg = <0x2>; 355 label = "lan2"; 356 phy-handle = <&switch0phy2>; 357 }; 358 359 port@3 { 360 reg = <0x3>; 361 label = "lan3"; 362 phy-handle = <&switch0phy3>; 363 }; 364 365 port@4 { 366 reg = <0x4>; 367 label = "lan4"; 368 phy-handle = <&switch0phy4>; 369 }; 370 371 port@5 { 372 reg = <0x5>; 373 label = "lan5"; 374 phy-handle = <&switch0phy5>; 375 }; 376 377 port@6 { 378 reg = <0x6>; 379 label = "lan6"; 380 phy-handle = <&switch0phy6>; 381 }; 382 383 port@7 { 384 reg = <0x7>; 385 label = "lan7"; 386 phy-handle = <&switch0phy7>; 387 }; 388 389 port@8 { 390 reg = <0x8>; 391 label = "lan8"; 392 phy-handle = <&switch0phy8>; 393 }; 394 395 port@9 { 396 reg = <0x9>; 397 label = "cpu"; 398 ethernet = <ð1>; 399 phy-mode = "2500base-x"; 400 managed = "in-band-status"; 401 }; 402 403 switch0port10: port@a { 404 reg = <0xa>; 405 label = "dsa"; 406 phy-mode = "2500base-x"; 407 managed = "in-band-status"; 408 link = <&switch1port9 &switch2port9>; 409 status = "disabled"; 410 }; 411 412 port-sfp@a { 413 reg = <0xa>; 414 label = "sfp"; 415 sfp = <&sfp>; 416 phy-mode = "sgmii"; 417 managed = "in-band-status"; 418 status = "disabled"; 419 }; 420 }; 421 }; 422 423 switch0@2 { 424 compatible = "marvell,mv88e6085"; 425 reg = <0x2 0>; 426 dsa,member = <0 0>; 427 interrupt-parent = <&moxtet>; 428 interrupts = <MOXTET_IRQ_TOPAZ>; 429 status = "disabled"; 430 431 mdio { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 435 switch0phy1_topaz: switch0phy1@11 { 436 reg = <0x11>; 437 }; 438 439 switch0phy2_topaz: switch0phy2@12 { 440 reg = <0x12>; 441 }; 442 443 switch0phy3_topaz: switch0phy3@13 { 444 reg = <0x13>; 445 }; 446 447 switch0phy4_topaz: switch0phy4@14 { 448 reg = <0x14>; 449 }; 450 }; 451 452 ports { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 456 port@1 { 457 reg = <0x1>; 458 label = "lan1"; 459 phy-handle = <&switch0phy1_topaz>; 460 }; 461 462 port@2 { 463 reg = <0x2>; 464 label = "lan2"; 465 phy-handle = <&switch0phy2_topaz>; 466 }; 467 468 port@3 { 469 reg = <0x3>; 470 label = "lan3"; 471 phy-handle = <&switch0phy3_topaz>; 472 }; 473 474 port@4 { 475 reg = <0x4>; 476 label = "lan4"; 477 phy-handle = <&switch0phy4_topaz>; 478 }; 479 480 port@5 { 481 reg = <0x5>; 482 label = "cpu"; 483 phy-mode = "2500base-x"; 484 managed = "in-band-status"; 485 ethernet = <ð1>; 486 }; 487 }; 488 }; 489 490 switch1@11 { 491 compatible = "marvell,mv88e6190"; 492 reg = <0x11 0>; 493 dsa,member = <0 1>; 494 interrupt-parent = <&moxtet>; 495 interrupts = <MOXTET_IRQ_PERIDOT(1)>; 496 status = "disabled"; 497 498 mdio { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 502 switch1phy1: switch1phy1@1 { 503 reg = <0x1>; 504 }; 505 506 switch1phy2: switch1phy2@2 { 507 reg = <0x2>; 508 }; 509 510 switch1phy3: switch1phy3@3 { 511 reg = <0x3>; 512 }; 513 514 switch1phy4: switch1phy4@4 { 515 reg = <0x4>; 516 }; 517 518 switch1phy5: switch1phy5@5 { 519 reg = <0x5>; 520 }; 521 522 switch1phy6: switch1phy6@6 { 523 reg = <0x6>; 524 }; 525 526 switch1phy7: switch1phy7@7 { 527 reg = <0x7>; 528 }; 529 530 switch1phy8: switch1phy8@8 { 531 reg = <0x8>; 532 }; 533 }; 534 535 ports { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 539 port@1 { 540 reg = <0x1>; 541 label = "lan9"; 542 phy-handle = <&switch1phy1>; 543 }; 544 545 port@2 { 546 reg = <0x2>; 547 label = "lan10"; 548 phy-handle = <&switch1phy2>; 549 }; 550 551 port@3 { 552 reg = <0x3>; 553 label = "lan11"; 554 phy-handle = <&switch1phy3>; 555 }; 556 557 port@4 { 558 reg = <0x4>; 559 label = "lan12"; 560 phy-handle = <&switch1phy4>; 561 }; 562 563 port@5 { 564 reg = <0x5>; 565 label = "lan13"; 566 phy-handle = <&switch1phy5>; 567 }; 568 569 port@6 { 570 reg = <0x6>; 571 label = "lan14"; 572 phy-handle = <&switch1phy6>; 573 }; 574 575 port@7 { 576 reg = <0x7>; 577 label = "lan15"; 578 phy-handle = <&switch1phy7>; 579 }; 580 581 port@8 { 582 reg = <0x8>; 583 label = "lan16"; 584 phy-handle = <&switch1phy8>; 585 }; 586 587 switch1port9: port@9 { 588 reg = <0x9>; 589 label = "dsa"; 590 phy-mode = "2500base-x"; 591 managed = "in-band-status"; 592 link = <&switch0port10>; 593 }; 594 595 switch1port10: port@a { 596 reg = <0xa>; 597 label = "dsa"; 598 phy-mode = "2500base-x"; 599 managed = "in-band-status"; 600 link = <&switch2port9>; 601 status = "disabled"; 602 }; 603 604 port-sfp@a { 605 reg = <0xa>; 606 label = "sfp"; 607 sfp = <&sfp>; 608 phy-mode = "sgmii"; 609 managed = "in-band-status"; 610 status = "disabled"; 611 }; 612 }; 613 }; 614 615 switch1@2 { 616 compatible = "marvell,mv88e6085"; 617 reg = <0x2 0>; 618 dsa,member = <0 1>; 619 interrupt-parent = <&moxtet>; 620 interrupts = <MOXTET_IRQ_TOPAZ>; 621 status = "disabled"; 622 623 mdio { 624 #address-cells = <1>; 625 #size-cells = <0>; 626 627 switch1phy1_topaz: switch1phy1@11 { 628 reg = <0x11>; 629 }; 630 631 switch1phy2_topaz: switch1phy2@12 { 632 reg = <0x12>; 633 }; 634 635 switch1phy3_topaz: switch1phy3@13 { 636 reg = <0x13>; 637 }; 638 639 switch1phy4_topaz: switch1phy4@14 { 640 reg = <0x14>; 641 }; 642 }; 643 644 ports { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 port@1 { 649 reg = <0x1>; 650 label = "lan9"; 651 phy-handle = <&switch1phy1_topaz>; 652 }; 653 654 port@2 { 655 reg = <0x2>; 656 label = "lan10"; 657 phy-handle = <&switch1phy2_topaz>; 658 }; 659 660 port@3 { 661 reg = <0x3>; 662 label = "lan11"; 663 phy-handle = <&switch1phy3_topaz>; 664 }; 665 666 port@4 { 667 reg = <0x4>; 668 label = "lan12"; 669 phy-handle = <&switch1phy4_topaz>; 670 }; 671 672 port@5 { 673 reg = <0x5>; 674 label = "dsa"; 675 phy-mode = "2500base-x"; 676 managed = "in-band-status"; 677 link = <&switch0port10>; 678 }; 679 }; 680 }; 681 682 switch2@12 { 683 compatible = "marvell,mv88e6190"; 684 reg = <0x12 0>; 685 dsa,member = <0 2>; 686 interrupt-parent = <&moxtet>; 687 interrupts = <MOXTET_IRQ_PERIDOT(2)>; 688 status = "disabled"; 689 690 mdio { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 694 switch2phy1: switch2phy1@1 { 695 reg = <0x1>; 696 }; 697 698 switch2phy2: switch2phy2@2 { 699 reg = <0x2>; 700 }; 701 702 switch2phy3: switch2phy3@3 { 703 reg = <0x3>; 704 }; 705 706 switch2phy4: switch2phy4@4 { 707 reg = <0x4>; 708 }; 709 710 switch2phy5: switch2phy5@5 { 711 reg = <0x5>; 712 }; 713 714 switch2phy6: switch2phy6@6 { 715 reg = <0x6>; 716 }; 717 718 switch2phy7: switch2phy7@7 { 719 reg = <0x7>; 720 }; 721 722 switch2phy8: switch2phy8@8 { 723 reg = <0x8>; 724 }; 725 }; 726 727 ports { 728 #address-cells = <1>; 729 #size-cells = <0>; 730 731 port@1 { 732 reg = <0x1>; 733 label = "lan17"; 734 phy-handle = <&switch2phy1>; 735 }; 736 737 port@2 { 738 reg = <0x2>; 739 label = "lan18"; 740 phy-handle = <&switch2phy2>; 741 }; 742 743 port@3 { 744 reg = <0x3>; 745 label = "lan19"; 746 phy-handle = <&switch2phy3>; 747 }; 748 749 port@4 { 750 reg = <0x4>; 751 label = "lan20"; 752 phy-handle = <&switch2phy4>; 753 }; 754 755 port@5 { 756 reg = <0x5>; 757 label = "lan21"; 758 phy-handle = <&switch2phy5>; 759 }; 760 761 port@6 { 762 reg = <0x6>; 763 label = "lan22"; 764 phy-handle = <&switch2phy6>; 765 }; 766 767 port@7 { 768 reg = <0x7>; 769 label = "lan23"; 770 phy-handle = <&switch2phy7>; 771 }; 772 773 port@8 { 774 reg = <0x8>; 775 label = "lan24"; 776 phy-handle = <&switch2phy8>; 777 }; 778 779 switch2port9: port@9 { 780 reg = <0x9>; 781 label = "dsa"; 782 phy-mode = "2500base-x"; 783 managed = "in-band-status"; 784 link = <&switch1port10 &switch0port10>; 785 }; 786 787 port-sfp@a { 788 reg = <0xa>; 789 label = "sfp"; 790 sfp = <&sfp>; 791 phy-mode = "sgmii"; 792 managed = "in-band-status"; 793 status = "disabled"; 794 }; 795 }; 796 }; 797 798 switch2@2 { 799 compatible = "marvell,mv88e6085"; 800 reg = <0x2 0>; 801 dsa,member = <0 2>; 802 interrupt-parent = <&moxtet>; 803 interrupts = <MOXTET_IRQ_TOPAZ>; 804 status = "disabled"; 805 806 mdio { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 810 switch2phy1_topaz: switch2phy1@11 { 811 reg = <0x11>; 812 }; 813 814 switch2phy2_topaz: switch2phy2@12 { 815 reg = <0x12>; 816 }; 817 818 switch2phy3_topaz: switch2phy3@13 { 819 reg = <0x13>; 820 }; 821 822 switch2phy4_topaz: switch2phy4@14 { 823 reg = <0x14>; 824 }; 825 }; 826 827 ports { 828 #address-cells = <1>; 829 #size-cells = <0>; 830 831 port@1 { 832 reg = <0x1>; 833 label = "lan17"; 834 phy-handle = <&switch2phy1_topaz>; 835 }; 836 837 port@2 { 838 reg = <0x2>; 839 label = "lan18"; 840 phy-handle = <&switch2phy2_topaz>; 841 }; 842 843 port@3 { 844 reg = <0x3>; 845 label = "lan19"; 846 phy-handle = <&switch2phy3_topaz>; 847 }; 848 849 port@4 { 850 reg = <0x4>; 851 label = "lan20"; 852 phy-handle = <&switch2phy4_topaz>; 853 }; 854 855 port@5 { 856 reg = <0x5>; 857 label = "dsa"; 858 phy-mode = "2500base-x"; 859 managed = "in-band-status"; 860 link = <&switch1port10 &switch0port10>; 861 }; 862 }; 863 }; 864}; 865