1// SPDX-License-Identifier: GPL-2.0-only 2/** 3 * dts file for Hisilicon D02 Development Board 4 * 5 * Copyright (C) 2014,2015 HiSilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 compatible = "hisilicon,hip05-d02"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 psci { 17 compatible = "arm,psci-0.2"; 18 method = "smc"; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 cluster2 { 55 core0 { 56 cpu = <&cpu8>; 57 }; 58 core1 { 59 cpu = <&cpu9>; 60 }; 61 core2 { 62 cpu = <&cpu10>; 63 }; 64 core3 { 65 cpu = <&cpu11>; 66 }; 67 }; 68 cluster3 { 69 core0 { 70 cpu = <&cpu12>; 71 }; 72 core1 { 73 cpu = <&cpu13>; 74 }; 75 core2 { 76 cpu = <&cpu14>; 77 }; 78 core3 { 79 cpu = <&cpu15>; 80 }; 81 }; 82 }; 83 84 cpu0: cpu@20000 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a57"; 87 reg = <0x20000>; 88 enable-method = "psci"; 89 next-level-cache = <&cluster0_l2>; 90 }; 91 92 cpu1: cpu@20001 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a57"; 95 reg = <0x20001>; 96 enable-method = "psci"; 97 next-level-cache = <&cluster0_l2>; 98 }; 99 100 cpu2: cpu@20002 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a57"; 103 reg = <0x20002>; 104 enable-method = "psci"; 105 next-level-cache = <&cluster0_l2>; 106 }; 107 108 cpu3: cpu@20003 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a57"; 111 reg = <0x20003>; 112 enable-method = "psci"; 113 next-level-cache = <&cluster0_l2>; 114 }; 115 116 cpu4: cpu@20100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a57"; 119 reg = <0x20100>; 120 enable-method = "psci"; 121 next-level-cache = <&cluster1_l2>; 122 }; 123 124 cpu5: cpu@20101 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a57"; 127 reg = <0x20101>; 128 enable-method = "psci"; 129 next-level-cache = <&cluster1_l2>; 130 }; 131 132 cpu6: cpu@20102 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a57"; 135 reg = <0x20102>; 136 enable-method = "psci"; 137 next-level-cache = <&cluster1_l2>; 138 }; 139 140 cpu7: cpu@20103 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a57"; 143 reg = <0x20103>; 144 enable-method = "psci"; 145 next-level-cache = <&cluster1_l2>; 146 }; 147 148 cpu8: cpu@20200 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a57"; 151 reg = <0x20200>; 152 enable-method = "psci"; 153 next-level-cache = <&cluster2_l2>; 154 }; 155 156 cpu9: cpu@20201 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a57"; 159 reg = <0x20201>; 160 enable-method = "psci"; 161 next-level-cache = <&cluster2_l2>; 162 }; 163 164 cpu10: cpu@20202 { 165 device_type = "cpu"; 166 compatible = "arm,cortex-a57"; 167 reg = <0x20202>; 168 enable-method = "psci"; 169 next-level-cache = <&cluster2_l2>; 170 }; 171 172 cpu11: cpu@20203 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a57"; 175 reg = <0x20203>; 176 enable-method = "psci"; 177 next-level-cache = <&cluster2_l2>; 178 }; 179 180 cpu12: cpu@20300 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a57"; 183 reg = <0x20300>; 184 enable-method = "psci"; 185 next-level-cache = <&cluster3_l2>; 186 }; 187 188 cpu13: cpu@20301 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a57"; 191 reg = <0x20301>; 192 enable-method = "psci"; 193 next-level-cache = <&cluster3_l2>; 194 }; 195 196 cpu14: cpu@20302 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a57"; 199 reg = <0x20302>; 200 enable-method = "psci"; 201 next-level-cache = <&cluster3_l2>; 202 }; 203 204 cpu15: cpu@20303 { 205 device_type = "cpu"; 206 compatible = "arm,cortex-a57"; 207 reg = <0x20303>; 208 enable-method = "psci"; 209 next-level-cache = <&cluster3_l2>; 210 }; 211 212 cluster0_l2: l2-cache0 { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 }; 217 218 cluster1_l2: l2-cache1 { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-unified; 222 }; 223 224 cluster2_l2: l2-cache2 { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 }; 229 230 cluster3_l2: l2-cache3 { 231 compatible = "cache"; 232 cache-level = <2>; 233 cache-unified; 234 }; 235 }; 236 237 gic: interrupt-controller@8d000000 { 238 compatible = "arm,gic-v3"; 239 #interrupt-cells = <3>; 240 #address-cells = <2>; 241 #size-cells = <2>; 242 ranges; 243 interrupt-controller; 244 #redistributor-regions = <1>; 245 redistributor-stride = <0x0 0x30000>; 246 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ 247 <0x0 0x8d100000 0 0x300000>, /* GICR */ 248 <0x0 0xfe000000 0 0x10000>, /* GICC */ 249 <0x0 0xfe010000 0 0x10000>, /* GICH */ 250 <0x0 0xfe020000 0 0x10000>; /* GICV */ 251 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 252 253 its_peri: msi-controller@8c000000 { 254 compatible = "arm,gic-v3-its"; 255 msi-controller; 256 #msi-cells = <1>; 257 reg = <0x0 0x8c000000 0x0 0x40000>; 258 }; 259 260 its_m3: msi-controller@a3000000 { 261 compatible = "arm,gic-v3-its"; 262 msi-controller; 263 #msi-cells = <1>; 264 reg = <0x0 0xa3000000 0x0 0x40000>; 265 }; 266 267 its_pcie: msi-controller@b7000000 { 268 compatible = "arm,gic-v3-its"; 269 msi-controller; 270 #msi-cells = <1>; 271 reg = <0x0 0xb7000000 0x0 0x40000>; 272 }; 273 274 its_dsa: msi-controller@c6000000 { 275 compatible = "arm,gic-v3-its"; 276 msi-controller; 277 #msi-cells = <1>; 278 reg = <0x0 0xc6000000 0x0 0x40000>; 279 }; 280 }; 281 282 timer { 283 compatible = "arm,armv8-timer"; 284 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 285 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 286 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 287 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 288 }; 289 290 pmu { 291 compatible = "arm,cortex-a57-pmu"; 292 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 293 }; 294 295 soc { 296 compatible = "simple-bus"; 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 refclk200mhz: refclk200mhz { 302 compatible = "fixed-clock"; 303 #clock-cells = <0>; 304 clock-frequency = <200000000>; 305 }; 306 307 uart0: serial@80300000 { 308 compatible = "snps,dw-apb-uart"; 309 reg = <0x0 0x80300000 0x0 0x10000>; 310 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&refclk200mhz>, <&refclk200mhz>; 312 clock-names = "baudclk", "apb_pclk"; 313 reg-shift = <2>; 314 reg-io-width = <4>; 315 status = "disabled"; 316 }; 317 318 uart1: serial@80310000 { 319 compatible = "snps,dw-apb-uart"; 320 reg = <0x0 0x80310000 0x0 0x10000>; 321 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&refclk200mhz>, <&refclk200mhz>; 323 clock-names = "baudclk", "apb_pclk"; 324 reg-shift = <2>; 325 reg-io-width = <4>; 326 status = "disabled"; 327 }; 328 329 lbc: local-bus@80380000 { 330 compatible = "hisilicon,hisi-localbus", "simple-bus"; 331 reg = <0x0 0x80380000 0x0 0x10000>; 332 status = "disabled"; 333 }; 334 335 peri_gpio0: gpio@802e0000 { 336 #address-cells = <1>; 337 #size-cells = <0>; 338 compatible = "snps,dw-apb-gpio"; 339 reg = <0x0 0x802e0000 0x0 0x10000>; 340 status = "disabled"; 341 342 porta: gpio-controller@0 { 343 compatible = "snps,dw-apb-gpio-port"; 344 gpio-controller; 345 #gpio-cells = <2>; 346 ngpios = <32>; 347 reg = <0>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 351 }; 352 }; 353 354 peri_gpio1: gpio@802f0000 { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 compatible = "snps,dw-apb-gpio"; 358 reg = <0x0 0x802f0000 0x0 0x10000>; 359 status = "disabled"; 360 361 portb: gpio-controller@0 { 362 compatible = "snps,dw-apb-gpio-port"; 363 gpio-controller; 364 #gpio-cells = <2>; 365 ngpios = <32>; 366 reg = <0>; 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; 370 }; 371 }; 372 }; 373}; 374