1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Pinctrl dts file for HiSilicon HiKey970 development board 4 */ 5 6#include <dt-bindings/pinctrl/hisi.h> 7 8/ { 9 soc { 10 range: gpio-range { 11 #pinctrl-single,gpio-range-cells = <3>; 12 }; 13 14 pmx0: pinmux@e896c000 { 15 compatible = "pinctrl-single"; 16 reg = <0x0 0xe896c000 0x0 0x72c>; 17 #pinctrl-cells = <1>; 18 #gpio-range-cells = <0x3>; 19 pinctrl-single,register-width = <0x20>; 20 pinctrl-single,function-mask = <0x7>; 21 /* pin base, nr pins & gpio function */ 22 pinctrl-single,gpio-range = <&range 0 82 0>; 23 24 uart0_pmx_func: uart0_pmx_func { 25 pinctrl-single,pins = < 26 0x054 MUX_M2 /* UART0_RXD */ 27 0x058 MUX_M2 /* UART0_TXD */ 28 >; 29 }; 30 31 uart2_pmx_func: uart2_pmx_func { 32 pinctrl-single,pins = < 33 0x700 MUX_M2 /* UART2_CTS_N */ 34 0x704 MUX_M2 /* UART2_RTS_N */ 35 0x708 MUX_M2 /* UART2_RXD */ 36 0x70c MUX_M2 /* UART2_TXD */ 37 >; 38 }; 39 40 uart3_pmx_func: uart3_pmx_func { 41 pinctrl-single,pins = < 42 0x064 MUX_M1 /* UART3_CTS_N */ 43 0x068 MUX_M1 /* UART3_RTS_N */ 44 0x06c MUX_M1 /* UART3_RXD */ 45 0x070 MUX_M1 /* UART3_TXD */ 46 >; 47 }; 48 49 uart4_pmx_func: uart4_pmx_func { 50 pinctrl-single,pins = < 51 0x074 MUX_M1 /* UART4_CTS_N */ 52 0x078 MUX_M1 /* UART4_RTS_N */ 53 0x07c MUX_M1 /* UART4_RXD */ 54 0x080 MUX_M1 /* UART4_TXD */ 55 >; 56 }; 57 58 uart6_pmx_func: uart6_pmx_func { 59 pinctrl-single,pins = < 60 0x05c MUX_M1 /* UART6_RXD */ 61 0x060 MUX_M1 /* UART6_TXD */ 62 >; 63 }; 64 }; 65 66 pmx2: pinmux@e896c800 { 67 compatible = "pinconf-single"; 68 reg = <0x0 0xe896c800 0x0 0x72c>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <0x20>; 71 72 uart0_cfg_func: uart0_cfg_func { 73 pinctrl-single,pins = < 74 0x058 0x0 /* UART0_RXD */ 75 0x05c 0x0 /* UART0_TXD */ 76 >; 77 pinctrl-single,bias-pulldown = < 78 PULL_DIS 79 PULL_DOWN 80 PULL_DIS 81 PULL_DOWN 82 >; 83 pinctrl-single,bias-pullup = < 84 PULL_DIS 85 PULL_UP 86 PULL_DIS 87 PULL_UP 88 >; 89 pinctrl-single,drive-strength = < 90 DRIVE7_04MA DRIVE6_MASK 91 >; 92 }; 93 94 uart2_cfg_func: uart2_cfg_func { 95 pinctrl-single,pins = < 96 0x700 0x0 /* UART2_CTS_N */ 97 0x704 0x0 /* UART2_RTS_N */ 98 0x708 0x0 /* UART2_RXD */ 99 0x70c 0x0 /* UART2_TXD */ 100 >; 101 pinctrl-single,bias-pulldown = < 102 PULL_DIS 103 PULL_DOWN 104 PULL_DIS 105 PULL_DOWN 106 >; 107 pinctrl-single,bias-pullup = < 108 PULL_DIS 109 PULL_UP 110 PULL_DIS 111 PULL_UP 112 >; 113 pinctrl-single,drive-strength = < 114 DRIVE7_04MA DRIVE6_MASK 115 >; 116 }; 117 118 uart3_cfg_func: uart3_cfg_func { 119 pinctrl-single,pins = < 120 0x068 0x0 /* UART3_CTS_N */ 121 0x06c 0x0 /* UART3_RTS_N */ 122 0x070 0x0 /* UART3_RXD */ 123 0x074 0x0 /* UART3_TXD */ 124 >; 125 pinctrl-single,bias-pulldown = < 126 PULL_DIS 127 PULL_DOWN 128 PULL_DIS 129 PULL_DOWN 130 >; 131 pinctrl-single,bias-pullup = < 132 PULL_DIS 133 PULL_UP 134 PULL_DIS 135 PULL_UP 136 >; 137 pinctrl-single,drive-strength = < 138 DRIVE7_04MA DRIVE6_MASK 139 >; 140 }; 141 142 uart4_cfg_func: uart4_cfg_func { 143 pinctrl-single,pins = < 144 0x078 0x0 /* UART4_CTS_N */ 145 0x07c 0x0 /* UART4_RTS_N */ 146 0x080 0x0 /* UART4_RXD */ 147 0x084 0x0 /* UART4_TXD */ 148 >; 149 pinctrl-single,bias-pulldown = < 150 PULL_DIS 151 PULL_DOWN 152 PULL_DIS 153 PULL_DOWN 154 >; 155 pinctrl-single,bias-pullup = < 156 PULL_DIS 157 PULL_UP 158 PULL_DIS 159 PULL_UP 160 >; 161 pinctrl-single,drive-strength = < 162 DRIVE7_04MA DRIVE6_MASK 163 >; 164 }; 165 166 uart6_cfg_func: uart6_cfg_func { 167 pinctrl-single,pins = < 168 0x060 0x0 /* UART6_RXD */ 169 0x064 0x0 /* UART6_TXD */ 170 >; 171 pinctrl-single,bias-pulldown = < 172 PULL_DIS 173 PULL_DOWN 174 PULL_DIS 175 PULL_DOWN 176 >; 177 pinctrl-single,bias-pullup = < 178 PULL_DIS 179 PULL_UP 180 PULL_DIS 181 PULL_UP 182 >; 183 pinctrl-single,drive-strength = < 184 DRIVE7_02MA DRIVE6_MASK 185 >; 186 }; 187 }; 188 189 pmx5: pinmux@fc182000 { 190 compatible = "pinctrl-single"; 191 reg = <0x0 0xfc182000 0x0 0x028>; 192 #gpio-range-cells = <3>; 193 #pinctrl-cells = <1>; 194 pinctrl-single,register-width = <0x20>; 195 pinctrl-single,function-mask = <0x7>; 196 /* pin base, nr pins & gpio function */ 197 pinctrl-single,gpio-range = <&range 0 10 0>; 198 199 sdio_pmx_func: sdio_pmx_func { 200 pinctrl-single,pins = < 201 0x000 MUX_M1 /* SDIO_CLK */ 202 0x004 MUX_M1 /* SDIO_CMD */ 203 0x008 MUX_M1 /* SDIO_DATA0 */ 204 0x00c MUX_M1 /* SDIO_DATA1 */ 205 0x010 MUX_M1 /* SDIO_DATA2 */ 206 0x014 MUX_M1 /* SDIO_DATA3 */ 207 >; 208 }; 209 }; 210 211 pmx6: pinmux@fc182800 { 212 compatible = "pinconf-single"; 213 reg = <0x0 0xfc182800 0x0 0x028>; 214 #pinctrl-cells = <1>; 215 pinctrl-single,register-width = <0x20>; 216 217 sdio_clk_cfg_func: sdio_clk_cfg_func { 218 pinctrl-single,pins = < 219 0x000 0x0 /* SDIO_CLK */ 220 >; 221 pinctrl-single,bias-pulldown = < 222 PULL_DIS 223 PULL_DOWN 224 PULL_DIS 225 PULL_DOWN 226 >; 227 pinctrl-single,bias-pullup = < 228 PULL_DIS 229 PULL_UP 230 PULL_DIS 231 PULL_UP 232 >; 233 pinctrl-single,drive-strength = < 234 DRIVE6_32MA DRIVE6_MASK 235 >; 236 }; 237 238 sdio_cfg_func: sdio_cfg_func { 239 pinctrl-single,pins = < 240 0x004 0x0 /* SDIO_CMD */ 241 0x008 0x0 /* SDIO_DATA0 */ 242 0x00c 0x0 /* SDIO_DATA1 */ 243 0x010 0x0 /* SDIO_DATA2 */ 244 0x014 0x0 /* SDIO_DATA3 */ 245 >; 246 pinctrl-single,bias-pulldown = < 247 PULL_DIS 248 PULL_DOWN 249 PULL_DIS 250 PULL_DOWN 251 >; 252 pinctrl-single,bias-pullup = < 253 PULL_UP 254 PULL_UP 255 PULL_DIS 256 PULL_UP 257 >; 258 pinctrl-single,drive-strength = < 259 DRIVE6_19MA DRIVE6_MASK 260 >; 261 }; 262 }; 263 264 pmx7: pinmux@ff37e000 { 265 compatible = "pinctrl-single"; 266 reg = <0x0 0xff37e000 0x0 0x030>; 267 #gpio-range-cells = <3>; 268 #pinctrl-cells = <1>; 269 pinctrl-single,register-width = <0x20>; 270 pinctrl-single,function-mask = <7>; 271 /* pin base, nr pins & gpio function */ 272 pinctrl-single,gpio-range = <&range 0 12 0>; 273 274 sd_pmx_func: sd_pmx_func { 275 pinctrl-single,pins = < 276 0x000 MUX_M1 /* SD_CLK */ 277 0x004 MUX_M1 /* SD_CMD */ 278 0x008 MUX_M1 /* SD_DATA0 */ 279 0x00c MUX_M1 /* SD_DATA1 */ 280 0x010 MUX_M1 /* SD_DATA2 */ 281 0x014 MUX_M1 /* SD_DATA3 */ 282 >; 283 }; 284 }; 285 286 pmx8: pinmux@ff37e800 { 287 compatible = "pinconf-single"; 288 reg = <0x0 0xff37e800 0x0 0x030>; 289 #pinctrl-cells = <1>; 290 pinctrl-single,register-width = <0x20>; 291 292 sd_clk_cfg_func: sd_clk_cfg_func { 293 pinctrl-single,pins = < 294 0x000 0x0 /* SD_CLK */ 295 >; 296 pinctrl-single,bias-pulldown = < 297 PULL_DIS 298 PULL_DOWN 299 PULL_DIS 300 PULL_DOWN 301 >; 302 pinctrl-single,bias-pullup = < 303 PULL_DIS 304 PULL_UP 305 PULL_DIS 306 PULL_UP 307 >; 308 pinctrl-single,drive-strength = < 309 DRIVE6_32MA 310 DRIVE6_MASK 311 >; 312 }; 313 314 sd_cfg_func: sd_cfg_func { 315 pinctrl-single,pins = < 316 0x004 0x0 /* SD_CMD */ 317 0x008 0x0 /* SD_DATA0 */ 318 0x00c 0x0 /* SD_DATA1 */ 319 0x010 0x0 /* SD_DATA2 */ 320 0x014 0x0 /* SD_DATA3 */ 321 >; 322 pinctrl-single,bias-pulldown = < 323 PULL_DIS 324 PULL_DOWN 325 PULL_DIS 326 PULL_DOWN 327 >; 328 pinctrl-single,bias-pullup = < 329 PULL_UP 330 PULL_UP 331 PULL_DIS 332 PULL_UP 333 >; 334 pinctrl-single,drive-strength = < 335 DRIVE6_19MA 336 DRIVE6_MASK 337 >; 338 }; 339 }; 340 341 pmx1: pinmux@fff11000 { 342 compatible = "pinctrl-single"; 343 reg = <0x0 0xfff11000 0x0 0x73c>; 344 #gpio-range-cells = <0x3>; 345 #pinctrl-cells = <1>; 346 pinctrl-single,register-width = <0x20>; 347 pinctrl-single,function-mask = <0x7>; 348 /* pin base, nr pins & gpio function */ 349 pinctrl-single,gpio-range = <&range 0 46 0>; 350 }; 351 352 pmx16: pinmux@fff11800 { 353 compatible = "pinconf-single"; 354 reg = <0x0 0xfff11800 0x0 0x73c>; 355 #pinctrl-cells = <1>; 356 pinctrl-single,register-width = <0x20>; 357 }; 358 }; 359}; 360