1// SPDX-License-Identifier: GPL-2.0 2/* 3 * pinctrl dts fils for Hislicon HiKey development board 4 * 5 */ 6#include <dt-bindings/pinctrl/hisi.h> 7 8/ { 9 soc { 10 pmx0: pinmux@f7010000 { 11 pinctrl-names = "default"; 12 pinctrl-0 = < 13 &boot_sel_pmx_func 14 &hkadc_ssi_pmx_func 15 &codec_clk_pmx_func 16 &pwm_in_pmx_func 17 &bl_pwm_pmx_func 18 >; 19 20 boot_sel_pmx_func: boot_sel_pmx_func { 21 pinctrl-single,pins = < 22 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */ 23 >; 24 }; 25 26 emmc_pmx_func: emmc_pmx_func { 27 pinctrl-single,pins = < 28 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */ 29 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */ 30 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */ 31 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */ 32 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */ 33 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */ 34 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */ 35 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */ 36 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */ 37 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */ 38 >; 39 }; 40 41 sd_pmx_func: sd_pmx_func { 42 pinctrl-single,pins = < 43 0xc MUX_M0 /* SD_CLK (IOMG003) */ 44 0x10 MUX_M0 /* SD_CMD (IOMG004) */ 45 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */ 46 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */ 47 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */ 48 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */ 49 >; 50 }; 51 sd_pmx_idle: sd_pmx_idle { 52 pinctrl-single,pins = < 53 0xc MUX_M1 /* SD_CLK (IOMG003) */ 54 0x10 MUX_M1 /* SD_CMD (IOMG004) */ 55 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */ 56 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */ 57 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */ 58 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */ 59 >; 60 }; 61 62 sdio_pmx_func: sdio_pmx_func { 63 pinctrl-single,pins = < 64 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */ 65 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */ 66 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */ 67 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */ 68 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */ 69 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */ 70 >; 71 }; 72 sdio_pmx_idle: sdio_pmx_idle { 73 pinctrl-single,pins = < 74 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */ 75 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */ 76 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */ 77 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */ 78 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */ 79 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */ 80 >; 81 }; 82 83 isp_pmx_func: isp_pmx_func { 84 pinctrl-single,pins = < 85 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */ 86 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */ 87 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */ 88 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */ 89 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */ 90 0x38 MUX_M1 /* ISP_PWM (IOMG014) */ 91 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */ 92 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */ 93 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */ 94 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */ 95 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */ 96 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */ 97 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */ 98 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */ 99 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */ 100 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */ 101 >; 102 }; 103 104 hkadc_ssi_pmx_func: hkadc_ssi_pmx_func { 105 pinctrl-single,pins = < 106 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */ 107 >; 108 }; 109 110 codec_clk_pmx_func: codec_clk_pmx_func { 111 pinctrl-single,pins = < 112 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */ 113 >; 114 }; 115 116 codec_pmx_func: codec_pmx_func { 117 pinctrl-single,pins = < 118 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */ 119 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */ 120 0x78 MUX_M0 /* CODEC_DI (IOMG030) */ 121 0x7c MUX_M0 /* CODEC_DO (IOMG031) */ 122 >; 123 }; 124 125 fm_pmx_func: fm_pmx_func { 126 pinctrl-single,pins = < 127 0x80 MUX_M1 /* FM_XCLK (IOMG032) */ 128 0x84 MUX_M1 /* FM_XFS (IOMG033) */ 129 0x88 MUX_M1 /* FM_DI (IOMG034) */ 130 0x8c MUX_M1 /* FM_DO (IOMG035) */ 131 >; 132 }; 133 134 bt_pmx_func: bt_pmx_func { 135 pinctrl-single,pins = < 136 0x90 MUX_M0 /* BT_XCLK (IOMG036) */ 137 0x94 MUX_M0 /* BT_XFS (IOMG037) */ 138 0x98 MUX_M0 /* BT_DI (IOMG038) */ 139 0x9c MUX_M0 /* BT_DO (IOMG039) */ 140 >; 141 }; 142 143 pwm_in_pmx_func: pwm_in_pmx_func { 144 pinctrl-single,pins = < 145 0xb8 MUX_M1 /* PWM_IN (IOMG046) */ 146 >; 147 }; 148 149 bl_pwm_pmx_func: bl_pwm_pmx_func { 150 pinctrl-single,pins = < 151 0xbc MUX_M1 /* BL_PWM (IOMG047) */ 152 >; 153 }; 154 155 uart0_pmx_func: uart0_pmx_func { 156 pinctrl-single,pins = < 157 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */ 158 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */ 159 >; 160 }; 161 162 uart1_pmx_func: uart1_pmx_func { 163 pinctrl-single,pins = < 164 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */ 165 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */ 166 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */ 167 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */ 168 >; 169 }; 170 171 uart2_pmx_func: uart2_pmx_func { 172 pinctrl-single,pins = < 173 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */ 174 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */ 175 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */ 176 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */ 177 >; 178 }; 179 180 uart3_pmx_func: uart3_pmx_func { 181 pinctrl-single,pins = < 182 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */ 183 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */ 184 0x188 MUX_M1 /* UART3_RXD (IOMG098) */ 185 0x18c MUX_M1 /* UART3_TXD (IOMG099) */ 186 >; 187 }; 188 189 uart4_pmx_func: uart4_pmx_func { 190 pinctrl-single,pins = < 191 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */ 192 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */ 193 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */ 194 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */ 195 >; 196 }; 197 198 uart5_pmx_func: uart5_pmx_func { 199 pinctrl-single,pins = < 200 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */ 201 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */ 202 >; 203 }; 204 205 i2c0_pmx_func: i2c0_pmx_func { 206 pinctrl-single,pins = < 207 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */ 208 0xec MUX_M0 /* I2C0_SDA (IOMG059) */ 209 >; 210 }; 211 212 i2c1_pmx_func: i2c1_pmx_func { 213 pinctrl-single,pins = < 214 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */ 215 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */ 216 >; 217 }; 218 219 i2c2_pmx_func: i2c2_pmx_func { 220 pinctrl-single,pins = < 221 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */ 222 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */ 223 >; 224 }; 225 226 spi0_pmx_func: spi0_pmx_func { 227 pinctrl-single,pins = < 228 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */ 229 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */ 230 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */ 231 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */ 232 >; 233 }; 234 }; 235 236 pmx1: pinmux@f7010800 { 237 238 pinctrl-names = "default"; 239 pinctrl-0 = < 240 &boot_sel_cfg_func 241 &hkadc_ssi_cfg_func 242 &codec_clk_cfg_func 243 &pwm_in_cfg_func 244 &bl_pwm_cfg_func 245 >; 246 247 boot_sel_cfg_func: boot_sel_cfg_func { 248 pinctrl-single,pins = < 249 0x0 0x0 /* BOOT_SEL (IOCFG000) */ 250 >; 251 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 252 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; 253 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 254 }; 255 256 hkadc_ssi_cfg_func: hkadc_ssi_cfg_func { 257 pinctrl-single,pins = < 258 0x6c 0x0 /* HKADC_SSI (IOCFG027) */ 259 >; 260 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 261 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 262 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 263 }; 264 265 emmc_clk_cfg_func: emmc_clk_cfg_func { 266 pinctrl-single,pins = < 267 0x104 0x0 /* EMMC_CLK (IOCFG065) */ 268 >; 269 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 270 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 271 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; 272 }; 273 274 emmc_cfg_func: emmc_cfg_func { 275 pinctrl-single,pins = < 276 0x108 0x0 /* EMMC_CMD (IOCFG066) */ 277 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */ 278 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */ 279 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */ 280 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */ 281 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */ 282 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */ 283 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */ 284 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */ 285 >; 286 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 287 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; 288 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; 289 }; 290 291 emmc_rst_cfg_func: emmc_rst_cfg_func { 292 pinctrl-single,pins = < 293 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */ 294 >; 295 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 296 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 297 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; 298 }; 299 300 sd_clk_cfg_func: sd_clk_cfg_func { 301 pinctrl-single,pins = < 302 0xc 0x0 /* SD_CLK (IOCFG003) */ 303 >; 304 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 305 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 306 pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>; 307 }; 308 sd_clk_cfg_idle: sd_clk_cfg_idle { 309 pinctrl-single,pins = < 310 0xc 0x0 /* SD_CLK (IOCFG003) */ 311 >; 312 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 313 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 314 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 315 }; 316 317 sd_cfg_func: sd_cfg_func { 318 pinctrl-single,pins = < 319 0x10 0x0 /* SD_CMD (IOCFG004) */ 320 0x14 0x0 /* SD_DATA0 (IOCFG005) */ 321 0x18 0x0 /* SD_DATA1 (IOCFG006) */ 322 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ 323 0x20 0x0 /* SD_DATA3 (IOCFG008) */ 324 >; 325 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 326 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 327 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; 328 }; 329 sd_cfg_idle: sd_cfg_idle { 330 pinctrl-single,pins = < 331 0x10 0x0 /* SD_CMD (IOCFG004) */ 332 0x14 0x0 /* SD_DATA0 (IOCFG005) */ 333 0x18 0x0 /* SD_DATA1 (IOCFG006) */ 334 0x1c 0x0 /* SD_DATA2 (IOCFG007) */ 335 0x20 0x0 /* SD_DATA3 (IOCFG008) */ 336 >; 337 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 338 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 339 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 340 }; 341 342 sdio_clk_cfg_func: sdio_clk_cfg_func { 343 pinctrl-single,pins = < 344 0x134 0x0 /* SDIO_CLK (IOCFG077) */ 345 >; 346 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 347 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 348 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; 349 }; 350 sdio_clk_cfg_idle: sdio_clk_cfg_idle { 351 pinctrl-single,pins = < 352 0x134 0x0 /* SDIO_CLK (IOCFG077) */ 353 >; 354 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 355 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 356 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 357 }; 358 359 sdio_cfg_func: sdio_cfg_func { 360 pinctrl-single,pins = < 361 0x138 0x0 /* SDIO_CMD (IOCFG078) */ 362 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ 363 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ 364 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ 365 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ 366 >; 367 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 368 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; 369 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; 370 }; 371 sdio_cfg_idle: sdio_cfg_idle { 372 pinctrl-single,pins = < 373 0x138 0x0 /* SDIO_CMD (IOCFG078) */ 374 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */ 375 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */ 376 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */ 377 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */ 378 >; 379 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 380 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; 381 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 382 }; 383 384 isp_cfg_func1: isp_cfg_func1 { 385 pinctrl-single,pins = < 386 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */ 387 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */ 388 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */ 389 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ 390 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ 391 0x3c 0x0 /* ISP_PWM (IOCFG015) */ 392 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */ 393 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */ 394 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */ 395 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */ 396 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */ 397 0x58 0x0 /* ISP_SDA0 (IOCFG022) */ 398 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */ 399 0x60 0x0 /* ISP_SDA1 (IOCFG024) */ 400 0x64 0x0 /* ISP_SCL1 (IOCFG025) */ 401 >; 402 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 403 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 404 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 405 }; 406 isp_cfg_idle1: isp_cfg_idle1 { 407 pinctrl-single,pins = < 408 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */ 409 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */ 410 >; 411 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 412 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 413 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 414 }; 415 416 isp_cfg_func2: isp_cfg_func2 { 417 pinctrl-single,pins = < 418 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */ 419 >; 420 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 421 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 422 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 423 }; 424 425 codec_clk_cfg_func: codec_clk_cfg_func { 426 pinctrl-single,pins = < 427 0x70 0x0 /* CODEC_CLK (IOCFG028) */ 428 >; 429 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 430 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 431 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; 432 }; 433 codec_clk_cfg_idle: codec_clk_cfg_idle { 434 pinctrl-single,pins = < 435 0x70 0x0 /* CODEC_CLK (IOCFG028) */ 436 >; 437 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 438 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 439 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 440 }; 441 442 codec_cfg_func1: codec_cfg_func1 { 443 pinctrl-single,pins = < 444 0x74 0x0 /* DMIC_CLK (IOCFG029) */ 445 >; 446 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 447 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 448 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 449 }; 450 451 codec_cfg_func2: codec_cfg_func2 { 452 pinctrl-single,pins = < 453 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ 454 0x7c 0x0 /* CODEC_DI (IOCFG031) */ 455 0x80 0x0 /* CODEC_DO (IOCFG032) */ 456 >; 457 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 458 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 459 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; 460 }; 461 codec_cfg_idle2: codec_cfg_idle2 { 462 pinctrl-single,pins = < 463 0x78 0x0 /* CODEC_SYNC (IOCFG030) */ 464 0x7c 0x0 /* CODEC_DI (IOCFG031) */ 465 0x80 0x0 /* CODEC_DO (IOCFG032) */ 466 >; 467 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 468 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 469 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 470 }; 471 472 fm_cfg_func: fm_cfg_func { 473 pinctrl-single,pins = < 474 0x84 0x0 /* FM_XCLK (IOCFG033) */ 475 0x88 0x0 /* FM_XFS (IOCFG034) */ 476 0x8c 0x0 /* FM_DI (IOCFG035) */ 477 0x90 0x0 /* FM_DO (IOCFG036) */ 478 >; 479 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 480 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 481 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 482 }; 483 484 bt_cfg_func: bt_cfg_func { 485 pinctrl-single,pins = < 486 0x94 0x0 /* BT_XCLK (IOCFG037) */ 487 0x98 0x0 /* BT_XFS (IOCFG038) */ 488 0x9c 0x0 /* BT_DI (IOCFG039) */ 489 0xa0 0x0 /* BT_DO (IOCFG040) */ 490 >; 491 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 492 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 493 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 494 }; 495 bt_cfg_idle: bt_cfg_idle { 496 pinctrl-single,pins = < 497 0x94 0x0 /* BT_XCLK (IOCFG037) */ 498 0x98 0x0 /* BT_XFS (IOCFG038) */ 499 0x9c 0x0 /* BT_DI (IOCFG039) */ 500 0xa0 0x0 /* BT_DO (IOCFG040) */ 501 >; 502 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 503 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 504 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 505 }; 506 507 pwm_in_cfg_func: pwm_in_cfg_func { 508 pinctrl-single,pins = < 509 0xbc 0x0 /* PWM_IN (IOCFG047) */ 510 >; 511 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 512 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 513 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 514 }; 515 516 bl_pwm_cfg_func: bl_pwm_cfg_func { 517 pinctrl-single,pins = < 518 0xc0 0x0 /* BL_PWM (IOCFG048) */ 519 >; 520 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 521 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 522 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 523 }; 524 525 uart0_cfg_func1: uart0_cfg_func1 { 526 pinctrl-single,pins = < 527 0xc4 0x0 /* UART0_RXD (IOCFG049) */ 528 >; 529 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 530 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; 531 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 532 }; 533 534 uart0_cfg_func2: uart0_cfg_func2 { 535 pinctrl-single,pins = < 536 0xc8 0x0 /* UART0_TXD (IOCFG050) */ 537 >; 538 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 539 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 540 pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>; 541 }; 542 543 uart1_cfg_func1: uart1_cfg_func1 { 544 pinctrl-single,pins = < 545 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */ 546 0xd4 0x0 /* UART1_RXD (IOCFG053) */ 547 >; 548 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 549 pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>; 550 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 551 }; 552 553 uart1_cfg_func2: uart1_cfg_func2 { 554 pinctrl-single,pins = < 555 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */ 556 0xd8 0x0 /* UART1_TXD (IOCFG054) */ 557 >; 558 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 559 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 560 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 561 }; 562 563 uart2_cfg_func: uart2_cfg_func { 564 pinctrl-single,pins = < 565 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */ 566 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */ 567 0xe4 0x0 /* UART2_RXD (IOCFG057) */ 568 0xe8 0x0 /* UART2_TXD (IOCFG058) */ 569 >; 570 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 571 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 572 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 573 }; 574 575 uart3_cfg_func: uart3_cfg_func { 576 pinctrl-single,pins = < 577 0x190 0x0 /* UART3_CTS_N (IOCFG100) */ 578 0x194 0x0 /* UART3_RTS_N (IOCFG101) */ 579 0x198 0x0 /* UART3_RXD (IOCFG102) */ 580 0x19c 0x0 /* UART3_TXD (IOCFG103) */ 581 >; 582 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 583 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 584 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 585 }; 586 587 uart4_cfg_func: uart4_cfg_func { 588 pinctrl-single,pins = < 589 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */ 590 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */ 591 0x1e8 0x0 /* UART4_RXD (IOCFG122) */ 592 0x1ec 0x0 /* UART4_TXD (IOCFG123) */ 593 >; 594 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 595 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 596 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 597 }; 598 599 uart5_cfg_func: uart5_cfg_func { 600 pinctrl-single,pins = < 601 0x1d8 0x0 /* UART4_RXD (IOCFG118) */ 602 0x1dc 0x0 /* UART4_TXD (IOCFG119) */ 603 >; 604 pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>; 605 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 606 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 607 }; 608 609 i2c0_cfg_func: i2c0_cfg_func { 610 pinctrl-single,pins = < 611 0xec 0x0 /* I2C0_SCL (IOCFG059) */ 612 0xf0 0x0 /* I2C0_SDA (IOCFG060) */ 613 >; 614 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 615 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 616 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 617 }; 618 619 i2c1_cfg_func: i2c1_cfg_func { 620 pinctrl-single,pins = < 621 0xf4 0x0 /* I2C1_SCL (IOCFG061) */ 622 0xf8 0x0 /* I2C1_SDA (IOCFG062) */ 623 >; 624 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 625 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 626 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 627 }; 628 629 i2c2_cfg_func: i2c2_cfg_func { 630 pinctrl-single,pins = < 631 0xfc 0x0 /* I2C2_SCL (IOCFG063) */ 632 0x100 0x0 /* I2C2_SDA (IOCFG064) */ 633 >; 634 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 635 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 636 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 637 }; 638 639 spi0_cfg_func: spi0_cfg_func { 640 pinctrl-single,pins = < 641 0x1b0 0x0 /* SPI0_DI (IOCFG108) */ 642 0x1b4 0x0 /* SPI0_DO (IOCFG109) */ 643 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */ 644 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */ 645 >; 646 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 647 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 648 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 649 }; 650 }; 651 652 pmx2: pinmux@f8001800 { 653 654 pinctrl-names = "default"; 655 pinctrl-0 = < 656 &rstout_n_cfg_func 657 >; 658 659 rstout_n_cfg_func: rstout_n_cfg_func { 660 pinctrl-single,pins = < 661 0x0 0x0 /* RSTOUT_N (IOCFG000) */ 662 >; 663 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 664 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 665 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 666 }; 667 668 pmu_peri_en_cfg_func: pmu_peri_en_cfg_func { 669 pinctrl-single,pins = < 670 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */ 671 >; 672 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 673 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 674 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 675 }; 676 677 sysclk0_en_cfg_func: sysclk0_en_cfg_func { 678 pinctrl-single,pins = < 679 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */ 680 >; 681 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 682 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 683 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 684 }; 685 686 jtag_tdo_cfg_func: jtag_tdo_cfg_func { 687 pinctrl-single,pins = < 688 0xc 0x0 /* JTAG_TDO (IOCFG003) */ 689 >; 690 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 691 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 692 pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>; 693 }; 694 695 rf_reset_cfg_func: rf_reset_cfg_func { 696 pinctrl-single,pins = < 697 0x70 0x0 /* RF_RESET0 (IOCFG028) */ 698 0x74 0x0 /* RF_RESET1 (IOCFG029) */ 699 >; 700 pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>; 701 pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>; 702 pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>; 703 }; 704 }; 705 }; 706}; 707