1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2016-2018 NXP 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/memreserve/ 0x80000000 0x00010000; 10 11/ { 12 compatible = "fsl,s32v234"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 serial0 = &uart0; 19 serial1 = &uart1; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53"; 29 reg = <0x0 0x0>; 30 enable-method = "spin-table"; 31 cpu-release-addr = <0x0 0x80000000>; 32 next-level-cache = <&cluster0_l2_cache>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0 0x1>; 39 enable-method = "spin-table"; 40 cpu-release-addr = <0x0 0x80000000>; 41 next-level-cache = <&cluster0_l2_cache>; 42 }; 43 44 cpu2: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x100>; 48 enable-method = "spin-table"; 49 cpu-release-addr = <0x0 0x80000000>; 50 next-level-cache = <&cluster1_l2_cache>; 51 }; 52 53 cpu3: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x0 0x101>; 57 enable-method = "spin-table"; 58 cpu-release-addr = <0x0 0x80000000>; 59 next-level-cache = <&cluster1_l2_cache>; 60 }; 61 62 cluster0_l2_cache: l2-cache0 { 63 compatible = "cache"; 64 }; 65 66 cluster1_l2_cache: l2-cache1 { 67 compatible = "cache"; 68 }; 69 }; 70 71 timer { 72 compatible = "arm,armv8-timer"; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 74 IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 76 IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 78 IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 80 IRQ_TYPE_LEVEL_LOW)>; 81 /* clock-frequency might be modified by u-boot, depending on the 82 * chip version. 83 */ 84 clock-frequency = <10000000>; 85 }; 86 87 gic: interrupt-controller@7d001000 { 88 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 89 #interrupt-cells = <3>; 90 #address-cells = <0>; 91 interrupt-controller; 92 reg = <0 0x7d001000 0 0x1000>, 93 <0 0x7d002000 0 0x2000>, 94 <0 0x7d004000 0 0x2000>, 95 <0 0x7d006000 0 0x2000>; 96 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 97 IRQ_TYPE_LEVEL_HIGH)>; 98 }; 99 100 soc { 101 #address-cells = <2>; 102 #size-cells = <2>; 103 compatible = "simple-bus"; 104 interrupt-parent = <&gic>; 105 ranges; 106 107 aips0: bus@40000000 { 108 compatible = "simple-bus"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 interrupt-parent = <&gic>; 112 reg = <0x0 0x40000000 0x0 0x7d000>; 113 ranges; 114 115 uart0: serial@40053000 { 116 compatible = "fsl,s32v234-linflexuart"; 117 reg = <0x0 0x40053000 0x0 0x1000>; 118 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; 119 status = "disabled"; 120 }; 121 }; 122 123 aips1: bus@40080000 { 124 compatible = "simple-bus"; 125 #address-cells = <2>; 126 #size-cells = <2>; 127 interrupt-parent = <&gic>; 128 reg = <0x0 0x40080000 0x0 0x70000>; 129 ranges; 130 131 uart1: serial@400bc000 { 132 compatible = "fsl,s32v234-linflexuart"; 133 reg = <0x0 0x400bc000 0x0 0x1000>; 134 interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>; 135 status = "disabled"; 136 }; 137 }; 138 }; 139}; 140