1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * NXP S32G2 SoC family 4 * 5 * Copyright (c) 2021 SUSE LLC 6 * Copyright (c) 2017-2021 NXP 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "nxp,s32g2"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a53"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 next-level-cache = <&cluster0_l2>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x1>; 33 enable-method = "psci"; 34 next-level-cache = <&cluster0_l2>; 35 }; 36 37 cpu2: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 next-level-cache = <&cluster1_l2>; 43 }; 44 45 cpu3: cpu@101 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x101>; 49 enable-method = "psci"; 50 next-level-cache = <&cluster1_l2>; 51 }; 52 53 cluster0_l2: l2-cache0 { 54 compatible = "cache"; 55 cache-level = <2>; 56 }; 57 58 cluster1_l2: l2-cache1 { 59 compatible = "cache"; 60 cache-level = <2>; 61 }; 62 }; 63 64 pmu { 65 compatible = "arm,cortex-a53-pmu"; 66 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 67 }; 68 69 timer { 70 compatible = "arm,armv8-timer"; 71 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 72 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 73 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 74 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 75 }; 76 77 firmware { 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 }; 83 84 soc@0 { 85 compatible = "simple-bus"; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges = <0 0 0 0x80000000>; 89 90 uart0: serial@401c8000 { 91 compatible = "nxp,s32g2-linflexuart", 92 "fsl,s32v234-linflexuart"; 93 reg = <0x401c8000 0x3000>; 94 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 95 status = "disabled"; 96 }; 97 98 uart1: serial@401cc000 { 99 compatible = "nxp,s32g2-linflexuart", 100 "fsl,s32v234-linflexuart"; 101 reg = <0x401cc000 0x3000>; 102 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 103 status = "disabled"; 104 }; 105 106 uart2: serial@402bc000 { 107 compatible = "nxp,s32g2-linflexuart", 108 "fsl,s32v234-linflexuart"; 109 reg = <0x402bc000 0x3000>; 110 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 111 status = "disabled"; 112 }; 113 114 gic: interrupt-controller@50800000 { 115 compatible = "arm,gic-v3"; 116 reg = <0x50800000 0x10000>, 117 <0x50880000 0x80000>, 118 <0x50400000 0x2000>, 119 <0x50410000 0x2000>, 120 <0x50420000 0x2000>; 121 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 122 interrupt-controller; 123 #interrupt-cells = <3>; 124 }; 125 }; 126}; 127