1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * NXP S32G2 SoC family 4 * 5 * Copyright (c) 2021 SUSE LLC 6 * Copyright (c) 2017-2021 NXP 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "nxp,s32g2"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a53"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 next-level-cache = <&cluster0_l2>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x1>; 33 enable-method = "psci"; 34 next-level-cache = <&cluster0_l2>; 35 }; 36 37 cpu2: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 next-level-cache = <&cluster1_l2>; 43 }; 44 45 cpu3: cpu@101 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x101>; 49 enable-method = "psci"; 50 next-level-cache = <&cluster1_l2>; 51 }; 52 53 cluster0_l2: l2-cache0 { 54 compatible = "cache"; 55 }; 56 57 cluster1_l2: l2-cache1 { 58 compatible = "cache"; 59 }; 60 }; 61 62 pmu { 63 compatible = "arm,cortex-a53-pmu"; 64 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 65 }; 66 67 timer { 68 compatible = "arm,armv8-timer"; 69 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 70 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 71 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 72 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 73 }; 74 75 firmware { 76 psci { 77 compatible = "arm,psci-1.0"; 78 method = "smc"; 79 }; 80 }; 81 82 soc@0 { 83 compatible = "simple-bus"; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 ranges = <0 0 0 0x80000000>; 87 88 uart0: serial@401c8000 { 89 compatible = "nxp,s32g2-linflexuart", 90 "fsl,s32v234-linflexuart"; 91 reg = <0x401c8000 0x3000>; 92 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>; 93 status = "disabled"; 94 }; 95 96 uart1: serial@401cc000 { 97 compatible = "nxp,s32g2-linflexuart", 98 "fsl,s32v234-linflexuart"; 99 reg = <0x401cc000 0x3000>; 100 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>; 101 status = "disabled"; 102 }; 103 104 uart2: serial@402bc000 { 105 compatible = "nxp,s32g2-linflexuart", 106 "fsl,s32v234-linflexuart"; 107 reg = <0x402bc000 0x3000>; 108 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 109 status = "disabled"; 110 }; 111 112 gic: interrupt-controller@50800000 { 113 compatible = "arm,gic-v3"; 114 reg = <0x50800000 0x10000>, 115 <0x50880000 0x80000>, 116 <0x50400000 0x2000>, 117 <0x50410000 0x2000>, 118 <0x50420000 0x2000>; 119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 120 interrupt-controller; 121 #interrupt-cells = <3>; 122 }; 123 }; 124}; 125