1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 * Author: Alexander Stein 7 */ 8/dts-v1/; 9 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/pwm/pwm.h> 14 15#include "imx93-tqma9352.dtsi" 16 17/{ 18 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit"; 19 compatible = "tq,imx93-tqma9352-mba93xxca", 20 "tq,imx93-tqma9352", "fsl,imx93"; 21 chassis-type = "embedded"; 22 23 chosen { 24 stdout-path = &lpuart1; 25 }; 26 27 aliases { 28 eeprom0 = &eeprom0; 29 rtc0 = &pcf85063; 30 rtc1 = &bbnsm_rtc; 31 }; 32 33 backlight_lvds: backlight { 34 compatible = "pwm-backlight"; 35 pwms = <&tpm5 0 5000000 0>; 36 brightness-levels = <0 4 8 16 32 64 128 255>; 37 default-brightness-level = <7>; 38 power-supply = <®_12v0>; 39 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; 40 status = "disabled"; 41 }; 42 43 fan0: pwm-fan { 44 compatible = "pwm-fan"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_pwmfan>; 47 fan-supply = <®_pwm_fan>; 48 #cooling-cells = <2>; 49 /* typical 25 kHz -> 40.000 nsec */ 50 pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>; 51 cooling-levels = <0 32 64 128 196 240>; 52 pulses-per-revolution = <2>; 53 interrupt-parent = <&gpio2>; 54 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 55 status = "disabled"; 56 }; 57 58 gpio-keys { 59 compatible = "gpio-keys"; 60 autorepeat; 61 62 switch-a { 63 label = "switcha"; 64 linux,code = <BTN_0>; 65 gpios = <&expander0 6 GPIO_ACTIVE_LOW>; 66 wakeup-source; 67 }; 68 69 switch-b { 70 label = "switchb"; 71 linux,code = <BTN_1>; 72 gpios = <&expander0 7 GPIO_ACTIVE_LOW>; 73 wakeup-source; 74 }; 75 }; 76 77 gpio-leds { 78 compatible = "gpio-leds"; 79 80 led-1 { 81 color = <LED_COLOR_ID_GREEN>; 82 function = LED_FUNCTION_STATUS; 83 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; 84 linux,default-trigger = "default-on"; 85 }; 86 87 led-2 { 88 color = <LED_COLOR_ID_AMBER>; 89 function = LED_FUNCTION_HEARTBEAT; 90 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; 91 linux,default-trigger = "heartbeat"; 92 }; 93 }; 94 95 iio-hwmon { 96 compatible = "iio-hwmon"; 97 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; 98 }; 99 100 reg_3v3: regulator-3v3 { 101 compatible = "regulator-fixed"; 102 regulator-name = "V_3V3_MB"; 103 regulator-min-microvolt = <3300000>; 104 regulator-max-microvolt = <3300000>; 105 }; 106 107 reg_5v0: regulator-5v0 { 108 compatible = "regulator-fixed"; 109 regulator-name = "V_5V0_MB"; 110 regulator-min-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>; 112 }; 113 114 reg_12v0: regulator-12v0 { 115 compatible = "regulator-fixed"; 116 regulator-name = "V_12V"; 117 regulator-min-microvolt = <12000000>; 118 regulator-max-microvolt = <12000000>; 119 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; 120 enable-active-high; 121 }; 122 123 reg_mpcie_1v5: regulator-mpcie-1v5 { 124 compatible = "regulator-fixed"; 125 regulator-name = "V_1V5_MPCIE"; 126 regulator-min-microvolt = <1500000>; 127 regulator-max-microvolt = <1500000>; 128 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; 129 enable-active-high; 130 }; 131 132 reg_mpcie_3v3: regulator-mpcie-3v3 { 133 compatible = "regulator-fixed"; 134 regulator-name = "V_3V3_MPCIE"; 135 regulator-min-microvolt = <3300000>; 136 regulator-max-microvolt = <3300000>; 137 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 }; 140 141 reg_pwm_fan: regulator-pwm-fan { 142 compatible = "regulator-fixed"; 143 regulator-name = "FAN_PWR"; 144 regulator-min-microvolt = <12000000>; 145 regulator-max-microvolt = <12000000>; 146 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 147 enable-active-high; 148 vin-supply = <®_12v0>; 149 }; 150 151 thermal-zones { 152 cpu-thermal { 153 trips { 154 cpu_active0: trip-active0 { 155 temperature = <40000>; 156 hysteresis = <5000>; 157 type = "active"; 158 }; 159 160 cpu_active1: trip-active1 { 161 temperature = <48000>; 162 hysteresis = <3000>; 163 type = "active"; 164 }; 165 166 cpu_active2: trip-active2 { 167 temperature = <60000>; 168 hysteresis = <10000>; 169 type = "active"; 170 }; 171 }; 172 173 cooling-maps { 174 map1 { 175 trip = <&cpu_active0>; 176 cooling-device = <&fan0 1 1>; 177 }; 178 179 map2 { 180 trip = <&cpu_active1>; 181 cooling-device = <&fan0 2 2>; 182 }; 183 184 map3 { 185 trip = <&cpu_active2>; 186 cooling-device = <&fan0 3 3>; 187 }; 188 }; 189 }; 190 }; 191}; 192 193&adc1 { 194 status = "okay"; 195}; 196 197&eqos { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_eqos>; 200 phy-mode = "rgmii-id"; 201 phy-handle = <ðphy_eqos>; 202 status = "okay"; 203 204 mdio { 205 compatible = "snps,dwmac-mdio"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 209 ethphy_eqos: ethernet-phy@0 { 210 compatible = "ethernet-phy-ieee802.3-c22"; 211 reg = <0>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_eqos_phy>; 214 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; 215 reset-assert-us = <500000>; 216 reset-deassert-us = <50000>; 217 interrupt-parent = <&gpio3>; 218 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 219 enet-phy-lane-no-swap; 220 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 221 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 222 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 223 ti,dp83867-rxctrl-strap-quirk; 224 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 225 }; 226 }; 227}; 228 229&fec { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_fec>; 232 phy-mode = "rgmii-id"; 233 phy-handle = <ðphy_fec>; 234 fsl,magic-packet; 235 status = "okay"; 236 237 mdio { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 clock-frequency = <5000000>; 241 242 ethphy_fec: ethernet-phy@0 { 243 compatible = "ethernet-phy-ieee802.3-c22"; 244 reg = <0>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_fec_phy>; 247 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; 248 reset-assert-us = <500000>; 249 reset-deassert-us = <50000>; 250 interrupt-parent = <&gpio3>; 251 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 252 enet-phy-lane-no-swap; 253 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 254 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 255 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 256 ti,dp83867-rxctrl-strap-quirk; 257 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 258 }; 259 }; 260}; 261 262&flexcan1 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_flexcan1>; 265 xceiver-supply = <®_3v3>; 266 status = "okay"; 267}; 268 269&flexcan2 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_flexcan2>; 272 xceiver-supply = <®_3v3>; 273 status = "okay"; 274}; 275 276&gpio1 { 277 expander-irq-hog { 278 gpio-hog; 279 gpios = <12 GPIO_ACTIVE_LOW>; 280 input; 281 line-name = "PEX_INT#"; 282 }; 283 284 tcpc-irq-hog { 285 gpio-hog; 286 gpios = <2 GPIO_ACTIVE_LOW>; 287 input; 288 line-name = "USB_C_ALERT#"; 289 }; 290}; 291 292&lpi2c3 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 clock-frequency = <400000>; 296 pinctrl-names = "default", "sleep"; 297 pinctrl-0 = <&pinctrl_lpi2c3>; 298 pinctrl-1 = <&pinctrl_lpi2c3>; 299 status = "okay"; 300 301 temperature-sensor@1c { 302 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 303 reg = <0x1c>; 304 }; 305 306 eeprom2: eeprom@54 { 307 compatible = "nxp,se97b", "atmel,24c02"; 308 reg = <0x54>; 309 pagesize = <16>; 310 vcc-supply = <®_3v3>; 311 }; 312 313 expander0: gpio@70 { 314 compatible = "nxp,pca9538"; 315 reg = <0x70>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_pexp_irq>; 318 gpio-controller; 319 #gpio-cells = <2>; 320 interrupt-controller; 321 #interrupt-cells = <2>; 322 interrupt-parent = <&gpio1>; 323 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 324 vcc-supply = <®_3v3>; 325 gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#", 326 "MPCIE_1V5_EN", "MPCIE_3V3_EN", 327 "MPCIE_PERST#", "MPCIE_WDISABLE#", 328 "BUTTON_A#", "BUTTON_B#"; 329 330 mpcie-wake-hog { 331 gpio-hog; 332 gpios = <1 GPIO_ACTIVE_LOW>; 333 input; 334 line-name = "MPCIE_WAKE#"; 335 }; 336 337 /* 338 * Controls the mPCIE slot reset which is low active as 339 * reset signal. The output-low states, the signal is 340 * inactive, e.g. not in reset 341 */ 342 mpcie_rst_hog: mpcie-rst-hog { 343 gpio-hog; 344 gpios = <4 GPIO_ACTIVE_LOW>; 345 output-low; 346 line-name = "MPCIE_PERST#"; 347 }; 348 349 /* 350 * Controls the mPCIE slot WDISABLE pin which is low active 351 * as disable signal. The output-low states, the signal is 352 * inactive, e.g. not disabled 353 */ 354 mpcie_wdisable_hog: mpcie-wdisable-hog { 355 gpio-hog; 356 gpios = <5 GPIO_ACTIVE_LOW>; 357 output-low; 358 line-name = "MPCIE_WDISABLE#"; 359 }; 360 }; 361 362 expander1: gpio@71 { 363 compatible = "nxp,pca9538"; 364 reg = <0x71>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 vcc-supply = <®_3v3>; 368 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", 369 "USB_RESET#", "", 370 "WLAN_PD#", "WLAN_W_DISABLE#", 371 "WLAN_PERST#", "12V_EN"; 372 373 /* 374 * Controls the on board USB Hub reset which is low 375 * active as reset signal. The output-low states, the 376 * signal is inactive, e.g. no reset 377 */ 378 usb-reset-hog { 379 gpio-hog; 380 gpios = <2 GPIO_ACTIVE_LOW>; 381 output-low; 382 line-name = "USB_RESET#"; 383 }; 384 385 /* 386 * Controls the WiFi card PD pin which is low active 387 * as power down signal. The output-high states, the signal 388 * is active, e.g. card is powered down 389 */ 390 wlan-pd-hog { 391 gpio-hog; 392 gpios = <4 GPIO_ACTIVE_LOW>; 393 output-high; 394 line-name = "WLAN_PD#"; 395 }; 396 397 /* 398 * Controls the WiFi card disable pin which is low active 399 * as disable signal. The output-high states, the signal 400 * is active, e.g. card is disabled 401 */ 402 wlan-wdisable-hog { 403 gpio-hog; 404 gpios = <5 GPIO_ACTIVE_LOW>; 405 output-high; 406 line-name = "WLAN_W_DISABLE#"; 407 }; 408 409 /* 410 * Controls the WiFi card reset pin which is low active 411 * as reset signal. The output-high states, the signal 412 * is active, e.g. card in reset 413 */ 414 wlan-perst-hog { 415 gpio-hog; 416 gpios = <6 GPIO_ACTIVE_LOW>; 417 output-high; 418 line-name = "WLAN_PERST#"; 419 }; 420 }; 421 422 expander2: gpio@72 { 423 compatible = "nxp,pca9538"; 424 reg = <0x72>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 vcc-supply = <®_3v3>; 428 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", 429 "LCD_BLT_EN", "DP_EN", 430 "MIPI_CSI_EN", "MIPI_CSI_RST#", 431 "USER_LED1", "USER_LED2"; 432 }; 433}; 434 435&lpi2c5 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 clock-frequency = <400000>; 439 pinctrl-names = "default", "sleep"; 440 pinctrl-0 = <&pinctrl_lpi2c5>; 441 pinctrl-1 = <&pinctrl_lpi2c5>; 442 status = "okay"; 443}; 444 445&lpspi6 { 446 pinctrl-names = "default", "sleep"; 447 pinctrl-0 = <&pinctrl_lpspi6>; 448 pinctrl-1 = <&pinctrl_lpspi6>; 449 status = "okay"; 450}; 451 452&lpuart1 { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_uart1>; 455 status = "okay"; 456}; 457 458&lpuart2 { 459 pinctrl-names = "default"; 460 pinctrl-0 = <&pinctrl_uart2>; 461 linux,rs485-enabled-at-boot-time; 462 status = "okay"; 463}; 464 465/* disabled per default, console for M33 */ 466&lpuart3 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_uart3>; 469 status = "disabled"; 470}; 471 472&lpuart6 { 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pinctrl_uart6>; 475 status = "okay"; 476}; 477 478&lpuart8 { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_uart8>; 481 status = "okay"; 482}; 483 484&tpm5 { 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_tpm5>; 487}; 488 489&tpm6 { 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pinctrl_tpm6>; 492 status = "okay"; 493}; 494 495&usdhc2 { 496 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 497 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; 498 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 499 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 500 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 501 vmmc-supply = <®_usdhc2_vmmc>; 502 bus-width = <4>; 503 no-sdio; 504 no-mmc; 505 disable-wp; 506 status = "okay"; 507}; 508 509&iomuxc { 510 pinctrl_eqos: eqosgrp { 511 fsl,pins = < 512 /* PD | FSEL_2 | DSE X4 */ 513 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e 514 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e 515 /* PD | FSEL_2 | DSE X6 */ 516 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 517 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 518 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 519 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 520 /* PD | FSEL_3 | DSE X6 */ 521 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 522 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 523 /* PD | FSEL_2 | DSE X4 */ 524 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e 525 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e 526 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e 527 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e 528 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e 529 /* PD | FSEL_3 | DSE X3 */ 530 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 531 >; 532 }; 533 534 pinctrl_eqos_phy: eqosphygrp { 535 fsl,pins = < 536 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306 537 >; 538 }; 539 540 pinctrl_fec: fecgrp { 541 fsl,pins = < 542 /* PD | FSEL_2 | DSE X4 */ 543 MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e 544 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e 545 /* PD | FSEL_2 | DSE X6 */ 546 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 547 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 548 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 549 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 550 /* PD | FSEL_3 | DSE X6 */ 551 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 552 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 553 /* PD | FSEL_2 | DSE X4 */ 554 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e 555 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e 556 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e 557 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e 558 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e 559 /* PD | FSEL_3 | DSE X3 */ 560 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 561 >; 562 }; 563 564 pinctrl_fec_phy: fecphygrp { 565 fsl,pins = < 566 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306 567 >; 568 }; 569 570 pinctrl_flexcan1: flexcan1grp { 571 fsl,pins = < 572 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 573 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 574 >; 575 }; 576 577 pinctrl_flexcan2: flexcan2grp { 578 fsl,pins = < 579 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 580 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 581 >; 582 }; 583 584 pinctrl_lpi2c3: lpi2c3grp { 585 fsl,pins = < 586 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 587 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 588 >; 589 }; 590 591 pinctrl_lpi2c5: lpi2c5grp { 592 fsl,pins = < 593 MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e 594 MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e 595 >; 596 }; 597 598 pinctrl_lpspi6: lpspi6grp { 599 fsl,pins = < 600 MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x3fe 601 MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe 602 MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe 603 MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe 604 >; 605 }; 606 607 pinctrl_pexp_irq: pexpirqgrp { 608 fsl,pins = < 609 MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306 610 >; 611 }; 612 613 pinctrl_pwmfan: pwmfangrp { 614 fsl,pins = < 615 MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1306 616 >; 617 }; 618 619 pinctrl_tpm5: tpm5grp { 620 fsl,pins = < 621 MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e 622 >; 623 }; 624 625 pinctrl_tpm6: tpm6grp { 626 fsl,pins = < 627 MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e 628 >; 629 }; 630 631 pinctrl_typec: typecgrp { 632 fsl,pins = < 633 MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306 634 >; 635 }; 636 637 pinctrl_uart1: uart1grp { 638 fsl,pins = < 639 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 640 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 641 >; 642 }; 643 644 pinctrl_uart2: uart2grp { 645 fsl,pins = < 646 MX93_PAD_UART2_TXD__LPUART2_TX 0x31e 647 MX93_PAD_UART2_RXD__LPUART2_RX 0x31e 648 MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e 649 >; 650 }; 651 652 pinctrl_uart3: uart3grp { 653 fsl,pins = < 654 MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e 655 MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e 656 >; 657 }; 658 659 pinctrl_uart6: uart6grp { 660 fsl,pins = < 661 MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e 662 MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e 663 >; 664 }; 665 666 pinctrl_uart8: uart8grp { 667 fsl,pins = < 668 MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e 669 MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e 670 >; 671 }; 672 673 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 674 fsl,pins = < 675 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 676 >; 677 }; 678 679 pinctrl_usdhc2_hs: usdhc2hsgrp { 680 fsl,pins = < 681 /* HYS | PD | PU | FSEL_3 | DSE X5 */ 682 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be 683 /* HYS | PD | PU | FSEL_3 | DSE X4 */ 684 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 685 /* HYS | PD | PU | FSEL_3 | DSE X3 */ 686 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 687 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 688 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 689 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 690 /* PD | PU | FSEL_2 | DSE X3 */ 691 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e 692 >; 693 }; 694 695 pinctrl_usdhc2_uhs: usdhc2uhsgrp { 696 fsl,pins = < 697 /* HYS | PD | PU | FSEL_3 | DSE X6 */ 698 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe 699 /* HYS | PD | PU | FSEL_3 | DSE X4 */ 700 MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e 701 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e 702 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e 703 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e 704 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e 705 /* PD | PU | FSEL_2 | DSE X3 */ 706 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e 707 >; 708 }; 709}; 710