1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 9x9 Quick Start Board"; 13 compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; 14 15 bt_sco_codec: bt-sco-codec { 16 #sound-dai-cells = <1>; 17 compatible = "linux,bt-sco"; 18 }; 19 20 chosen { 21 stdout-path = &lpuart1; 22 }; 23 24 reserved-memory { 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 29 linux,cma { 30 compatible = "shared-dma-pool"; 31 reusable; 32 size = <0 0x10000000>; 33 linux,cma-default; 34 }; 35 36 vdev0vring0: vdev0vring0@a4000000 { 37 reg = <0 0xa4000000 0 0x8000>; 38 no-map; 39 }; 40 41 vdev0vring1: vdev0vring1@a4008000 { 42 reg = <0 0xa4008000 0 0x8000>; 43 no-map; 44 }; 45 46 vdev1vring0: vdev1vring0@a4010000 { 47 reg = <0 0xa4010000 0 0x8000>; 48 no-map; 49 }; 50 51 vdev1vring1: vdev1vring1@a4018000 { 52 reg = <0 0xa4018000 0 0x8000>; 53 no-map; 54 }; 55 56 rsc_table: rsc-table@2021e000 { 57 reg = <0 0x2021e000 0 0x1000>; 58 no-map; 59 }; 60 61 vdevbuffer: vdevbuffer@a4020000 { 62 compatible = "shared-dma-pool"; 63 reg = <0 0xa4020000 0 0x100000>; 64 no-map; 65 }; 66 67 }; 68 69 reg_vref_1v8: regulator-adc-vref { 70 compatible = "regulator-fixed"; 71 regulator-name = "VREF_1V8"; 72 regulator-min-microvolt = <1800000>; 73 regulator-max-microvolt = <1800000>; 74 }; 75 76 reg_audio_pwr: regulator-audio-pwr { 77 compatible = "regulator-fixed"; 78 regulator-name = "audio-pwr"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; 82 enable-active-high; 83 }; 84 85 reg_m2_pwr: regulator-m2-pwr { 86 compatible = "regulator-fixed"; 87 regulator-name = "M.2-power"; 88 regulator-min-microvolt = <3300000>; 89 regulator-max-microvolt = <3300000>; 90 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 91 enable-active-high; 92 }; 93 94 reg_rpi_3v3: regulator-rpi { 95 compatible = "regulator-fixed"; 96 regulator-name = "VDD_RPI_3V3"; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; 100 enable-active-high; 101 }; 102 103 reg_usdhc2_vmmc: regulator-usdhc2 { 104 compatible = "regulator-fixed"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 107 regulator-name = "VSD_3V3"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 111 enable-active-high; 112 off-on-delay-us = <12000>; 113 }; 114 115 reg_usdhc3_vmmc: regulator-usdhc3 { 116 compatible = "regulator-fixed"; 117 regulator-name = "WLAN_EN"; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 vin-supply = <®_m2_pwr>; 121 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 122 /* 123 * IW612 wifi chip needs more delay than other wifi chips to complete 124 * the host interface initialization after power up, otherwise the 125 * internal state of IW612 may be unstable, resulting in the failure of 126 * the SDIO3.0 switch voltage. 127 */ 128 startup-delay-us = <20000>; 129 enable-active-high; 130 }; 131 132 sound-bt-sco { 133 compatible = "simple-audio-card"; 134 simple-audio-card,name = "bt-sco-audio"; 135 simple-audio-card,format = "dsp_a"; 136 simple-audio-card,bitclock-inversion; 137 simple-audio-card,frame-master = <&btcpu>; 138 simple-audio-card,bitclock-master = <&btcpu>; 139 140 btcpu: simple-audio-card,cpu { 141 sound-dai = <&sai1>; 142 dai-tdm-slot-num = <2>; 143 dai-tdm-slot-width = <16>; 144 }; 145 146 simple-audio-card,codec { 147 sound-dai = <&bt_sco_codec 1>; 148 }; 149 }; 150 151 sound-micfil { 152 compatible = "fsl,imx-audio-card"; 153 model = "micfil-audio"; 154 155 pri-dai-link { 156 link-name = "micfil hifi"; 157 format = "i2s"; 158 159 cpu { 160 sound-dai = <&micfil>; 161 }; 162 }; 163 }; 164 165 sound-wm8962 { 166 compatible = "fsl,imx-audio-wm8962"; 167 model = "wm8962-audio"; 168 audio-cpu = <&sai3>; 169 audio-codec = <&wm8962>; 170 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 171 audio-routing = 172 "Headphone Jack", "HPOUTL", 173 "Headphone Jack", "HPOUTR", 174 "Ext Spk", "SPKOUTL", 175 "Ext Spk", "SPKOUTR", 176 "AMIC", "MICBIAS", 177 "IN3R", "AMIC", 178 "IN1R", "AMIC"; 179 }; 180 181 usdhc3_pwrseq: usdhc3_pwrseq { 182 compatible = "mmc-pwrseq-simple"; 183 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 184 }; 185}; 186 187&adc1 { 188 vref-supply = <®_vref_1v8>; 189 status = "okay"; 190}; 191 192&cm33 { 193 mbox-names = "tx", "rx", "rxdb"; 194 mboxes = <&mu1 0 1>, 195 <&mu1 1 1>, 196 <&mu1 3 1>; 197 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 198 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 199 status = "okay"; 200}; 201 202&eqos { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_eqos>; 205 phy-mode = "rgmii-id"; 206 phy-handle = <ðphy1>; 207 status = "okay"; 208 209 mdio { 210 compatible = "snps,dwmac-mdio"; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 clock-frequency = <5000000>; 214 215 ethphy1: ethernet-phy@1 { 216 compatible = "ethernet-phy-ieee802.3-c22"; 217 reg = <1>; 218 reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 219 reset-assert-us = <10000>; 220 reset-deassert-us = <80000>; 221 realtek,clkout-disable; 222 }; 223 }; 224}; 225 226&lpi2c1 { 227 clock-frequency = <400000>; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_lpi2c1>; 230 status = "okay"; 231 232 wm8962: audio-codec@1a { 233 compatible = "wlf,wm8962"; 234 reg = <0x1a>; 235 clocks = <&clk IMX93_CLK_SAI3_GATE>; 236 DCVDD-supply = <®_audio_pwr>; 237 DBVDD-supply = <®_audio_pwr>; 238 AVDD-supply = <®_audio_pwr>; 239 CPVDD-supply = <®_audio_pwr>; 240 MICVDD-supply = <®_audio_pwr>; 241 PLLVDD-supply = <®_audio_pwr>; 242 SPKVDD1-supply = <®_audio_pwr>; 243 SPKVDD2-supply = <®_audio_pwr>; 244 gpio-cfg = < 245 0x0000 /* 0:Default */ 246 0x0000 /* 1:Default */ 247 0x0000 /* 2:FN_DMICCLK */ 248 0x0000 /* 3:Default */ 249 0x0000 /* 4:FN_DMICCDAT */ 250 0x0000 /* 5:Default */ 251 >; 252 }; 253 254 p3t1085: temperature-sensor@48 { 255 compatible = "nxp,p3t1085"; 256 reg = <0x48>; 257 }; 258 259 ptn5110: tcpc@50 { 260 compatible = "nxp,ptn5110", "tcpci"; 261 reg = <0x50>; 262 interrupt-parent = <&gpio3>; 263 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 264 265 typec1_con: connector { 266 compatible = "usb-c-connector"; 267 label = "USB-C"; 268 power-role = "dual"; 269 data-role = "dual"; 270 try-power-role = "sink"; 271 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 272 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 273 PDO_VAR(5000, 20000, 3000)>; 274 op-sink-microwatt = <15000000>; 275 self-powered; 276 277 ports { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 281 port@0 { 282 reg = <0>; 283 284 typec1_dr_sw: endpoint { 285 remote-endpoint = <&usb1_drd_sw>; 286 }; 287 }; 288 }; 289 }; 290 }; 291 292 rtc@53 { 293 compatible = "nxp,pcf2131"; 294 reg = <0x53>; 295 interrupt-parent = <&pcal6524>; 296 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 297 }; 298 299 inertial-meter@6a { 300 compatible = "st,lsm6dso"; 301 reg = <0x6a>; 302 }; 303}; 304 305&lpi2c2 { 306 clock-frequency = <400000>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_lpi2c2>; 309 status = "okay"; 310 311 pcal6524: gpio@22 { 312 compatible = "nxp,pcal6524"; 313 reg = <0x22>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 interrupt-parent = <&gpio3>; 319 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_pcal6524>; 322 323 exp-sel-hog { 324 gpio-hog; 325 gpios = <22 GPIO_ACTIVE_HIGH>; 326 output-low; 327 }; 328 329 mic-can-sel-hog { 330 gpio-hog; 331 gpios = <17 GPIO_ACTIVE_HIGH>; 332 output-low; 333 }; 334 }; 335 336 pmic@25 { 337 compatible = "nxp,pca9451a"; 338 reg = <0x25>; 339 interrupt-parent = <&pcal6524>; 340 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 341 342 regulators { 343 buck1: BUCK1 { 344 regulator-name = "BUCK1"; 345 regulator-min-microvolt = <650000>; 346 regulator-max-microvolt = <2237500>; 347 regulator-boot-on; 348 regulator-always-on; 349 regulator-ramp-delay = <3125>; 350 }; 351 352 buck2: BUCK2 { 353 regulator-name = "BUCK2"; 354 regulator-min-microvolt = <600000>; 355 regulator-max-microvolt = <2187500>; 356 regulator-boot-on; 357 regulator-always-on; 358 regulator-ramp-delay = <3125>; 359 }; 360 361 buck4: BUCK4 { 362 regulator-name = "BUCK4"; 363 regulator-min-microvolt = <600000>; 364 regulator-max-microvolt = <3400000>; 365 regulator-boot-on; 366 regulator-always-on; 367 }; 368 369 buck5: BUCK5 { 370 regulator-name = "BUCK5"; 371 regulator-min-microvolt = <600000>; 372 regulator-max-microvolt = <3400000>; 373 regulator-boot-on; 374 regulator-always-on; 375 }; 376 377 buck6: BUCK6 { 378 regulator-name = "BUCK6"; 379 regulator-min-microvolt = <600000>; 380 regulator-max-microvolt = <3400000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 385 ldo1: LDO1 { 386 regulator-name = "LDO1"; 387 regulator-min-microvolt = <1600000>; 388 regulator-max-microvolt = <3300000>; 389 regulator-boot-on; 390 regulator-always-on; 391 }; 392 393 ldo4: LDO4 { 394 regulator-name = "LDO4"; 395 regulator-min-microvolt = <800000>; 396 regulator-max-microvolt = <3300000>; 397 regulator-boot-on; 398 regulator-always-on; 399 }; 400 401 ldo5: LDO5 { 402 regulator-name = "LDO5"; 403 regulator-min-microvolt = <1800000>; 404 regulator-max-microvolt = <3300000>; 405 regulator-boot-on; 406 regulator-always-on; 407 }; 408 }; 409 }; 410}; 411 412&lpuart1 { /* console */ 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_uart1>; 415 status = "okay"; 416}; 417 418&lpuart5 { 419 /* BT */ 420 pinctrl-names = "default"; 421 pinctrl-0 = <&pinctrl_uart5>; 422 status = "okay"; 423 424 bluetooth { 425 compatible = "nxp,88w8987-bt"; 426 }; 427}; 428 429&micfil { 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_pdm>; 432 assigned-clocks = <&clk IMX93_CLK_PDM>; 433 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 434 assigned-clock-rates = <49152000>; 435 status = "okay"; 436}; 437 438&mu1 { 439 status = "okay"; 440}; 441 442&mu2 { 443 status = "okay"; 444}; 445 446&sai1 { 447 pinctrl-names = "default"; 448 pinctrl-0 = <&pinctrl_sai1>; 449 assigned-clocks = <&clk IMX93_CLK_SAI1>; 450 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 451 assigned-clock-rates = <12288000>; 452 fsl,sai-mclk-direction-output; 453 status = "okay"; 454}; 455 456&sai3 { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_sai3>; 459 assigned-clocks = <&clk IMX93_CLK_SAI3>; 460 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 461 assigned-clock-rates = <12288000>; 462 fsl,sai-mclk-direction-output; 463 fsl,sai-synchronous-rx; 464 status = "okay"; 465}; 466 467&usbotg1 { 468 dr_mode = "otg"; 469 hnp-disable; 470 srp-disable; 471 adp-disable; 472 usb-role-switch; 473 disable-over-current; 474 samsung,picophy-pre-emp-curr-control = <3>; 475 samsung,picophy-dc-vol-level-adjust = <7>; 476 status = "okay"; 477 478 port { 479 usb1_drd_sw: endpoint { 480 remote-endpoint = <&typec1_dr_sw>; 481 }; 482 }; 483}; 484 485&usdhc1 { 486 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 487 pinctrl-0 = <&pinctrl_usdhc1>; 488 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 489 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 490 bus-width = <8>; 491 non-removable; 492 status = "okay"; 493}; 494 495&usdhc2 { 496 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 497 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 498 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 499 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 500 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 501 vmmc-supply = <®_usdhc2_vmmc>; 502 bus-width = <4>; 503 no-mmc; 504 status = "okay"; 505}; 506 507&usdhc3 { 508 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 509 pinctrl-0 = <&pinctrl_usdhc3>; 510 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 511 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 512 mmc-pwrseq = <&usdhc3_pwrseq>; 513 vmmc-supply = <®_usdhc3_vmmc>; 514 bus-width = <4>; 515 keep-power-in-suspend; 516 non-removable; 517 wakeup-source; 518 status = "okay"; 519}; 520 521&wdog3 { 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pinctrl_wdog>; 524 fsl,ext-reset-output; 525 status = "okay"; 526}; 527 528&iomuxc { 529 pinctrl_eqos: eqosgrp { 530 fsl,pins = < 531 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 532 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 533 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 534 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 535 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 536 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 537 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 538 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 539 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 540 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 541 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 542 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 543 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 544 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 545 >; 546 }; 547 548 pinctrl_lpi2c1: lpi2c1grp { 549 fsl,pins = < 550 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 551 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 552 >; 553 }; 554 555 pinctrl_lpi2c2: lpi2c2grp { 556 fsl,pins = < 557 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 558 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 559 >; 560 }; 561 562 pinctrl_pcal6524: pcal6524grp { 563 fsl,pins = < 564 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 565 >; 566 }; 567 568 pinctrl_pdm: pdmgrp { 569 fsl,pins = < 570 MX93_PAD_PDM_CLK__PDM_CLK 0x31e 571 MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e 572 MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e 573 >; 574 }; 575 576 pinctrl_uart1: uart1grp { 577 fsl,pins = < 578 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 579 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 580 >; 581 }; 582 583 pinctrl_uart5: uart5grp { 584 fsl,pins = < 585 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 586 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 587 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 588 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 589 >; 590 }; 591 592 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 593 pinctrl_usdhc1: usdhc1grp { 594 fsl,pins = < 595 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 596 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 597 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 598 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 599 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 600 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 601 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 602 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 603 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 604 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 605 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 606 >; 607 }; 608 609 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 610 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 611 fsl,pins = < 612 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 613 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 614 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 615 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 616 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 617 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 618 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 619 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 620 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 621 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 622 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 623 >; 624 }; 625 626 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 627 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 628 fsl,pins = < 629 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 630 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 631 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 632 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 633 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 634 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 635 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 636 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 637 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 638 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 639 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 640 >; 641 }; 642 643 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 644 fsl,pins = < 645 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 646 >; 647 }; 648 649 pinctrl_sai1: sai1grp { 650 fsl,pins = < 651 MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 652 MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 653 MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e 654 MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e 655 >; 656 }; 657 658 pinctrl_sai3: sai3grp { 659 fsl,pins = < 660 MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e 661 MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e 662 MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e 663 MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e 664 MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e 665 >; 666 }; 667 668 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 669 fsl,pins = < 670 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 671 >; 672 }; 673 674 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 675 pinctrl_usdhc2: usdhc2grp { 676 fsl,pins = < 677 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 678 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 679 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 680 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 681 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 682 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 683 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 684 >; 685 }; 686 687 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 688 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 689 fsl,pins = < 690 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 691 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 692 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 693 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 694 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 695 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 696 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 697 >; 698 }; 699 700 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 701 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 702 fsl,pins = < 703 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 704 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 705 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 706 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 707 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 708 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 709 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 710 >; 711 }; 712 713 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 714 pinctrl_usdhc3: usdhc3grp { 715 fsl,pins = < 716 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 717 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 718 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 719 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 720 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 721 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 722 >; 723 }; 724 725 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 726 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 727 fsl,pins = < 728 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 729 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 730 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 731 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 732 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 733 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 734 >; 735 }; 736 737 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 738 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 739 fsl,pins = < 740 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 741 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 742 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 743 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 744 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 745 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 746 >; 747 }; 748 749 pinctrl_wdog: wdoggrp { 750 fsl,pins = < 751 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 752 >; 753 }; 754}; 755