1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx93.dtsi" 10 11/ { 12 model = "NXP i.MX93 14X14 EVK board"; 13 compatible = "fsl,imx93-14x14-evk", "fsl,imx93"; 14 15 chosen { 16 stdout-path = &lpuart1; 17 }; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 linux,cma { 25 compatible = "shared-dma-pool"; 26 reusable; 27 alloc-ranges = <0 0x80000000 0 0x40000000>; 28 size = <0 0x10000000>; 29 linux,cma-default; 30 }; 31 32 vdev0vring0: vdev0vring0@a4000000 { 33 reg = <0 0xa4000000 0 0x8000>; 34 no-map; 35 }; 36 37 vdev0vring1: vdev0vring1@a4008000 { 38 reg = <0 0xa4008000 0 0x8000>; 39 no-map; 40 }; 41 42 vdev1vring0: vdev1vring0@a4010000 { 43 reg = <0 0xa4010000 0 0x8000>; 44 no-map; 45 }; 46 47 vdev1vring1: vdev1vring1@a4018000 { 48 reg = <0 0xa4018000 0 0x8000>; 49 no-map; 50 }; 51 52 rsc_table: rsc-table@2021e000 { 53 reg = <0 0x2021e000 0 0x1000>; 54 no-map; 55 }; 56 57 vdevbuffer: vdevbuffer@a4020000 { 58 compatible = "shared-dma-pool"; 59 reg = <0 0xa4020000 0 0x100000>; 60 no-map; 61 }; 62 }; 63 64 reg_can1_stby: regulator-can1-stby { 65 compatible = "regulator-fixed"; 66 regulator-name = "can1-stby"; 67 regulator-min-microvolt = <3300000>; 68 regulator-max-microvolt = <3300000>; 69 gpio = <&pcal6524_2 10 GPIO_ACTIVE_HIGH>; 70 enable-active-high; 71 vin-supply = <®_can1_en>; 72 }; 73 74 reg_can1_en: regulator-can1-en { 75 compatible = "regulator-fixed"; 76 regulator-name = "can1-en"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 gpio = <&pcal6524_2 12 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 }; 82 83 reg_can2_stby: regulator-can2-stby { 84 compatible = "regulator-fixed"; 85 regulator-name = "can2-stby"; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 gpio = <&pcal6524_2 11 GPIO_ACTIVE_HIGH>; 89 enable-active-high; 90 vin-supply = <®_can2_en>; 91 }; 92 93 reg_can2_en: regulator-can2-en { 94 compatible = "regulator-fixed"; 95 regulator-name = "can2-en"; 96 regulator-min-microvolt = <3300000>; 97 regulator-max-microvolt = <3300000>; 98 gpio = <&pcal6524_2 13 GPIO_ACTIVE_HIGH>; 99 enable-active-high; 100 }; 101 102 reg_m2_pwr: regulator-m2-pwr { 103 compatible = "regulator-fixed"; 104 regulator-name = "M.2-power"; 105 regulator-min-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>; 107 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 108 enable-active-high; 109 }; 110 111 reg_usdhc2_vmmc: regulator-usdhc2 { 112 compatible = "regulator-fixed"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 115 regulator-name = "VSD_3V3"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 119 enable-active-high; 120 off-on-delay-us = <12000>; 121 }; 122 123 reg_usdhc3_vmmc: regulator-usdhc3 { 124 compatible = "regulator-fixed"; 125 regulator-name = "WLAN_EN"; 126 regulator-min-microvolt = <3300000>; 127 regulator-max-microvolt = <3300000>; 128 vin-supply = <®_m2_pwr>; 129 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 130 /* 131 * IW612 wifi chip needs more delay than other wifi chips to complete 132 * the host interface initialization after power up, otherwise the 133 * internal state of IW612 may be unstable, resulting in the failure of 134 * the SDIO3.0 switch voltage. 135 */ 136 startup-delay-us = <20000>; 137 enable-active-high; 138 }; 139 140 reg_vdd_12v: regulator-vdd-12v { 141 compatible = "regulator-fixed"; 142 regulator-name = "reg_vdd_12v"; 143 regulator-min-microvolt = <12000000>; 144 regulator-max-microvolt = <12000000>; 145 gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; 146 enable-active-high; 147 }; 148 149 reg_vref_1v8: regulator-adc-vref { 150 compatible = "regulator-fixed"; 151 regulator-name = "vref_1v8"; 152 regulator-min-microvolt = <1800000>; 153 regulator-max-microvolt = <1800000>; 154 }; 155 156 usdhc3_pwrseq: usdhc3_pwrseq { 157 compatible = "mmc-pwrseq-simple"; 158 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 159 }; 160}; 161 162&adc1 { 163 vref-supply = <®_vref_1v8>; 164 status = "okay"; 165}; 166 167&cm33 { 168 mbox-names = "tx", "rx", "rxdb"; 169 mboxes = <&mu1 0 1>, 170 <&mu1 1 1>, 171 <&mu1 3 1>; 172 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 173 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 174 status = "okay"; 175}; 176 177&fec { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_fec>; 180 phy-mode = "rgmii-id"; 181 phy-handle = <ðphy2>; 182 fsl,magic-packet; 183 status = "okay"; 184 185 mdio { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 clock-frequency = <5000000>; 189 190 ethphy2: ethernet-phy@2 { 191 compatible = "ethernet-phy-ieee802.3-c22"; 192 reg = <2>; 193 eee-broken-1000t; 194 reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; 195 reset-assert-us = <10000>; 196 reset-deassert-us = <80000>; 197 realtek,clkout-disable; 198 }; 199 }; 200}; 201 202&flexcan1 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_flexcan1>; 205 xceiver-supply = <®_can1_stby>; 206 status = "okay"; 207}; 208 209&flexcan2 { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_flexcan2>; 212 xceiver-supply = <®_can2_stby>; 213 status = "okay"; 214}; 215 216&lpi2c1 { 217 clock-frequency = <400000>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_lpi2c1>; 220 status = "okay"; 221 222 lsm6dsm@6a { 223 compatible = "st,lsm6dso"; 224 reg = <0x6a>; 225 }; 226}; 227 228&lpi2c2 { 229 clock-frequency = <400000>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_lpi2c2>; 232 status = "okay"; 233 234 pcal6524_2: gpio@20 { 235 compatible = "nxp,pcal6524"; 236 reg = <0x20>; 237 gpio-controller; 238 #gpio-cells = <2>; 239 }; 240 241 pcal6524: gpio@22 { 242 compatible = "nxp,pcal6524"; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_pcal6524>; 245 reg = <0x22>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 interrupt-parent = <&gpio3>; 251 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 252 }; 253 254 pmic@25 { 255 compatible = "nxp,pca9452"; 256 reg = <0x25>; 257 interrupt-parent = <&pcal6524>; 258 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 259 260 regulators { 261 buck1: BUCK1 { 262 regulator-name = "BUCK1"; 263 regulator-min-microvolt = <610000>; 264 regulator-max-microvolt = <950000>; 265 regulator-boot-on; 266 regulator-always-on; 267 regulator-ramp-delay = <3125>; 268 }; 269 270 buck2: BUCK2 { 271 regulator-name = "BUCK2"; 272 regulator-min-microvolt = <600000>; 273 regulator-max-microvolt = <670000>; 274 regulator-boot-on; 275 regulator-always-on; 276 regulator-ramp-delay = <3125>; 277 }; 278 279 buck4: BUCK4{ 280 regulator-name = "BUCK4"; 281 regulator-min-microvolt = <1620000>; 282 regulator-max-microvolt = <3400000>; 283 regulator-boot-on; 284 regulator-always-on; 285 }; 286 287 buck5: BUCK5{ 288 regulator-name = "BUCK5"; 289 regulator-min-microvolt = <1620000>; 290 regulator-max-microvolt = <3400000>; 291 regulator-boot-on; 292 regulator-always-on; 293 }; 294 295 buck6: BUCK6 { 296 regulator-name = "BUCK6"; 297 regulator-min-microvolt = <1060000>; 298 regulator-max-microvolt = <1140000>; 299 regulator-boot-on; 300 regulator-always-on; 301 }; 302 303 ldo1: LDO1 { 304 regulator-name = "LDO1"; 305 regulator-min-microvolt = <1620000>; 306 regulator-max-microvolt = <1980000>; 307 regulator-boot-on; 308 regulator-always-on; 309 }; 310 311 ldo3: LDO3 { 312 regulator-name = "LDO3"; 313 regulator-min-microvolt = <1710000>; 314 regulator-max-microvolt = <1890000>; 315 regulator-boot-on; 316 regulator-always-on; 317 }; 318 319 ldo4: LDO4 { 320 regulator-name = "LDO4"; 321 regulator-min-microvolt = <800000>; 322 regulator-max-microvolt = <840000>; 323 regulator-boot-on; 324 regulator-always-on; 325 }; 326 327 ldo5: LDO5 { 328 regulator-name = "LDO5"; 329 regulator-min-microvolt = <1800000>; 330 regulator-max-microvolt = <3300000>; 331 regulator-boot-on; 332 regulator-always-on; 333 }; 334 }; 335 }; 336}; 337 338&lpi2c3 { 339 clock-frequency = <400000>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_lpi2c3>; 342 status = "okay"; 343}; 344 345&lpuart1 { /* console */ 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_uart1>; 348 status = "okay"; 349}; 350 351&mu1 { 352 status = "okay"; 353}; 354 355&mu2 { 356 status = "okay"; 357}; 358 359&usbotg1 { 360 dr_mode = "otg"; 361 hnp-disable; 362 srp-disable; 363 adp-disable; 364 disable-over-current; 365 samsung,picophy-pre-emp-curr-control = <3>; 366 samsung,picophy-dc-vol-level-adjust = <7>; 367 status = "okay"; 368}; 369 370&usbotg2 { 371 dr_mode = "host"; 372 disable-over-current; 373 samsung,picophy-pre-emp-curr-control = <3>; 374 samsung,picophy-dc-vol-level-adjust = <7>; 375 status = "okay"; 376}; 377 378&usdhc1 { 379 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 380 pinctrl-0 = <&pinctrl_usdhc1>; 381 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 382 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 383 bus-width = <8>; 384 non-removable; 385 status = "okay"; 386}; 387 388&usdhc2 { 389 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 390 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 391 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 392 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 393 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 394 vmmc-supply = <®_usdhc2_vmmc>; 395 bus-width = <4>; 396 no-mmc; 397 status = "okay"; 398}; 399 400&usdhc3 { 401 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 402 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; 403 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; 404 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; 405 pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; 406 mmc-pwrseq = <&usdhc3_pwrseq>; 407 vmmc-supply = <®_usdhc3_vmmc>; 408 bus-width = <4>; 409 keep-power-in-suspend; 410 non-removable; 411 wakeup-source; 412 status = "okay"; 413}; 414 415&wdog3 { 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_wdog>; 418 fsl,ext-reset-output; 419 status = "okay"; 420}; 421 422&iomuxc { 423 pinctrl_flexcan1: flexcan1grp { 424 fsl,pins = < 425 MX93_PAD_PDM_CLK__CAN1_TX 0x139e 426 MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e 427 >; 428 }; 429 430 pinctrl_flexcan2: flexcan2grp { 431 fsl,pins = < 432 MX93_PAD_GPIO_IO25__CAN2_TX 0x139e 433 MX93_PAD_GPIO_IO27__CAN2_RX 0x139e 434 >; 435 }; 436 437 pinctrl_lpi2c1: lpi2c1grp { 438 fsl,pins = < 439 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 440 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 441 >; 442 }; 443 444 pinctrl_lpi2c2: lpi2c2grp { 445 fsl,pins = < 446 MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 447 MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 448 >; 449 }; 450 451 pinctrl_lpi2c3: lpi2c3grp { 452 fsl,pins = < 453 MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 454 MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 455 >; 456 }; 457 458 pinctrl_pcal6524: pcal6524grp { 459 fsl,pins = < 460 MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 461 >; 462 }; 463 464 pinctrl_fec: fecgrp { 465 fsl,pins = < 466 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 467 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 468 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 469 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 470 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 471 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 472 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e 473 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 474 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 475 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 476 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 477 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 478 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e 479 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 480 >; 481 }; 482 483 pinctrl_uart1: uart1grp { 484 fsl,pins = < 485 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 486 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 487 >; 488 }; 489 490 pinctrl_uart5: uart5grp { 491 fsl,pins = < 492 MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 493 MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 494 MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 495 MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 496 >; 497 }; 498 499 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 500 pinctrl_usdhc1: usdhc1grp { 501 fsl,pins = < 502 MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 503 MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 504 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 505 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 506 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 507 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 508 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 509 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 510 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 511 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 512 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 513 >; 514 }; 515 516 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 517 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 518 fsl,pins = < 519 MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 520 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 521 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 522 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 523 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 524 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 525 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 526 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 527 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 528 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 529 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 530 >; 531 }; 532 533 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 534 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 535 fsl,pins = < 536 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 537 MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 538 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 539 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 540 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 541 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 542 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 543 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 544 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 545 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 546 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 547 >; 548 }; 549 550 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 551 fsl,pins = < 552 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 553 >; 554 }; 555 556 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 557 fsl,pins = < 558 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 559 >; 560 }; 561 562 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 563 pinctrl_usdhc2: usdhc2grp { 564 fsl,pins = < 565 MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 566 MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 567 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 568 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 569 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 570 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 571 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 572 >; 573 }; 574 575 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 576 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 577 fsl,pins = < 578 MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 579 MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 580 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 581 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 582 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 583 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 584 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 585 >; 586 }; 587 588 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 589 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 590 fsl,pins = < 591 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 592 MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 593 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 594 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 595 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 596 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 597 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 598 >; 599 }; 600 601 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 602 pinctrl_usdhc3: usdhc3grp { 603 fsl,pins = < 604 MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 605 MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 606 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 607 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 608 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 609 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 610 >; 611 }; 612 613 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 614 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 615 fsl,pins = < 616 MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e 617 MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e 618 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e 619 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e 620 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e 621 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e 622 >; 623 }; 624 625 /* need to config the SION for data and cmd pad, refer to ERR052021 */ 626 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 627 fsl,pins = < 628 MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe 629 MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe 630 MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe 631 MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe 632 MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe 633 MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe 634 >; 635 }; 636 637 pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { 638 fsl,pins = < 639 MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e 640 MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e 641 MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e 642 MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e 643 MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e 644 MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e 645 >; 646 }; 647 648 pinctrl_usdhc3_wlan: usdhc3wlangrp { 649 fsl,pins = < 650 MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 651 >; 652 }; 653 654 pinctrl_wdog: wdoggrp { 655 fsl,pins = < 656 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 657 >; 658 }; 659}; 660