1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8ulp.dtsi" 9 10/ { 11 model = "NXP i.MX8ULP EVK"; 12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13 14 chosen { 15 stdout-path = &lpuart5; 16 }; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x0 0x80000000 0 0x80000000>; 21 }; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 linux,cma { 29 compatible = "shared-dma-pool"; 30 reusable; 31 size = <0 0x28000000>; 32 linux,cma-default; 33 }; 34 35 m33_reserved: noncacheable-section@a8600000 { 36 reg = <0 0xa8600000 0 0x1000000>; 37 no-map; 38 }; 39 40 rsc_table: rsc-table@1fff8000{ 41 reg = <0 0x1fff8000 0 0x1000>; 42 no-map; 43 }; 44 45 vdev0vring0: vdev0vring0@aff00000 { 46 reg = <0 0xaff00000 0 0x8000>; 47 no-map; 48 }; 49 50 vdev0vring1: vdev0vring1@aff08000 { 51 reg = <0 0xaff08000 0 0x8000>; 52 no-map; 53 }; 54 55 vdev1vring0: vdev1vring0@aff10000 { 56 reg = <0 0xaff10000 0 0x8000>; 57 no-map; 58 }; 59 60 vdev1vring1: vdev1vring1@aff18000 { 61 reg = <0 0xaff18000 0 0x8000>; 62 no-map; 63 }; 64 65 vdevbuffer: vdevbuffer@a8400000 { 66 compatible = "shared-dma-pool"; 67 reg = <0 0xa8400000 0 0x100000>; 68 no-map; 69 }; 70 }; 71 72 clock_ext_rmii: clock-ext-rmii { 73 compatible = "fixed-clock"; 74 clock-frequency = <50000000>; 75 clock-output-names = "ext_rmii_clk"; 76 #clock-cells = <0>; 77 }; 78 79 clock_ext_ts: clock-ext-ts { 80 compatible = "fixed-clock"; 81 /* External ts clock is 50MHZ from PHY on EVK board. */ 82 clock-frequency = <50000000>; 83 clock-output-names = "ext_ts_clk"; 84 #clock-cells = <0>; 85 }; 86}; 87 88&cm33 { 89 mbox-names = "tx", "rx", "rxdb"; 90 mboxes = <&mu 0 1>, 91 <&mu 1 1>, 92 <&mu 3 1>; 93 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 94 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 95 status = "okay"; 96}; 97 98&flexspi2 { 99 pinctrl-names = "default", "sleep"; 100 pinctrl-0 = <&pinctrl_flexspi2_ptd>; 101 pinctrl-1 = <&pinctrl_flexspi2_ptd>; 102 status = "okay"; 103 104 mx25uw51345gxdi00: flash@0 { 105 compatible = "jedec,spi-nor"; 106 reg = <0>; 107 spi-max-frequency = <200000000>; 108 spi-tx-bus-width = <8>; 109 spi-rx-bus-width = <8>; 110 }; 111}; 112 113&lpuart5 { 114 /* console */ 115 pinctrl-names = "default", "sleep"; 116 pinctrl-0 = <&pinctrl_lpuart5>; 117 pinctrl-1 = <&pinctrl_lpuart5>; 118 status = "okay"; 119}; 120 121&lpi2c7 { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 clock-frequency = <400000>; 125 pinctrl-names = "default", "sleep"; 126 pinctrl-0 = <&pinctrl_lpi2c7>; 127 pinctrl-1 = <&pinctrl_lpi2c7>; 128 status = "okay"; 129 130 pcal6408: gpio@21 { 131 compatible = "nxp,pcal9554b"; 132 reg = <0x21>; 133 gpio-controller; 134 #gpio-cells = <2>; 135 }; 136}; 137 138&usdhc0 { 139 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 140 pinctrl-0 = <&pinctrl_usdhc0>; 141 pinctrl-1 = <&pinctrl_usdhc0>; 142 pinctrl-2 = <&pinctrl_usdhc0>; 143 pinctrl-3 = <&pinctrl_usdhc0>; 144 non-removable; 145 bus-width = <8>; 146 status = "okay"; 147}; 148 149&fec { 150 pinctrl-names = "default", "sleep"; 151 pinctrl-0 = <&pinctrl_enet>; 152 pinctrl-1 = <&pinctrl_enet>; 153 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 154 <&pcc4 IMX8ULP_CLK_ENET>, 155 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, 156 <&clock_ext_rmii>; 157 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 158 assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; 159 assigned-clock-parents = <&clock_ext_ts>; 160 phy-mode = "rmii"; 161 phy-handle = <ðphy>; 162 status = "okay"; 163 164 mdio { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 ethphy: ethernet-phy@1 { 169 reg = <1>; 170 micrel,led-mode = <1>; 171 }; 172 }; 173}; 174 175&mu { 176 status = "okay"; 177}; 178 179&iomuxc1 { 180 pinctrl_enet: enetgrp { 181 fsl,pins = < 182 MX8ULP_PAD_PTE15__ENET0_MDC 0x43 183 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 184 MX8ULP_PAD_PTE17__ENET0_RXER 0x43 185 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 186 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 187 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 188 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 189 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 190 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 191 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 192 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 193 >; 194 }; 195 196 pinctrl_flexspi2_ptd: flexspi2ptdgrp { 197 fsl,pins = < 198 199 MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 200 MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 201 MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 202 MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 203 MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 204 MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 205 MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 206 MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 207 MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 208 MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 209 MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 210 >; 211 }; 212 213 pinctrl_lpuart5: lpuart5grp { 214 fsl,pins = < 215 MX8ULP_PAD_PTF14__LPUART5_TX 0x3 216 MX8ULP_PAD_PTF15__LPUART5_RX 0x3 217 >; 218 }; 219 220 pinctrl_lpi2c7: lpi2c7grp { 221 fsl,pins = < 222 MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 223 MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 224 >; 225 }; 226 227 pinctrl_usdhc0: usdhc0grp { 228 fsl,pins = < 229 MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 230 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 231 MX8ULP_PAD_PTD10__SDHC0_D0 0x3 232 MX8ULP_PAD_PTD9__SDHC0_D1 0x3 233 MX8ULP_PAD_PTD8__SDHC0_D2 0x3 234 MX8ULP_PAD_PTD7__SDHC0_D3 0x3 235 MX8ULP_PAD_PTD6__SDHC0_D4 0x3 236 MX8ULP_PAD_PTD5__SDHC0_D5 0x3 237 MX8ULP_PAD_PTD4__SDHC0_D6 0x3 238 MX8ULP_PAD_PTD3__SDHC0_D7 0x3 239 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 240 >; 241 }; 242}; 243