1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2020 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/clock/imx8-lpcg.h> 10#include <dt-bindings/firmware/imx/rsrc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/pinctrl/pads-imx8qxp.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec1; 24 ethernet1 = &fec2; 25 gpio0 = &lsio_gpio0; 26 gpio1 = &lsio_gpio1; 27 gpio2 = &lsio_gpio2; 28 gpio3 = &lsio_gpio3; 29 gpio4 = &lsio_gpio4; 30 gpio5 = &lsio_gpio5; 31 gpio6 = &lsio_gpio6; 32 gpio7 = &lsio_gpio7; 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mu0 = &lsio_mu0; 41 mu1 = &lsio_mu1; 42 mu2 = &lsio_mu2; 43 mu3 = &lsio_mu3; 44 mu4 = &lsio_mu4; 45 serial0 = &lpuart0; 46 serial1 = &lpuart1; 47 serial2 = &lpuart2; 48 serial3 = &lpuart3; 49 }; 50 51 cpus { 52 #address-cells = <2>; 53 #size-cells = <0>; 54 55 /* We have 1 clusters with 4 Cortex-A35 cores */ 56 A35_0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a35"; 59 reg = <0x0 0x0>; 60 enable-method = "psci"; 61 i-cache-size = <0x8000>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 d-cache-size = <0x8000>; 65 d-cache-line-size = <64>; 66 d-cache-sets = <128>; 67 next-level-cache = <&A35_L2>; 68 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 69 operating-points-v2 = <&a35_opp_table>; 70 #cooling-cells = <2>; 71 }; 72 73 A35_1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a35"; 76 reg = <0x0 0x1>; 77 enable-method = "psci"; 78 i-cache-size = <0x8000>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <256>; 81 d-cache-size = <0x8000>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&A35_L2>; 85 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 86 operating-points-v2 = <&a35_opp_table>; 87 #cooling-cells = <2>; 88 }; 89 90 A35_2: cpu@2 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a35"; 93 reg = <0x0 0x2>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A35_L2>; 102 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 103 operating-points-v2 = <&a35_opp_table>; 104 #cooling-cells = <2>; 105 }; 106 107 A35_3: cpu@3 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a35"; 110 reg = <0x0 0x3>; 111 enable-method = "psci"; 112 i-cache-size = <0x8000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&A35_L2>; 119 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 120 operating-points-v2 = <&a35_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A35_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-size = <0x80000>; 128 cache-line-size = <64>; 129 cache-sets = <1024>; 130 }; 131 }; 132 133 a35_opp_table: opp-table { 134 compatible = "operating-points-v2"; 135 opp-shared; 136 137 opp-900000000 { 138 opp-hz = /bits/ 64 <900000000>; 139 opp-microvolt = <1000000>; 140 clock-latency-ns = <150000>; 141 }; 142 143 opp-1200000000 { 144 opp-hz = /bits/ 64 <1200000000>; 145 opp-microvolt = <1100000>; 146 clock-latency-ns = <150000>; 147 opp-suspend; 148 }; 149 }; 150 151 gic: interrupt-controller@51a00000 { 152 compatible = "arm,gic-v3"; 153 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 154 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 155 #interrupt-cells = <3>; 156 interrupt-controller; 157 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 158 }; 159 160 reserved-memory { 161 #address-cells = <2>; 162 #size-cells = <2>; 163 ranges; 164 165 dsp_reserved: dsp@92400000 { 166 reg = <0 0x92400000 0 0x2000000>; 167 no-map; 168 }; 169 }; 170 171 pmu { 172 compatible = "arm,cortex-a35-pmu"; 173 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 174 }; 175 176 psci { 177 compatible = "arm,psci-1.0"; 178 method = "smc"; 179 }; 180 181 scu { 182 compatible = "fsl,imx-scu"; 183 mbox-names = "tx0", 184 "rx0", 185 "gip3"; 186 mboxes = <&lsio_mu1 0 0 187 &lsio_mu1 1 0 188 &lsio_mu1 3 3>; 189 190 pd: imx8qx-pd { 191 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 192 #power-domain-cells = <1>; 193 }; 194 195 clk: clock-controller { 196 compatible = "fsl,imx8qxp-clk"; 197 #clock-cells = <2>; 198 clocks = <&xtal32k &xtal24m>; 199 clock-names = "xtal_32KHz", "xtal_24Mhz"; 200 }; 201 202 iomuxc: pinctrl { 203 compatible = "fsl,imx8qxp-iomuxc"; 204 }; 205 206 ocotp: imx8qx-ocotp { 207 compatible = "fsl,imx8qxp-scu-ocotp"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 }; 211 212 scu_key: scu-key { 213 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 214 linux,keycodes = <KEY_POWER>; 215 status = "disabled"; 216 }; 217 218 rtc: rtc { 219 compatible = "fsl,imx8qxp-sc-rtc"; 220 }; 221 222 watchdog { 223 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 224 timeout-sec = <60>; 225 }; 226 227 tsens: thermal-sensor { 228 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 229 #thermal-sensor-cells = <1>; 230 }; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 236 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 237 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 238 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 239 }; 240 241 xtal32k: clock-xtal32k { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <32768>; 245 clock-output-names = "xtal_32KHz"; 246 }; 247 248 xtal24m: clock-xtal24m { 249 compatible = "fixed-clock"; 250 #clock-cells = <0>; 251 clock-frequency = <24000000>; 252 clock-output-names = "xtal_24MHz"; 253 }; 254 255 thermal_zones: thermal-zones { 256 cpu-thermal0 { 257 polling-delay-passive = <250>; 258 polling-delay = <2000>; 259 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 260 261 trips { 262 cpu_alert0: trip0 { 263 temperature = <107000>; 264 hysteresis = <2000>; 265 type = "passive"; 266 }; 267 268 cpu_crit0: trip1 { 269 temperature = <127000>; 270 hysteresis = <2000>; 271 type = "critical"; 272 }; 273 }; 274 275 cooling-maps { 276 map0 { 277 trip = <&cpu_alert0>; 278 cooling-device = 279 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 280 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 283 }; 284 }; 285 }; 286 }; 287 288 /* sorted in register address */ 289 #include "imx8-ss-img.dtsi" 290 #include "imx8-ss-adma.dtsi" 291 #include "imx8-ss-conn.dtsi" 292 #include "imx8-ss-ddr.dtsi" 293 #include "imx8-ss-lsio.dtsi" 294}; 295 296#include "imx8qxp-ss-img.dtsi" 297#include "imx8qxp-ss-adma.dtsi" 298#include "imx8qxp-ss-conn.dtsi" 299#include "imx8qxp-ss-lsio.dtsi" 300