1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7&dma_subsys { 8 uart4_lpcg: clock-controller@5a4a0000 { 9 compatible = "fsl,imx8qxp-lpcg"; 10 reg = <0x5a4a0000 0x10000>; 11 #clock-cells = <1>; 12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, 13 <&dma_ipg_clk>; 14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 15 clock-output-names = "uart4_lpcg_baud_clk", 16 "uart4_lpcg_ipg_clk"; 17 power-domains = <&pd IMX_SC_R_UART_4>; 18 }; 19 20 can1_lpcg: clock-controller@5ace0000 { 21 compatible = "fsl,imx8qxp-lpcg"; 22 reg = <0x5ace0000 0x10000>; 23 #clock-cells = <1>; 24 clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, 25 <&dma_ipg_clk>, <&dma_ipg_clk>; 26 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 27 clock-output-names = "can1_lpcg_pe_clk", 28 "can1_lpcg_ipg_clk", 29 "can1_lpcg_chi_clk"; 30 power-domains = <&pd IMX_SC_R_CAN_1>; 31 }; 32 33 can2_lpcg: clock-controller@5acf0000 { 34 compatible = "fsl,imx8qxp-lpcg"; 35 reg = <0x5acf0000 0x10000>; 36 #clock-cells = <1>; 37 clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, 38 <&dma_ipg_clk>, <&dma_ipg_clk>; 39 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 40 clock-output-names = "can2_lpcg_pe_clk", 41 "can2_lpcg_ipg_clk", 42 "can2_lpcg_chi_clk"; 43 power-domains = <&pd IMX_SC_R_CAN_2>; 44 }; 45}; 46 47&flexcan1 { 48 fsl,clk-source = /bits/ 8 <1>; 49}; 50 51&flexcan2 { 52 clocks = <&can1_lpcg 1>, 53 <&can1_lpcg 0>; 54 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; 55 fsl,clk-source = /bits/ 8 <1>; 56}; 57 58&flexcan3 { 59 clocks = <&can2_lpcg 1>, 60 <&can2_lpcg 0>; 61 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; 62 fsl,clk-source = /bits/ 8 <1>; 63}; 64 65&lpuart0 { 66 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 67}; 68 69&lpuart1 { 70 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 71}; 72 73&lpuart2 { 74 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 75}; 76 77&lpuart3 { 78 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; 79}; 80 81&i2c0 { 82 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 83}; 84 85&i2c1 { 86 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 87}; 88 89&i2c2 { 90 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 91}; 92 93&i2c3 { 94 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 95}; 96