1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/imx8mq.h> 15#include "imx8mq-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gpc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &ecspi1; 41 spi1 = &ecspi2; 42 spi2 = &ecspi3; 43 }; 44 45 ckil: clock-ckil { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 clock-output-names = "ckil"; 50 }; 51 52 osc_25m: clock-osc-25m { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 clock-output-names = "osc_25m"; 57 }; 58 59 osc_27m: clock-osc-27m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 clock-output-names = "osc_27m"; 64 }; 65 66 hdmi_phy_27m: clock-hdmi-phy-27m { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <27000000>; 70 clock-output-names = "hdmi_phy_27m"; 71 }; 72 73 clk_ext1: clock-ext1 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <133000000>; 77 clock-output-names = "clk_ext1"; 78 }; 79 80 clk_ext2: clock-ext2 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <133000000>; 84 clock-output-names = "clk_ext2"; 85 }; 86 87 clk_ext3: clock-ext3 { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <133000000>; 91 clock-output-names = "clk_ext3"; 92 }; 93 94 clk_ext4: clock-ext4 { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <133000000>; 98 clock-output-names = "clk_ext4"; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 A53_0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0>; 109 clock-latency = <61036>; /* two CLK32 periods */ 110 clocks = <&clk IMX8MQ_CLK_ARM>; 111 enable-method = "psci"; 112 i-cache-size = <0x8000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&A53_L2>; 119 operating-points-v2 = <&a53_opp_table>; 120 #cooling-cells = <2>; 121 nvmem-cells = <&cpu_speed_grade>; 122 nvmem-cell-names = "speed_grade"; 123 }; 124 125 A53_1: cpu@1 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x1>; 129 clock-latency = <61036>; /* two CLK32 periods */ 130 clocks = <&clk IMX8MQ_CLK_ARM>; 131 enable-method = "psci"; 132 i-cache-size = <0x8000>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <256>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 next-level-cache = <&A53_L2>; 139 operating-points-v2 = <&a53_opp_table>; 140 #cooling-cells = <2>; 141 }; 142 143 A53_2: cpu@2 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x2>; 147 clock-latency = <61036>; /* two CLK32 periods */ 148 clocks = <&clk IMX8MQ_CLK_ARM>; 149 enable-method = "psci"; 150 i-cache-size = <0x8000>; 151 i-cache-line-size = <64>; 152 i-cache-sets = <256>; 153 d-cache-size = <0x8000>; 154 d-cache-line-size = <64>; 155 d-cache-sets = <128>; 156 next-level-cache = <&A53_L2>; 157 operating-points-v2 = <&a53_opp_table>; 158 #cooling-cells = <2>; 159 }; 160 161 A53_3: cpu@3 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a53"; 164 reg = <0x3>; 165 clock-latency = <61036>; /* two CLK32 periods */ 166 clocks = <&clk IMX8MQ_CLK_ARM>; 167 enable-method = "psci"; 168 i-cache-size = <0x8000>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <256>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 next-level-cache = <&A53_L2>; 175 operating-points-v2 = <&a53_opp_table>; 176 #cooling-cells = <2>; 177 }; 178 179 A53_L2: l2-cache0 { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 cache-size = <0x100000>; 184 cache-line-size = <64>; 185 cache-sets = <1024>; 186 }; 187 }; 188 189 a53_opp_table: opp-table { 190 compatible = "operating-points-v2"; 191 opp-shared; 192 193 opp-800000000 { 194 opp-hz = /bits/ 64 <800000000>; 195 opp-microvolt = <900000>; 196 /* Industrial only */ 197 opp-supported-hw = <0xf>, <0x4>; 198 clock-latency-ns = <150000>; 199 opp-suspend; 200 }; 201 202 opp-1000000000 { 203 opp-hz = /bits/ 64 <1000000000>; 204 opp-microvolt = <900000>; 205 /* Consumer only */ 206 opp-supported-hw = <0xe>, <0x3>; 207 clock-latency-ns = <150000>; 208 opp-suspend; 209 }; 210 211 opp-1300000000 { 212 opp-hz = /bits/ 64 <1300000000>; 213 opp-microvolt = <1000000>; 214 opp-supported-hw = <0xc>, <0x4>; 215 clock-latency-ns = <150000>; 216 opp-suspend; 217 }; 218 219 opp-1500000000 { 220 opp-hz = /bits/ 64 <1500000000>; 221 opp-microvolt = <1000000>; 222 opp-supported-hw = <0x8>, <0x3>; 223 clock-latency-ns = <150000>; 224 opp-suspend; 225 }; 226 }; 227 228 pmu { 229 compatible = "arm,cortex-a53-pmu"; 230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-parent = <&gic>; 232 }; 233 234 psci { 235 compatible = "arm,psci-1.0"; 236 method = "smc"; 237 }; 238 239 thermal-zones { 240 cpu_thermal: cpu-thermal { 241 polling-delay-passive = <250>; 242 polling-delay = <2000>; 243 thermal-sensors = <&tmu 0>; 244 245 trips { 246 cpu_alert: cpu-alert { 247 temperature = <80000>; 248 hysteresis = <2000>; 249 type = "passive"; 250 }; 251 252 cpu-crit { 253 temperature = <90000>; 254 hysteresis = <2000>; 255 type = "critical"; 256 }; 257 }; 258 259 cooling-maps { 260 map0 { 261 trip = <&cpu_alert>; 262 cooling-device = 263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 267 }; 268 }; 269 }; 270 271 gpu-thermal { 272 polling-delay-passive = <250>; 273 polling-delay = <2000>; 274 thermal-sensors = <&tmu 1>; 275 276 trips { 277 gpu_alert: gpu-alert { 278 temperature = <80000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 gpu-crit { 284 temperature = <90000>; 285 hysteresis = <2000>; 286 type = "critical"; 287 }; 288 }; 289 290 cooling-maps { 291 map0 { 292 trip = <&gpu_alert>; 293 cooling-device = 294 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 295 }; 296 }; 297 }; 298 299 vpu-thermal { 300 polling-delay-passive = <250>; 301 polling-delay = <2000>; 302 thermal-sensors = <&tmu 2>; 303 304 trips { 305 vpu-crit { 306 temperature = <90000>; 307 hysteresis = <2000>; 308 type = "critical"; 309 }; 310 }; 311 }; 312 }; 313 314 timer { 315 compatible = "arm,armv8-timer"; 316 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 317 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 318 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 319 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 320 interrupt-parent = <&gic>; 321 arm,no-tick-in-suspend; 322 }; 323 324 soc: soc@0 { 325 compatible = "fsl,imx8mq-soc", "simple-bus"; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0x0 0x0 0x0 0x3e000000>; 329 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 330 nvmem-cells = <&imx8mq_uid>; 331 nvmem-cell-names = "soc_unique_id"; 332 333 aips1: bus@30000000 { /* AIPS1 */ 334 compatible = "fsl,aips-bus", "simple-bus"; 335 reg = <0x30000000 0x400000>; 336 #address-cells = <1>; 337 #size-cells = <1>; 338 ranges = <0x30000000 0x30000000 0x400000>; 339 340 sai1: sai@30010000 { 341 #sound-dai-cells = <0>; 342 compatible = "fsl,imx8mq-sai"; 343 reg = <0x30010000 0x10000>; 344 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 346 <&clk IMX8MQ_CLK_SAI1_ROOT>, 347 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 348 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 sai6: sai@30030000 { 355 #sound-dai-cells = <0>; 356 compatible = "fsl,imx8mq-sai"; 357 reg = <0x30030000 0x10000>; 358 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 360 <&clk IMX8MQ_CLK_SAI6_ROOT>, 361 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 362 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 363 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 sai5: sai@30040000 { 369 #sound-dai-cells = <0>; 370 compatible = "fsl,imx8mq-sai"; 371 reg = <0x30040000 0x10000>; 372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 374 <&clk IMX8MQ_CLK_SAI5_ROOT>, 375 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 376 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 377 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 sai4: sai@30050000 { 383 #sound-dai-cells = <0>; 384 compatible = "fsl,imx8mq-sai"; 385 reg = <0x30050000 0x10000>; 386 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 388 <&clk IMX8MQ_CLK_SAI4_ROOT>, 389 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 390 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 391 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 396 gpio1: gpio@30200000 { 397 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 398 reg = <0x30200000 0x10000>; 399 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 gpio-ranges = <&iomuxc 0 10 30>; 407 }; 408 409 gpio2: gpio@30210000 { 410 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 411 reg = <0x30210000 0x10000>; 412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 gpio-ranges = <&iomuxc 0 40 21>; 420 }; 421 422 gpio3: gpio@30220000 { 423 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 424 reg = <0x30220000 0x10000>; 425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 gpio-ranges = <&iomuxc 0 61 26>; 433 }; 434 435 gpio4: gpio@30230000 { 436 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 437 reg = <0x30230000 0x10000>; 438 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 gpio-ranges = <&iomuxc 0 87 32>; 446 }; 447 448 gpio5: gpio@30240000 { 449 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 450 reg = <0x30240000 0x10000>; 451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 gpio-ranges = <&iomuxc 0 119 30>; 459 }; 460 461 tmu: tmu@30260000 { 462 compatible = "fsl,imx8mq-tmu"; 463 reg = <0x30260000 0x10000>; 464 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 466 little-endian; 467 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 468 fsl,tmu-calibration = <0x00000000 0x00000023>, 469 <0x00000001 0x00000029>, 470 <0x00000002 0x0000002f>, 471 <0x00000003 0x00000035>, 472 <0x00000004 0x0000003d>, 473 <0x00000005 0x00000043>, 474 <0x00000006 0x0000004b>, 475 <0x00000007 0x00000051>, 476 <0x00000008 0x00000057>, 477 <0x00000009 0x0000005f>, 478 <0x0000000a 0x00000067>, 479 <0x0000000b 0x0000006f>, 480 481 <0x00010000 0x0000001b>, 482 <0x00010001 0x00000023>, 483 <0x00010002 0x0000002b>, 484 <0x00010003 0x00000033>, 485 <0x00010004 0x0000003b>, 486 <0x00010005 0x00000043>, 487 <0x00010006 0x0000004b>, 488 <0x00010007 0x00000055>, 489 <0x00010008 0x0000005d>, 490 <0x00010009 0x00000067>, 491 <0x0001000a 0x00000070>, 492 493 <0x00020000 0x00000017>, 494 <0x00020001 0x00000023>, 495 <0x00020002 0x0000002d>, 496 <0x00020003 0x00000037>, 497 <0x00020004 0x00000041>, 498 <0x00020005 0x0000004b>, 499 <0x00020006 0x00000057>, 500 <0x00020007 0x00000063>, 501 <0x00020008 0x0000006f>, 502 503 <0x00030000 0x00000015>, 504 <0x00030001 0x00000021>, 505 <0x00030002 0x0000002d>, 506 <0x00030003 0x00000039>, 507 <0x00030004 0x00000045>, 508 <0x00030005 0x00000053>, 509 <0x00030006 0x0000005f>, 510 <0x00030007 0x00000071>; 511 #thermal-sensor-cells = <1>; 512 }; 513 514 wdog1: watchdog@30280000 { 515 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 516 reg = <0x30280000 0x10000>; 517 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 519 status = "disabled"; 520 }; 521 522 wdog2: watchdog@30290000 { 523 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 524 reg = <0x30290000 0x10000>; 525 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 527 status = "disabled"; 528 }; 529 530 wdog3: watchdog@302a0000 { 531 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 532 reg = <0x302a0000 0x10000>; 533 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 535 status = "disabled"; 536 }; 537 538 sdma2: dma-controller@302c0000 { 539 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 540 reg = <0x302c0000 0x10000>; 541 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 543 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 544 clock-names = "ipg", "ahb"; 545 #dma-cells = <3>; 546 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 547 }; 548 549 lcdif: lcd-controller@30320000 { 550 compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif"; 551 reg = <0x30320000 0x10000>; 552 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 554 <&clk IMX8MQ_CLK_DISP_APB_ROOT>, 555 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>; 556 clock-names = "pix", "axi", "disp_axi"; 557 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 558 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 559 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 560 <&clk IMX8MQ_VIDEO_PLL1>; 561 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 562 <&clk IMX8MQ_VIDEO_PLL1>, 563 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 564 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 565 status = "disabled"; 566 567 port { 568 lcdif_mipi_dsi: endpoint { 569 remote-endpoint = <&mipi_dsi_lcdif_in>; 570 }; 571 }; 572 }; 573 574 iomuxc: pinctrl@30330000 { 575 compatible = "fsl,imx8mq-iomuxc"; 576 reg = <0x30330000 0x10000>; 577 }; 578 579 iomuxc_gpr: syscon@30340000 { 580 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd"; 581 reg = <0x30340000 0x10000>; 582 583 mux: mux-controller { 584 compatible = "mmio-mux"; 585 #mux-control-cells = <1>; 586 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 587 }; 588 }; 589 590 ocotp: efuse@30350000 { 591 compatible = "fsl,imx8mq-ocotp", "syscon"; 592 reg = <0x30350000 0x10000>; 593 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 594 #address-cells = <1>; 595 #size-cells = <1>; 596 597 /* 598 * The register address below maps to the MX8M 599 * Fusemap Description Table entries this way. 600 * Assuming 601 * reg = <ADDR SIZE>; 602 * then 603 * Fuse Address = (ADDR * 4) + 0x400 604 * Note that if SIZE is greater than 4, then 605 * each subsequent fuse is located at offset 606 * +0x10 in Fusemap Description Table (e.g. 607 * reg = <0x4 0x8> describes fuses 0x410 and 608 * 0x420). 609 */ 610 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ 611 reg = <0x4 0x8>; 612 }; 613 614 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 615 reg = <0x10 4>; 616 }; 617 618 fec_mac_address: mac-address@90 { /* 0x640 */ 619 reg = <0x90 6>; 620 }; 621 }; 622 623 anatop: clock-controller@30360000 { 624 compatible = "fsl,imx8mq-anatop"; 625 reg = <0x30360000 0x10000>; 626 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 627 #clock-cells = <1>; 628 }; 629 630 snvs: snvs@30370000 { 631 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 632 reg = <0x30370000 0x10000>; 633 634 snvs_rtc: snvs-rtc-lp{ 635 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 636 regmap =<&snvs>; 637 offset = <0x34>; 638 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 641 clock-names = "snvs-rtc"; 642 }; 643 644 snvs_pwrkey: snvs-powerkey { 645 compatible = "fsl,sec-v4.0-pwrkey"; 646 regmap = <&snvs>; 647 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 649 clock-names = "snvs-pwrkey"; 650 linux,keycode = <KEY_POWER>; 651 wakeup-source; 652 status = "disabled"; 653 }; 654 }; 655 656 clk: clock-controller@30380000 { 657 compatible = "fsl,imx8mq-ccm"; 658 reg = <0x30380000 0x10000>; 659 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 661 #clock-cells = <1>; 662 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 663 <&clk_ext1>, <&clk_ext2>, 664 <&clk_ext3>, <&clk_ext4>; 665 clock-names = "ckil", "osc_25m", "osc_27m", 666 "clk_ext1", "clk_ext2", 667 "clk_ext3", "clk_ext4"; 668 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 669 <&clk IMX8MQ_CLK_A53_CORE>, 670 <&clk IMX8MQ_CLK_NOC>, 671 <&clk IMX8MQ_CLK_AUDIO_AHB>, 672 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 673 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 674 <&clk IMX8MQ_AUDIO_PLL1>, 675 <&clk IMX8MQ_AUDIO_PLL2>; 676 assigned-clock-rates = <0>, <0>, 677 <800000000>, 678 <0>, 679 <0>, 680 <0>, 681 <786432000>, 682 <722534400>; 683 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 684 <&clk IMX8MQ_ARM_PLL_OUT>, 685 <0>, 686 <&clk IMX8MQ_SYS2_PLL_500M>, 687 <&clk IMX8MQ_AUDIO_PLL1>, 688 <&clk IMX8MQ_AUDIO_PLL2>; 689 }; 690 691 src: reset-controller@30390000 { 692 compatible = "fsl,imx8mq-src", "syscon"; 693 reg = <0x30390000 0x10000>; 694 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 695 #reset-cells = <1>; 696 }; 697 698 gpc: gpc@303a0000 { 699 compatible = "fsl,imx8mq-gpc"; 700 reg = <0x303a0000 0x10000>; 701 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-parent = <&gic>; 703 interrupt-controller; 704 #interrupt-cells = <3>; 705 706 pgc { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 pgc_mipi: power-domain@0 { 711 #power-domain-cells = <0>; 712 reg = <IMX8M_POWER_DOMAIN_MIPI>; 713 }; 714 715 /* 716 * As per comment in ATF source code: 717 * 718 * PCIE1 and PCIE2 share the 719 * same reset signal, if we 720 * power down PCIE2, PCIE1 721 * will be held in reset too. 722 * 723 * So instead of creating two 724 * separate power domains for 725 * PCIE1 and PCIE2 we create a 726 * link between both and use 727 * it as a shared PCIE power 728 * domain. 729 */ 730 pgc_pcie: power-domain@1 { 731 #power-domain-cells = <0>; 732 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 733 power-domains = <&pgc_pcie2>; 734 }; 735 736 pgc_otg1: power-domain@2 { 737 #power-domain-cells = <0>; 738 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 739 }; 740 741 pgc_otg2: power-domain@3 { 742 #power-domain-cells = <0>; 743 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 744 }; 745 746 pgc_ddr1: power-domain@4 { 747 #power-domain-cells = <0>; 748 reg = <IMX8M_POWER_DOMAIN_DDR1>; 749 }; 750 751 pgc_gpu: power-domain@5 { 752 #power-domain-cells = <0>; 753 reg = <IMX8M_POWER_DOMAIN_GPU>; 754 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 755 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 756 <&clk IMX8MQ_CLK_GPU_AXI>, 757 <&clk IMX8MQ_CLK_GPU_AHB>; 758 }; 759 760 pgc_vpu: power-domain@6 { 761 #power-domain-cells = <0>; 762 reg = <IMX8M_POWER_DOMAIN_VPU>; 763 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, 764 <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 765 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 766 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 767 <&clk IMX8MQ_CLK_VPU_G2>, 768 <&clk IMX8MQ_CLK_VPU_BUS>, 769 <&clk IMX8MQ_VPU_PLL_BYPASS>; 770 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 771 <&clk IMX8MQ_VPU_PLL_OUT>, 772 <&clk IMX8MQ_SYS1_PLL_800M>, 773 <&clk IMX8MQ_VPU_PLL>; 774 assigned-clock-rates = <600000000>, 775 <300000000>, 776 <800000000>, 777 <0>; 778 }; 779 780 pgc_disp: power-domain@7 { 781 #power-domain-cells = <0>; 782 reg = <IMX8M_POWER_DOMAIN_DISP>; 783 }; 784 785 pgc_mipi_csi1: power-domain@8 { 786 #power-domain-cells = <0>; 787 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 788 }; 789 790 pgc_mipi_csi2: power-domain@9 { 791 #power-domain-cells = <0>; 792 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 793 }; 794 795 pgc_pcie2: power-domain@a { 796 #power-domain-cells = <0>; 797 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 798 }; 799 }; 800 }; 801 }; 802 803 aips2: bus@30400000 { /* AIPS2 */ 804 compatible = "fsl,aips-bus", "simple-bus"; 805 reg = <0x30400000 0x400000>; 806 #address-cells = <1>; 807 #size-cells = <1>; 808 ranges = <0x30400000 0x30400000 0x400000>; 809 810 pwm1: pwm@30660000 { 811 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 812 reg = <0x30660000 0x10000>; 813 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 815 <&clk IMX8MQ_CLK_PWM1_ROOT>; 816 clock-names = "ipg", "per"; 817 #pwm-cells = <3>; 818 status = "disabled"; 819 }; 820 821 pwm2: pwm@30670000 { 822 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 823 reg = <0x30670000 0x10000>; 824 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 826 <&clk IMX8MQ_CLK_PWM2_ROOT>; 827 clock-names = "ipg", "per"; 828 #pwm-cells = <3>; 829 status = "disabled"; 830 }; 831 832 pwm3: pwm@30680000 { 833 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 834 reg = <0x30680000 0x10000>; 835 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 837 <&clk IMX8MQ_CLK_PWM3_ROOT>; 838 clock-names = "ipg", "per"; 839 #pwm-cells = <3>; 840 status = "disabled"; 841 }; 842 843 pwm4: pwm@30690000 { 844 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 845 reg = <0x30690000 0x10000>; 846 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 848 <&clk IMX8MQ_CLK_PWM4_ROOT>; 849 clock-names = "ipg", "per"; 850 #pwm-cells = <3>; 851 status = "disabled"; 852 }; 853 854 system_counter: timer@306a0000 { 855 compatible = "nxp,sysctr-timer"; 856 reg = <0x306a0000 0x20000>; 857 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&osc_25m>; 859 clock-names = "per"; 860 }; 861 }; 862 863 aips3: bus@30800000 { /* AIPS3 */ 864 compatible = "fsl,aips-bus", "simple-bus"; 865 reg = <0x30800000 0x400000>; 866 #address-cells = <1>; 867 #size-cells = <1>; 868 ranges = <0x30800000 0x30800000 0x400000>, 869 <0x08000000 0x08000000 0x10000000>; 870 871 spdif1: spdif@30810000 { 872 compatible = "fsl,imx35-spdif"; 873 reg = <0x30810000 0x10000>; 874 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 876 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 877 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 878 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 879 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 880 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 881 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 882 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 883 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 884 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 885 clock-names = "core", "rxtx0", 886 "rxtx1", "rxtx2", 887 "rxtx3", "rxtx4", 888 "rxtx5", "rxtx6", 889 "rxtx7", "spba"; 890 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 891 dma-names = "rx", "tx"; 892 status = "disabled"; 893 }; 894 895 ecspi1: spi@30820000 { 896 #address-cells = <1>; 897 #size-cells = <0>; 898 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 899 reg = <0x30820000 0x10000>; 900 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 902 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 903 clock-names = "ipg", "per"; 904 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 905 dma-names = "rx", "tx"; 906 status = "disabled"; 907 }; 908 909 ecspi2: spi@30830000 { 910 #address-cells = <1>; 911 #size-cells = <0>; 912 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 913 reg = <0x30830000 0x10000>; 914 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 916 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 917 clock-names = "ipg", "per"; 918 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 919 dma-names = "rx", "tx"; 920 status = "disabled"; 921 }; 922 923 ecspi3: spi@30840000 { 924 #address-cells = <1>; 925 #size-cells = <0>; 926 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 927 reg = <0x30840000 0x10000>; 928 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 930 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 931 clock-names = "ipg", "per"; 932 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 933 dma-names = "rx", "tx"; 934 status = "disabled"; 935 }; 936 937 uart1: serial@30860000 { 938 compatible = "fsl,imx8mq-uart", 939 "fsl,imx6q-uart"; 940 reg = <0x30860000 0x10000>; 941 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 943 <&clk IMX8MQ_CLK_UART1_ROOT>; 944 clock-names = "ipg", "per"; 945 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 946 dma-names = "rx", "tx"; 947 status = "disabled"; 948 }; 949 950 uart3: serial@30880000 { 951 compatible = "fsl,imx8mq-uart", 952 "fsl,imx6q-uart"; 953 reg = <0x30880000 0x10000>; 954 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 956 <&clk IMX8MQ_CLK_UART3_ROOT>; 957 clock-names = "ipg", "per"; 958 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 959 dma-names = "rx", "tx"; 960 status = "disabled"; 961 }; 962 963 uart2: serial@30890000 { 964 compatible = "fsl,imx8mq-uart", 965 "fsl,imx6q-uart"; 966 reg = <0x30890000 0x10000>; 967 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 969 <&clk IMX8MQ_CLK_UART2_ROOT>; 970 clock-names = "ipg", "per"; 971 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 972 dma-names = "rx", "tx"; 973 status = "disabled"; 974 }; 975 976 spdif2: spdif@308a0000 { 977 compatible = "fsl,imx35-spdif"; 978 reg = <0x308a0000 0x10000>; 979 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 981 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 982 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 983 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 984 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 985 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 986 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 987 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 988 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 989 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 990 clock-names = "core", "rxtx0", 991 "rxtx1", "rxtx2", 992 "rxtx3", "rxtx4", 993 "rxtx5", "rxtx6", 994 "rxtx7", "spba"; 995 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 996 dma-names = "rx", "tx"; 997 status = "disabled"; 998 }; 999 1000 sai2: sai@308b0000 { 1001 #sound-dai-cells = <0>; 1002 compatible = "fsl,imx8mq-sai"; 1003 reg = <0x308b0000 0x10000>; 1004 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 1006 <&clk IMX8MQ_CLK_SAI2_ROOT>, 1007 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1008 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1009 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 1010 dma-names = "rx", "tx"; 1011 status = "disabled"; 1012 }; 1013 1014 sai3: sai@308c0000 { 1015 #sound-dai-cells = <0>; 1016 compatible = "fsl,imx8mq-sai"; 1017 reg = <0x308c0000 0x10000>; 1018 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1019 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 1020 <&clk IMX8MQ_CLK_SAI3_ROOT>, 1021 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1022 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1023 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 1024 dma-names = "rx", "tx"; 1025 status = "disabled"; 1026 }; 1027 1028 crypto: crypto@30900000 { 1029 compatible = "fsl,sec-v4.0"; 1030 #address-cells = <1>; 1031 #size-cells = <1>; 1032 reg = <0x30900000 0x40000>; 1033 ranges = <0 0x30900000 0x40000>; 1034 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&clk IMX8MQ_CLK_AHB>, 1036 <&clk IMX8MQ_CLK_IPG_ROOT>; 1037 clock-names = "aclk", "ipg"; 1038 1039 sec_jr0: jr@1000 { 1040 compatible = "fsl,sec-v4.0-job-ring"; 1041 reg = <0x1000 0x1000>; 1042 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1043 status = "disabled"; 1044 }; 1045 1046 sec_jr1: jr@2000 { 1047 compatible = "fsl,sec-v4.0-job-ring"; 1048 reg = <0x2000 0x1000>; 1049 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1050 }; 1051 1052 sec_jr2: jr@3000 { 1053 compatible = "fsl,sec-v4.0-job-ring"; 1054 reg = <0x3000 0x1000>; 1055 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1056 }; 1057 }; 1058 1059 mipi_dsi: dsi@30a00000 { 1060 compatible = "fsl,imx8mq-nwl-dsi"; 1061 reg = <0x30a00000 0x300>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1065 <&clk IMX8MQ_CLK_DSI_AHB>, 1066 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1067 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1068 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1069 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1070 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 1071 <&clk IMX8MQ_CLK_DSI_CORE>, 1072 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 1073 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 1074 <&clk IMX8MQ_SYS1_PLL_266M>; 1075 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 1076 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1077 mux-controls = <&mux 0>; 1078 power-domains = <&pgc_mipi>; 1079 phys = <&dphy>; 1080 phy-names = "dphy"; 1081 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1082 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1083 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1084 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1085 reset-names = "byte", "dpi", "esc", "pclk"; 1086 status = "disabled"; 1087 1088 ports { 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 port@0 { 1093 reg = <0>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 mipi_dsi_lcdif_in: endpoint@0 { 1097 reg = <0>; 1098 remote-endpoint = <&lcdif_mipi_dsi>; 1099 }; 1100 }; 1101 }; 1102 }; 1103 1104 dphy: dphy@30a00300 { 1105 compatible = "fsl,imx8mq-mipi-dphy"; 1106 reg = <0x30a00300 0x100>; 1107 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1108 clock-names = "phy_ref"; 1109 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 1110 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 1111 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1112 <&clk IMX8MQ_VIDEO_PLL1>; 1113 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 1114 <&clk IMX8MQ_VIDEO_PLL1>, 1115 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1116 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; 1117 #phy-cells = <0>; 1118 power-domains = <&pgc_mipi>; 1119 status = "disabled"; 1120 }; 1121 1122 i2c1: i2c@30a20000 { 1123 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1124 reg = <0x30a20000 0x10000>; 1125 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c2: i2c@30a30000 { 1133 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1134 reg = <0x30a30000 0x10000>; 1135 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 i2c3: i2c@30a40000 { 1143 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1144 reg = <0x30a40000 0x10000>; 1145 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 i2c4: i2c@30a50000 { 1153 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1154 reg = <0x30a50000 0x10000>; 1155 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 uart4: serial@30a60000 { 1163 compatible = "fsl,imx8mq-uart", 1164 "fsl,imx6q-uart"; 1165 reg = <0x30a60000 0x10000>; 1166 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1168 <&clk IMX8MQ_CLK_UART4_ROOT>; 1169 clock-names = "ipg", "per"; 1170 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1171 dma-names = "rx", "tx"; 1172 status = "disabled"; 1173 }; 1174 1175 mipi_csi1: csi@30a70000 { 1176 compatible = "fsl,imx8mq-mipi-csi2"; 1177 reg = <0x30a70000 0x1000>; 1178 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1179 <&clk IMX8MQ_CLK_CSI1_ESC>, 1180 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; 1181 clock-names = "core", "esc", "ui"; 1182 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1183 <&clk IMX8MQ_CLK_CSI1_PHY_REF>, 1184 <&clk IMX8MQ_CLK_CSI1_ESC>; 1185 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1186 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1187 <&clk IMX8MQ_SYS2_PLL_1000M>, 1188 <&clk IMX8MQ_SYS1_PLL_800M>; 1189 power-domains = <&pgc_mipi_csi1>; 1190 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, 1191 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, 1192 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; 1193 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; 1194 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; 1195 interconnect-names = "dram"; 1196 status = "disabled"; 1197 1198 ports { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 1202 port@1 { 1203 reg = <1>; 1204 1205 csi1_mipi_ep: endpoint { 1206 remote-endpoint = <&csi1_ep>; 1207 }; 1208 }; 1209 }; 1210 }; 1211 1212 csi1: csi@30a90000 { 1213 compatible = "fsl,imx8mq-csi"; 1214 reg = <0x30a90000 0x10000>; 1215 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; 1217 clock-names = "mclk"; 1218 status = "disabled"; 1219 1220 port { 1221 csi1_ep: endpoint { 1222 remote-endpoint = <&csi1_mipi_ep>; 1223 }; 1224 }; 1225 }; 1226 1227 mipi_csi2: csi@30b60000 { 1228 compatible = "fsl,imx8mq-mipi-csi2"; 1229 reg = <0x30b60000 0x1000>; 1230 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1231 <&clk IMX8MQ_CLK_CSI2_ESC>, 1232 <&clk IMX8MQ_CLK_CSI2_PHY_REF>; 1233 clock-names = "core", "esc", "ui"; 1234 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1235 <&clk IMX8MQ_CLK_CSI2_PHY_REF>, 1236 <&clk IMX8MQ_CLK_CSI2_ESC>; 1237 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1238 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1239 <&clk IMX8MQ_SYS2_PLL_1000M>, 1240 <&clk IMX8MQ_SYS1_PLL_800M>; 1241 power-domains = <&pgc_mipi_csi2>; 1242 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, 1243 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, 1244 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; 1245 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; 1246 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; 1247 interconnect-names = "dram"; 1248 status = "disabled"; 1249 1250 ports { 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 1254 port@1 { 1255 reg = <1>; 1256 1257 csi2_mipi_ep: endpoint { 1258 remote-endpoint = <&csi2_ep>; 1259 }; 1260 }; 1261 }; 1262 }; 1263 1264 csi2: csi@30b80000 { 1265 compatible = "fsl,imx8mq-csi"; 1266 reg = <0x30b80000 0x10000>; 1267 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; 1269 clock-names = "mclk"; 1270 status = "disabled"; 1271 1272 port { 1273 csi2_ep: endpoint { 1274 remote-endpoint = <&csi2_mipi_ep>; 1275 }; 1276 }; 1277 }; 1278 1279 mu: mailbox@30aa0000 { 1280 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1281 reg = <0x30aa0000 0x10000>; 1282 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1284 #mbox-cells = <2>; 1285 }; 1286 1287 usdhc1: mmc@30b40000 { 1288 compatible = "fsl,imx8mq-usdhc", 1289 "fsl,imx7d-usdhc"; 1290 reg = <0x30b40000 0x10000>; 1291 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1293 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1294 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1295 clock-names = "ipg", "ahb", "per"; 1296 fsl,tuning-start-tap = <20>; 1297 fsl,tuning-step = <2>; 1298 bus-width = <4>; 1299 status = "disabled"; 1300 }; 1301 1302 usdhc2: mmc@30b50000 { 1303 compatible = "fsl,imx8mq-usdhc", 1304 "fsl,imx7d-usdhc"; 1305 reg = <0x30b50000 0x10000>; 1306 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1308 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1309 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1310 clock-names = "ipg", "ahb", "per"; 1311 fsl,tuning-start-tap = <20>; 1312 fsl,tuning-step = <2>; 1313 bus-width = <4>; 1314 status = "disabled"; 1315 }; 1316 1317 qspi0: spi@30bb0000 { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1321 reg = <0x30bb0000 0x10000>, 1322 <0x08000000 0x10000000>; 1323 reg-names = "QuadSPI", "QuadSPI-memory"; 1324 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1326 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1327 clock-names = "qspi_en", "qspi"; 1328 status = "disabled"; 1329 }; 1330 1331 sdma1: dma-controller@30bd0000 { 1332 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1333 reg = <0x30bd0000 0x10000>; 1334 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1336 <&clk IMX8MQ_CLK_AHB>; 1337 clock-names = "ipg", "ahb"; 1338 #dma-cells = <3>; 1339 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1340 }; 1341 1342 fec1: ethernet@30be0000 { 1343 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1344 reg = <0x30be0000 0x10000>; 1345 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1350 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1351 <&clk IMX8MQ_CLK_ENET_TIMER>, 1352 <&clk IMX8MQ_CLK_ENET_REF>, 1353 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1354 clock-names = "ipg", "ahb", "ptp", 1355 "enet_clk_ref", "enet_out"; 1356 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, 1357 <&clk IMX8MQ_CLK_ENET_TIMER>, 1358 <&clk IMX8MQ_CLK_ENET_REF>, 1359 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1360 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1361 <&clk IMX8MQ_SYS2_PLL_100M>, 1362 <&clk IMX8MQ_SYS2_PLL_125M>, 1363 <&clk IMX8MQ_SYS2_PLL_50M>; 1364 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1365 fsl,num-tx-queues = <3>; 1366 fsl,num-rx-queues = <3>; 1367 nvmem-cells = <&fec_mac_address>; 1368 nvmem-cell-names = "mac-address"; 1369 fsl,stop-mode = <&iomuxc_gpr 0x10 3>; 1370 status = "disabled"; 1371 }; 1372 }; 1373 1374 noc: interconnect@32700000 { 1375 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; 1376 reg = <0x32700000 0x100000>; 1377 clocks = <&clk IMX8MQ_CLK_NOC>; 1378 fsl,ddrc = <&ddrc>; 1379 #interconnect-cells = <1>; 1380 operating-points-v2 = <&noc_opp_table>; 1381 1382 noc_opp_table: opp-table { 1383 compatible = "operating-points-v2"; 1384 1385 opp-133000000 { 1386 opp-hz = /bits/ 64 <133333333>; 1387 }; 1388 1389 opp-400000000 { 1390 opp-hz = /bits/ 64 <400000000>; 1391 }; 1392 1393 opp-800000000 { 1394 opp-hz = /bits/ 64 <800000000>; 1395 }; 1396 }; 1397 }; 1398 1399 aips4: bus@32c00000 { /* AIPS4 */ 1400 compatible = "fsl,aips-bus", "simple-bus"; 1401 reg = <0x32c00000 0x400000>; 1402 #address-cells = <1>; 1403 #size-cells = <1>; 1404 ranges = <0x32c00000 0x32c00000 0x400000>; 1405 1406 irqsteer: interrupt-controller@32e2d000 { 1407 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1408 reg = <0x32e2d000 0x1000>; 1409 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1410 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1411 clock-names = "ipg"; 1412 fsl,channel = <0>; 1413 fsl,num-irqs = <64>; 1414 interrupt-controller; 1415 #interrupt-cells = <1>; 1416 }; 1417 }; 1418 1419 gpu: gpu@38000000 { 1420 compatible = "vivante,gc"; 1421 reg = <0x38000000 0x40000>; 1422 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1424 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1425 <&clk IMX8MQ_CLK_GPU_AXI>, 1426 <&clk IMX8MQ_CLK_GPU_AHB>; 1427 clock-names = "core", "shader", "bus", "reg"; 1428 #cooling-cells = <2>; 1429 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1430 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1431 <&clk IMX8MQ_CLK_GPU_AXI>, 1432 <&clk IMX8MQ_CLK_GPU_AHB>, 1433 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1434 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1435 <&clk IMX8MQ_GPU_PLL_OUT>, 1436 <&clk IMX8MQ_GPU_PLL_OUT>, 1437 <&clk IMX8MQ_GPU_PLL_OUT>, 1438 <&clk IMX8MQ_GPU_PLL>; 1439 assigned-clock-rates = <800000000>, <800000000>, 1440 <800000000>, <800000000>, <0>; 1441 power-domains = <&pgc_gpu>; 1442 }; 1443 1444 usb_dwc3_0: usb@38100000 { 1445 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1446 reg = <0x38100000 0x10000>; 1447 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1448 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1449 <&clk IMX8MQ_CLK_32K>; 1450 clock-names = "bus_early", "ref", "suspend"; 1451 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1452 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1453 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1454 <&clk IMX8MQ_SYS1_PLL_100M>; 1455 assigned-clock-rates = <500000000>, <100000000>; 1456 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1457 phys = <&usb3_phy0>, <&usb3_phy0>; 1458 phy-names = "usb2-phy", "usb3-phy"; 1459 power-domains = <&pgc_otg1>; 1460 status = "disabled"; 1461 }; 1462 1463 usb3_phy0: usb-phy@381f0040 { 1464 compatible = "fsl,imx8mq-usb-phy"; 1465 reg = <0x381f0040 0x40>; 1466 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1467 clock-names = "phy"; 1468 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1469 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1470 assigned-clock-rates = <100000000>; 1471 #phy-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 usb_dwc3_1: usb@38200000 { 1476 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1477 reg = <0x38200000 0x10000>; 1478 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1479 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1480 <&clk IMX8MQ_CLK_32K>; 1481 clock-names = "bus_early", "ref", "suspend"; 1482 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1483 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1484 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1485 <&clk IMX8MQ_SYS1_PLL_100M>; 1486 assigned-clock-rates = <500000000>, <100000000>; 1487 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1488 phys = <&usb3_phy1>, <&usb3_phy1>; 1489 phy-names = "usb2-phy", "usb3-phy"; 1490 power-domains = <&pgc_otg2>; 1491 status = "disabled"; 1492 }; 1493 1494 usb3_phy1: usb-phy@382f0040 { 1495 compatible = "fsl,imx8mq-usb-phy"; 1496 reg = <0x382f0040 0x40>; 1497 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1498 clock-names = "phy"; 1499 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1500 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1501 assigned-clock-rates = <100000000>; 1502 #phy-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 vpu_g1: video-codec@38300000 { 1507 compatible = "nxp,imx8mq-vpu-g1"; 1508 reg = <0x38300000 0x10000>; 1509 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1510 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; 1511 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; 1512 }; 1513 1514 vpu_g2: video-codec@38310000 { 1515 compatible = "nxp,imx8mq-vpu-g2"; 1516 reg = <0x38310000 0x10000>; 1517 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1519 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; 1520 }; 1521 1522 vpu_blk_ctrl: blk-ctrl@38320000 { 1523 compatible = "fsl,imx8mq-vpu-blk-ctrl"; 1524 reg = <0x38320000 0x100>; 1525 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 1526 power-domain-names = "bus", "g1", "g2"; 1527 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1528 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1529 clock-names = "g1", "g2"; 1530 #power-domain-cells = <1>; 1531 }; 1532 1533 pcie0: pcie@33800000 { 1534 compatible = "fsl,imx8mq-pcie"; 1535 reg = <0x33800000 0x400000>, 1536 <0x1ff00000 0x80000>; 1537 reg-names = "dbi", "config"; 1538 #address-cells = <3>; 1539 #size-cells = <2>; 1540 device_type = "pci"; 1541 bus-range = <0x00 0xff>; 1542 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1543 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1544 num-lanes = <1>; 1545 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1546 interrupt-names = "msi"; 1547 #interrupt-cells = <1>; 1548 interrupt-map-mask = <0 0 0 0x7>; 1549 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1550 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1551 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1552 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1553 fsl,max-link-speed = <2>; 1554 linux,pci-domain = <0>; 1555 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 1556 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1557 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1558 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1559 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1560 power-domains = <&pgc_pcie>; 1561 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1562 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1563 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1564 reset-names = "pciephy", "apps", "turnoff"; 1565 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, 1566 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1567 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1568 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1569 <&clk IMX8MQ_SYS2_PLL_100M>, 1570 <&clk IMX8MQ_SYS1_PLL_80M>; 1571 assigned-clock-rates = <250000000>, <100000000>, 1572 <10000000>; 1573 status = "disabled"; 1574 }; 1575 1576 pcie1: pcie@33c00000 { 1577 compatible = "fsl,imx8mq-pcie"; 1578 reg = <0x33c00000 0x400000>, 1579 <0x27f00000 0x80000>; 1580 reg-names = "dbi", "config"; 1581 #address-cells = <3>; 1582 #size-cells = <2>; 1583 device_type = "pci"; 1584 bus-range = <0x00 0xff>; 1585 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1586 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1587 num-lanes = <1>; 1588 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1589 interrupt-names = "msi"; 1590 #interrupt-cells = <1>; 1591 interrupt-map-mask = <0 0 0 0x7>; 1592 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1593 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1594 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1595 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1596 fsl,max-link-speed = <2>; 1597 linux,pci-domain = <1>; 1598 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1599 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1600 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1601 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1602 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1603 power-domains = <&pgc_pcie>; 1604 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1605 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1606 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1607 reset-names = "pciephy", "apps", "turnoff"; 1608 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1609 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1610 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1611 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1612 <&clk IMX8MQ_SYS2_PLL_100M>, 1613 <&clk IMX8MQ_SYS1_PLL_80M>; 1614 assigned-clock-rates = <250000000>, <100000000>, 1615 <10000000>; 1616 status = "disabled"; 1617 }; 1618 1619 pcie1_ep: pcie-ep@33c00000 { 1620 compatible = "fsl,imx8mq-pcie-ep"; 1621 reg = <0x33c00000 0x000400000>, 1622 <0x20000000 0x08000000>; 1623 reg-names = "dbi", "addr_space"; 1624 num-lanes = <1>; 1625 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1626 interrupt-names = "dma"; 1627 fsl,max-link-speed = <2>; 1628 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1629 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1630 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1631 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1632 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1633 power-domains = <&pgc_pcie>; 1634 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1635 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1636 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1637 reset-names = "pciephy", "apps", "turnoff"; 1638 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1639 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1640 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1641 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1642 <&clk IMX8MQ_SYS2_PLL_100M>, 1643 <&clk IMX8MQ_SYS1_PLL_80M>; 1644 assigned-clock-rates = <250000000>, <100000000>, 1645 <10000000>; 1646 num-ib-windows = <4>; 1647 num-ob-windows = <4>; 1648 status = "disabled"; 1649 }; 1650 1651 gic: interrupt-controller@38800000 { 1652 compatible = "arm,gic-v3"; 1653 reg = <0x38800000 0x10000>, /* GIC Dist */ 1654 <0x38880000 0xc0000>, /* GICR */ 1655 <0x31000000 0x2000>, /* GICC */ 1656 <0x31010000 0x2000>, /* GICV */ 1657 <0x31020000 0x2000>; /* GICH */ 1658 #interrupt-cells = <3>; 1659 interrupt-controller; 1660 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1661 interrupt-parent = <&gic>; 1662 }; 1663 1664 ddrc: memory-controller@3d400000 { 1665 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1666 reg = <0x3d400000 0x400000>; 1667 clock-names = "core", "pll", "alt", "apb"; 1668 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1669 <&clk IMX8MQ_DRAM_PLL_OUT>, 1670 <&clk IMX8MQ_CLK_DRAM_ALT>, 1671 <&clk IMX8MQ_CLK_DRAM_APB>; 1672 status = "disabled"; 1673 }; 1674 1675 ddr-pmu@3d800000 { 1676 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1677 reg = <0x3d800000 0x400000>; 1678 interrupt-parent = <&gic>; 1679 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1680 }; 1681 }; 1682}; 1683