1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "imx8mq-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gpc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec1; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 i2c3 = &i2c4; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 ckil: clock-ckil { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <32768>; 48 clock-output-names = "ckil"; 49 }; 50 51 osc_25m: clock-osc-25m { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <25000000>; 55 clock-output-names = "osc_25m"; 56 }; 57 58 osc_27m: clock-osc-27m { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 clock-frequency = <27000000>; 62 clock-output-names = "osc_27m"; 63 }; 64 65 clk_ext1: clock-ext1 { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <133000000>; 69 clock-output-names = "clk_ext1"; 70 }; 71 72 clk_ext2: clock-ext2 { 73 compatible = "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <133000000>; 76 clock-output-names = "clk_ext2"; 77 }; 78 79 clk_ext3: clock-ext3 { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <133000000>; 83 clock-output-names = "clk_ext3"; 84 }; 85 86 clk_ext4: clock-ext4 { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 clock-frequency= <133000000>; 90 clock-output-names = "clk_ext4"; 91 }; 92 93 cpus { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 A53_0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0>; 101 clock-latency = <61036>; /* two CLK32 periods */ 102 clocks = <&clk IMX8MQ_CLK_ARM>; 103 enable-method = "psci"; 104 next-level-cache = <&A53_L2>; 105 operating-points-v2 = <&a53_opp_table>; 106 #cooling-cells = <2>; 107 nvmem-cells = <&cpu_speed_grade>; 108 nvmem-cell-names = "speed_grade"; 109 }; 110 111 A53_1: cpu@1 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x1>; 115 clock-latency = <61036>; /* two CLK32 periods */ 116 clocks = <&clk IMX8MQ_CLK_ARM>; 117 enable-method = "psci"; 118 next-level-cache = <&A53_L2>; 119 operating-points-v2 = <&a53_opp_table>; 120 #cooling-cells = <2>; 121 }; 122 123 A53_2: cpu@2 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53"; 126 reg = <0x2>; 127 clock-latency = <61036>; /* two CLK32 periods */ 128 clocks = <&clk IMX8MQ_CLK_ARM>; 129 enable-method = "psci"; 130 next-level-cache = <&A53_L2>; 131 operating-points-v2 = <&a53_opp_table>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_3: cpu@3 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x3>; 139 clock-latency = <61036>; /* two CLK32 periods */ 140 clocks = <&clk IMX8MQ_CLK_ARM>; 141 enable-method = "psci"; 142 next-level-cache = <&A53_L2>; 143 operating-points-v2 = <&a53_opp_table>; 144 #cooling-cells = <2>; 145 }; 146 147 A53_L2: l2-cache0 { 148 compatible = "cache"; 149 }; 150 }; 151 152 a53_opp_table: opp-table { 153 compatible = "operating-points-v2"; 154 opp-shared; 155 156 opp-800000000 { 157 opp-hz = /bits/ 64 <800000000>; 158 opp-microvolt = <900000>; 159 /* Industrial only */ 160 opp-supported-hw = <0xf>, <0x4>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1000000000 { 166 opp-hz = /bits/ 64 <1000000000>; 167 opp-microvolt = <900000>; 168 /* Consumer only */ 169 opp-supported-hw = <0xe>, <0x3>; 170 clock-latency-ns = <150000>; 171 opp-suspend; 172 }; 173 174 opp-1300000000 { 175 opp-hz = /bits/ 64 <1300000000>; 176 opp-microvolt = <1000000>; 177 opp-supported-hw = <0xc>, <0x4>; 178 clock-latency-ns = <150000>; 179 opp-suspend; 180 }; 181 182 opp-1500000000 { 183 opp-hz = /bits/ 64 <1500000000>; 184 opp-microvolt = <1000000>; 185 opp-supported-hw = <0x8>, <0x3>; 186 clock-latency-ns = <150000>; 187 opp-suspend; 188 }; 189 }; 190 191 pmu { 192 compatible = "arm,cortex-a53-pmu"; 193 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-parent = <&gic>; 195 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 196 }; 197 198 psci { 199 compatible = "arm,psci-1.0"; 200 method = "smc"; 201 }; 202 203 thermal-zones { 204 cpu_thermal: cpu-thermal { 205 polling-delay-passive = <250>; 206 polling-delay = <2000>; 207 thermal-sensors = <&tmu 0>; 208 209 trips { 210 cpu_alert: cpu-alert { 211 temperature = <80000>; 212 hysteresis = <2000>; 213 type = "passive"; 214 }; 215 216 cpu-crit { 217 temperature = <90000>; 218 hysteresis = <2000>; 219 type = "critical"; 220 }; 221 }; 222 223 cooling-maps { 224 map0 { 225 trip = <&cpu_alert>; 226 cooling-device = 227 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 228 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 229 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 230 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 231 }; 232 }; 233 }; 234 235 gpu-thermal { 236 polling-delay-passive = <250>; 237 polling-delay = <2000>; 238 thermal-sensors = <&tmu 1>; 239 240 trips { 241 gpu_alert: gpu-alert { 242 temperature = <80000>; 243 hysteresis = <2000>; 244 type = "passive"; 245 }; 246 247 gpu-crit { 248 temperature = <90000>; 249 hysteresis = <2000>; 250 type = "critical"; 251 }; 252 }; 253 254 cooling-maps { 255 map0 { 256 trip = <&gpu_alert>; 257 cooling-device = 258 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 259 }; 260 }; 261 }; 262 263 vpu-thermal { 264 polling-delay-passive = <250>; 265 polling-delay = <2000>; 266 thermal-sensors = <&tmu 2>; 267 268 trips { 269 vpu-crit { 270 temperature = <90000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 }; 276 }; 277 278 timer { 279 compatible = "arm,armv8-timer"; 280 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 281 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 282 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 283 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 284 interrupt-parent = <&gic>; 285 arm,no-tick-in-suspend; 286 }; 287 288 soc@0 { 289 compatible = "simple-bus"; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges = <0x0 0x0 0x0 0x3e000000>; 293 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 294 295 bus@30000000 { /* AIPS1 */ 296 compatible = "fsl,aips-bus", "simple-bus"; 297 reg = <0x30000000 0x400000>; 298 #address-cells = <1>; 299 #size-cells = <1>; 300 ranges = <0x30000000 0x30000000 0x400000>; 301 302 sai1: sai@30010000 { 303 #sound-dai-cells = <0>; 304 compatible = "fsl,imx8mq-sai"; 305 reg = <0x30010000 0x10000>; 306 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 308 <&clk IMX8MQ_CLK_SAI1_ROOT>, 309 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 310 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 311 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 312 dma-names = "rx", "tx"; 313 status = "disabled"; 314 }; 315 316 sai6: sai@30030000 { 317 #sound-dai-cells = <0>; 318 compatible = "fsl,imx8mq-sai"; 319 reg = <0x30030000 0x10000>; 320 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 322 <&clk IMX8MQ_CLK_SAI6_ROOT>, 323 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 324 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 325 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 sai5: sai@30040000 { 331 #sound-dai-cells = <0>; 332 compatible = "fsl,imx8mq-sai"; 333 reg = <0x30040000 0x10000>; 334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 336 <&clk IMX8MQ_CLK_SAI5_ROOT>, 337 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 338 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 339 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 340 dma-names = "rx", "tx"; 341 status = "disabled"; 342 }; 343 344 sai4: sai@30050000 { 345 #sound-dai-cells = <0>; 346 compatible = "fsl,imx8mq-sai"; 347 reg = <0x30050000 0x10000>; 348 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 350 <&clk IMX8MQ_CLK_SAI4_ROOT>, 351 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 352 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 353 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 354 dma-names = "rx", "tx"; 355 status = "disabled"; 356 }; 357 358 gpio1: gpio@30200000 { 359 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 360 reg = <0x30200000 0x10000>; 361 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 gpio-ranges = <&iomuxc 0 10 30>; 369 }; 370 371 gpio2: gpio@30210000 { 372 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 373 reg = <0x30210000 0x10000>; 374 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 377 gpio-controller; 378 #gpio-cells = <2>; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 gpio-ranges = <&iomuxc 0 40 21>; 382 }; 383 384 gpio3: gpio@30220000 { 385 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 386 reg = <0x30220000 0x10000>; 387 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 gpio-ranges = <&iomuxc 0 61 26>; 395 }; 396 397 gpio4: gpio@30230000 { 398 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 399 reg = <0x30230000 0x10000>; 400 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 gpio-ranges = <&iomuxc 0 87 32>; 408 }; 409 410 gpio5: gpio@30240000 { 411 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 412 reg = <0x30240000 0x10000>; 413 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 gpio-ranges = <&iomuxc 0 119 30>; 421 }; 422 423 tmu: tmu@30260000 { 424 compatible = "fsl,imx8mq-tmu"; 425 reg = <0x30260000 0x10000>; 426 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 428 little-endian; 429 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 430 fsl,tmu-calibration = <0x00000000 0x00000023 431 0x00000001 0x00000029 432 0x00000002 0x0000002f 433 0x00000003 0x00000035 434 0x00000004 0x0000003d 435 0x00000005 0x00000043 436 0x00000006 0x0000004b 437 0x00000007 0x00000051 438 0x00000008 0x00000057 439 0x00000009 0x0000005f 440 0x0000000a 0x00000067 441 0x0000000b 0x0000006f 442 443 0x00010000 0x0000001b 444 0x00010001 0x00000023 445 0x00010002 0x0000002b 446 0x00010003 0x00000033 447 0x00010004 0x0000003b 448 0x00010005 0x00000043 449 0x00010006 0x0000004b 450 0x00010007 0x00000055 451 0x00010008 0x0000005d 452 0x00010009 0x00000067 453 0x0001000a 0x00000070 454 455 0x00020000 0x00000017 456 0x00020001 0x00000023 457 0x00020002 0x0000002d 458 0x00020003 0x00000037 459 0x00020004 0x00000041 460 0x00020005 0x0000004b 461 0x00020006 0x00000057 462 0x00020007 0x00000063 463 0x00020008 0x0000006f 464 465 0x00030000 0x00000015 466 0x00030001 0x00000021 467 0x00030002 0x0000002d 468 0x00030003 0x00000039 469 0x00030004 0x00000045 470 0x00030005 0x00000053 471 0x00030006 0x0000005f 472 0x00030007 0x00000071>; 473 #thermal-sensor-cells = <1>; 474 }; 475 476 wdog1: watchdog@30280000 { 477 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 478 reg = <0x30280000 0x10000>; 479 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 481 status = "disabled"; 482 }; 483 484 wdog2: watchdog@30290000 { 485 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 486 reg = <0x30290000 0x10000>; 487 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 489 status = "disabled"; 490 }; 491 492 wdog3: watchdog@302a0000 { 493 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 494 reg = <0x302a0000 0x10000>; 495 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 497 status = "disabled"; 498 }; 499 500 sdma2: sdma@302c0000 { 501 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 502 reg = <0x302c0000 0x10000>; 503 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 505 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 506 clock-names = "ipg", "ahb"; 507 #dma-cells = <3>; 508 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 509 }; 510 511 lcdif: lcd-controller@30320000 { 512 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 513 reg = <0x30320000 0x10000>; 514 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 516 clock-names = "pix"; 517 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 518 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 519 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 520 <&clk IMX8MQ_VIDEO_PLL1>; 521 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 522 <&clk IMX8MQ_VIDEO_PLL1>, 523 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 524 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 525 status = "disabled"; 526 527 port@0 { 528 lcdif_mipi_dsi: endpoint { 529 remote-endpoint = <&mipi_dsi_lcdif_in>; 530 }; 531 }; 532 }; 533 534 iomuxc: pinctrl@30330000 { 535 compatible = "fsl,imx8mq-iomuxc"; 536 reg = <0x30330000 0x10000>; 537 }; 538 539 iomuxc_gpr: syscon@30340000 { 540 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 541 "syscon", "simple-mfd"; 542 reg = <0x30340000 0x10000>; 543 544 mux: mux-controller { 545 compatible = "mmio-mux"; 546 #mux-control-cells = <1>; 547 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 548 }; 549 }; 550 551 ocotp: efuse@30350000 { 552 compatible = "fsl,imx8mq-ocotp", "syscon"; 553 reg = <0x30350000 0x10000>; 554 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 558 cpu_speed_grade: speed-grade@10 { 559 reg = <0x10 4>; 560 }; 561 }; 562 563 anatop: syscon@30360000 { 564 compatible = "fsl,imx8mq-anatop", "syscon"; 565 reg = <0x30360000 0x10000>; 566 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 567 }; 568 569 snvs: snvs@30370000 { 570 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 571 reg = <0x30370000 0x10000>; 572 573 snvs_rtc: snvs-rtc-lp{ 574 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 575 regmap =<&snvs>; 576 offset = <0x34>; 577 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 580 clock-names = "snvs-rtc"; 581 }; 582 583 snvs_pwrkey: snvs-powerkey { 584 compatible = "fsl,sec-v4.0-pwrkey"; 585 regmap = <&snvs>; 586 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 588 clock-names = "snvs-pwrkey"; 589 linux,keycode = <KEY_POWER>; 590 wakeup-source; 591 status = "disabled"; 592 }; 593 }; 594 595 clk: clock-controller@30380000 { 596 compatible = "fsl,imx8mq-ccm"; 597 reg = <0x30380000 0x10000>; 598 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 600 #clock-cells = <1>; 601 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 602 <&clk_ext1>, <&clk_ext2>, 603 <&clk_ext3>, <&clk_ext4>; 604 clock-names = "ckil", "osc_25m", "osc_27m", 605 "clk_ext1", "clk_ext2", 606 "clk_ext3", "clk_ext4"; 607 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 608 <&clk IMX8MQ_CLK_A53_CORE>, 609 <&clk IMX8MQ_CLK_NOC>; 610 assigned-clock-rates = <0>, <0>, 611 <800000000>; 612 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 613 <&clk IMX8MQ_ARM_PLL_OUT>; 614 }; 615 616 src: reset-controller@30390000 { 617 compatible = "fsl,imx8mq-src", "syscon"; 618 reg = <0x30390000 0x10000>; 619 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 620 #reset-cells = <1>; 621 }; 622 623 gpc: gpc@303a0000 { 624 compatible = "fsl,imx8mq-gpc"; 625 reg = <0x303a0000 0x10000>; 626 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-parent = <&gic>; 628 interrupt-controller; 629 #interrupt-cells = <3>; 630 631 pgc { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 pgc_mipi: power-domain@0 { 636 #power-domain-cells = <0>; 637 reg = <IMX8M_POWER_DOMAIN_MIPI>; 638 }; 639 640 /* 641 * As per comment in ATF source code: 642 * 643 * PCIE1 and PCIE2 share the 644 * same reset signal, if we 645 * power down PCIE2, PCIE1 646 * will be held in reset too. 647 * 648 * So instead of creating two 649 * separate power domains for 650 * PCIE1 and PCIE2 we create a 651 * link between both and use 652 * it as a shared PCIE power 653 * domain. 654 */ 655 pgc_pcie: power-domain@1 { 656 #power-domain-cells = <0>; 657 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 658 power-domains = <&pgc_pcie2>; 659 }; 660 661 pgc_otg1: power-domain@2 { 662 #power-domain-cells = <0>; 663 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 664 }; 665 666 pgc_otg2: power-domain@3 { 667 #power-domain-cells = <0>; 668 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 669 }; 670 671 pgc_ddr1: power-domain@4 { 672 #power-domain-cells = <0>; 673 reg = <IMX8M_POWER_DOMAIN_DDR1>; 674 }; 675 676 pgc_gpu: power-domain@5 { 677 #power-domain-cells = <0>; 678 reg = <IMX8M_POWER_DOMAIN_GPU>; 679 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 680 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 681 <&clk IMX8MQ_CLK_GPU_AXI>, 682 <&clk IMX8MQ_CLK_GPU_AHB>; 683 }; 684 685 pgc_vpu: power-domain@6 { 686 #power-domain-cells = <0>; 687 reg = <IMX8M_POWER_DOMAIN_VPU>; 688 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; 689 }; 690 691 pgc_disp: power-domain@7 { 692 #power-domain-cells = <0>; 693 reg = <IMX8M_POWER_DOMAIN_DISP>; 694 }; 695 696 pgc_mipi_csi1: power-domain@8 { 697 #power-domain-cells = <0>; 698 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 699 }; 700 701 pgc_mipi_csi2: power-domain@9 { 702 #power-domain-cells = <0>; 703 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 704 }; 705 706 pgc_pcie2: power-domain@a { 707 #power-domain-cells = <0>; 708 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 709 }; 710 }; 711 }; 712 }; 713 714 bus@30400000 { /* AIPS2 */ 715 compatible = "fsl,aips-bus", "simple-bus"; 716 reg = <0x30400000 0x400000>; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges = <0x30400000 0x30400000 0x400000>; 720 721 pwm1: pwm@30660000 { 722 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 723 reg = <0x30660000 0x10000>; 724 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 726 <&clk IMX8MQ_CLK_PWM1_ROOT>; 727 clock-names = "ipg", "per"; 728 #pwm-cells = <2>; 729 status = "disabled"; 730 }; 731 732 pwm2: pwm@30670000 { 733 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 734 reg = <0x30670000 0x10000>; 735 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 737 <&clk IMX8MQ_CLK_PWM2_ROOT>; 738 clock-names = "ipg", "per"; 739 #pwm-cells = <2>; 740 status = "disabled"; 741 }; 742 743 pwm3: pwm@30680000 { 744 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 745 reg = <0x30680000 0x10000>; 746 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 748 <&clk IMX8MQ_CLK_PWM3_ROOT>; 749 clock-names = "ipg", "per"; 750 #pwm-cells = <2>; 751 status = "disabled"; 752 }; 753 754 pwm4: pwm@30690000 { 755 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 756 reg = <0x30690000 0x10000>; 757 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 759 <&clk IMX8MQ_CLK_PWM4_ROOT>; 760 clock-names = "ipg", "per"; 761 #pwm-cells = <2>; 762 status = "disabled"; 763 }; 764 765 system_counter: timer@306a0000 { 766 compatible = "nxp,sysctr-timer"; 767 reg = <0x306a0000 0x20000>; 768 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&osc_25m>; 770 clock-names = "per"; 771 }; 772 }; 773 774 bus@30800000 { /* AIPS3 */ 775 compatible = "fsl,aips-bus", "simple-bus"; 776 reg = <0x30800000 0x400000>; 777 #address-cells = <1>; 778 #size-cells = <1>; 779 ranges = <0x30800000 0x30800000 0x400000>, 780 <0x08000000 0x08000000 0x10000000>; 781 782 ecspi1: spi@30820000 { 783 #address-cells = <1>; 784 #size-cells = <0>; 785 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 786 reg = <0x30820000 0x10000>; 787 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 789 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 790 clock-names = "ipg", "per"; 791 status = "disabled"; 792 }; 793 794 ecspi2: spi@30830000 { 795 #address-cells = <1>; 796 #size-cells = <0>; 797 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 798 reg = <0x30830000 0x10000>; 799 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 801 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 802 clock-names = "ipg", "per"; 803 status = "disabled"; 804 }; 805 806 ecspi3: spi@30840000 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 810 reg = <0x30840000 0x10000>; 811 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 813 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 814 clock-names = "ipg", "per"; 815 status = "disabled"; 816 }; 817 818 uart1: serial@30860000 { 819 compatible = "fsl,imx8mq-uart", 820 "fsl,imx6q-uart"; 821 reg = <0x30860000 0x10000>; 822 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 824 <&clk IMX8MQ_CLK_UART1_ROOT>; 825 clock-names = "ipg", "per"; 826 status = "disabled"; 827 }; 828 829 uart3: serial@30880000 { 830 compatible = "fsl,imx8mq-uart", 831 "fsl,imx6q-uart"; 832 reg = <0x30880000 0x10000>; 833 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 835 <&clk IMX8MQ_CLK_UART3_ROOT>; 836 clock-names = "ipg", "per"; 837 status = "disabled"; 838 }; 839 840 uart2: serial@30890000 { 841 compatible = "fsl,imx8mq-uart", 842 "fsl,imx6q-uart"; 843 reg = <0x30890000 0x10000>; 844 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 846 <&clk IMX8MQ_CLK_UART2_ROOT>; 847 clock-names = "ipg", "per"; 848 status = "disabled"; 849 }; 850 851 sai2: sai@308b0000 { 852 #sound-dai-cells = <0>; 853 compatible = "fsl,imx8mq-sai"; 854 reg = <0x308b0000 0x10000>; 855 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 857 <&clk IMX8MQ_CLK_SAI2_ROOT>, 858 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 859 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 860 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 861 dma-names = "rx", "tx"; 862 status = "disabled"; 863 }; 864 865 sai3: sai@308c0000 { 866 #sound-dai-cells = <0>; 867 compatible = "fsl,imx8mq-sai"; 868 reg = <0x308c0000 0x10000>; 869 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 871 <&clk IMX8MQ_CLK_SAI3_ROOT>, 872 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 873 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 874 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 875 dma-names = "rx", "tx"; 876 status = "disabled"; 877 }; 878 879 crypto: crypto@30900000 { 880 compatible = "fsl,sec-v4.0"; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 reg = <0x30900000 0x40000>; 884 ranges = <0 0x30900000 0x40000>; 885 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clk IMX8MQ_CLK_AHB>, 887 <&clk IMX8MQ_CLK_IPG_ROOT>; 888 clock-names = "aclk", "ipg"; 889 890 sec_jr0: jr@1000 { 891 compatible = "fsl,sec-v4.0-job-ring"; 892 reg = <0x1000 0x1000>; 893 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 894 }; 895 896 sec_jr1: jr@2000 { 897 compatible = "fsl,sec-v4.0-job-ring"; 898 reg = <0x2000 0x1000>; 899 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 900 }; 901 902 sec_jr2: jr@3000 { 903 compatible = "fsl,sec-v4.0-job-ring"; 904 reg = <0x3000 0x1000>; 905 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 906 }; 907 }; 908 909 mipi_dsi: mipi-dsi@30a00000 { 910 compatible = "fsl,imx8mq-nwl-dsi"; 911 reg = <0x30a00000 0x300>; 912 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 913 <&clk IMX8MQ_CLK_DSI_AHB>, 914 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 915 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 916 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 917 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 918 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 919 <&clk IMX8MQ_CLK_DSI_CORE>, 920 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 921 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 922 <&clk IMX8MQ_SYS1_PLL_266M>; 923 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 924 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 925 mux-controls = <&mux 0>; 926 power-domains = <&pgc_mipi>; 927 phys = <&dphy>; 928 phy-names = "dphy"; 929 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 930 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 931 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 932 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 933 reset-names = "byte", "dpi", "esc", "pclk"; 934 status = "disabled"; 935 936 ports { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 940 port@0 { 941 reg = <0>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 mipi_dsi_lcdif_in: endpoint@0 { 945 reg = <0>; 946 remote-endpoint = <&lcdif_mipi_dsi>; 947 }; 948 }; 949 }; 950 }; 951 952 dphy: dphy@30a00300 { 953 compatible = "fsl,imx8mq-mipi-dphy"; 954 reg = <0x30a00300 0x100>; 955 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 956 clock-names = "phy_ref"; 957 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 958 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; 959 assigned-clock-rates = <24000000>; 960 #phy-cells = <0>; 961 power-domains = <&pgc_mipi>; 962 status = "disabled"; 963 }; 964 965 i2c1: i2c@30a20000 { 966 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 967 reg = <0x30a20000 0x10000>; 968 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "disabled"; 973 }; 974 975 i2c2: i2c@30a30000 { 976 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 977 reg = <0x30a30000 0x10000>; 978 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 status = "disabled"; 983 }; 984 985 i2c3: i2c@30a40000 { 986 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 987 reg = <0x30a40000 0x10000>; 988 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 status = "disabled"; 993 }; 994 995 i2c4: i2c@30a50000 { 996 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 997 reg = <0x30a50000 0x10000>; 998 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 uart4: serial@30a60000 { 1006 compatible = "fsl,imx8mq-uart", 1007 "fsl,imx6q-uart"; 1008 reg = <0x30a60000 0x10000>; 1009 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1011 <&clk IMX8MQ_CLK_UART4_ROOT>; 1012 clock-names = "ipg", "per"; 1013 status = "disabled"; 1014 }; 1015 1016 mu: mailbox@30aa0000 { 1017 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1018 reg = <0x30aa0000 0x10000>; 1019 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1021 #mbox-cells = <2>; 1022 }; 1023 1024 usdhc1: mmc@30b40000 { 1025 compatible = "fsl,imx8mq-usdhc", 1026 "fsl,imx7d-usdhc"; 1027 reg = <0x30b40000 0x10000>; 1028 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1030 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1031 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1032 clock-names = "ipg", "ahb", "per"; 1033 fsl,tuning-start-tap = <20>; 1034 fsl,tuning-step = <2>; 1035 bus-width = <4>; 1036 status = "disabled"; 1037 }; 1038 1039 usdhc2: mmc@30b50000 { 1040 compatible = "fsl,imx8mq-usdhc", 1041 "fsl,imx7d-usdhc"; 1042 reg = <0x30b50000 0x10000>; 1043 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1045 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1046 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1047 clock-names = "ipg", "ahb", "per"; 1048 fsl,tuning-start-tap = <20>; 1049 fsl,tuning-step = <2>; 1050 bus-width = <4>; 1051 status = "disabled"; 1052 }; 1053 1054 qspi0: spi@30bb0000 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1058 reg = <0x30bb0000 0x10000>, 1059 <0x08000000 0x10000000>; 1060 reg-names = "QuadSPI", "QuadSPI-memory"; 1061 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1063 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1064 clock-names = "qspi_en", "qspi"; 1065 status = "disabled"; 1066 }; 1067 1068 sdma1: sdma@30bd0000 { 1069 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1070 reg = <0x30bd0000 0x10000>; 1071 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1073 <&clk IMX8MQ_CLK_AHB>; 1074 clock-names = "ipg", "ahb"; 1075 #dma-cells = <3>; 1076 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1077 }; 1078 1079 fec1: ethernet@30be0000 { 1080 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1081 reg = <0x30be0000 0x10000>; 1082 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1087 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1088 <&clk IMX8MQ_CLK_ENET_TIMER>, 1089 <&clk IMX8MQ_CLK_ENET_REF>, 1090 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1091 clock-names = "ipg", "ahb", "ptp", 1092 "enet_clk_ref", "enet_out"; 1093 fsl,num-tx-queues = <3>; 1094 fsl,num-rx-queues = <3>; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 bus@32c00000 { /* AIPS4 */ 1100 compatible = "fsl,aips-bus", "simple-bus"; 1101 reg = <0x32c00000 0x400000>; 1102 #address-cells = <1>; 1103 #size-cells = <1>; 1104 ranges = <0x32c00000 0x32c00000 0x400000>; 1105 1106 irqsteer: interrupt-controller@32e2d000 { 1107 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1108 reg = <0x32e2d000 0x1000>; 1109 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1111 clock-names = "ipg"; 1112 fsl,channel = <0>; 1113 fsl,num-irqs = <64>; 1114 interrupt-controller; 1115 #interrupt-cells = <1>; 1116 }; 1117 }; 1118 1119 gpu: gpu@38000000 { 1120 compatible = "vivante,gc"; 1121 reg = <0x38000000 0x40000>; 1122 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1124 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1125 <&clk IMX8MQ_CLK_GPU_AXI>, 1126 <&clk IMX8MQ_CLK_GPU_AHB>; 1127 clock-names = "core", "shader", "bus", "reg"; 1128 #cooling-cells = <2>; 1129 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1130 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1131 <&clk IMX8MQ_CLK_GPU_AXI>, 1132 <&clk IMX8MQ_CLK_GPU_AHB>, 1133 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1134 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1135 <&clk IMX8MQ_GPU_PLL_OUT>, 1136 <&clk IMX8MQ_GPU_PLL_OUT>, 1137 <&clk IMX8MQ_GPU_PLL_OUT>, 1138 <&clk IMX8MQ_GPU_PLL>; 1139 assigned-clock-rates = <800000000>, <800000000>, 1140 <800000000>, <800000000>, <0>; 1141 power-domains = <&pgc_gpu>; 1142 }; 1143 1144 usb_dwc3_0: usb@38100000 { 1145 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1146 reg = <0x38100000 0x10000>; 1147 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1148 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1149 <&clk IMX8MQ_CLK_32K>; 1150 clock-names = "bus_early", "ref", "suspend"; 1151 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1152 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1153 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1154 <&clk IMX8MQ_SYS1_PLL_100M>; 1155 assigned-clock-rates = <500000000>, <100000000>; 1156 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1157 phys = <&usb3_phy0>, <&usb3_phy0>; 1158 phy-names = "usb2-phy", "usb3-phy"; 1159 power-domains = <&pgc_otg1>; 1160 usb3-resume-missing-cas; 1161 status = "disabled"; 1162 }; 1163 1164 usb3_phy0: usb-phy@381f0040 { 1165 compatible = "fsl,imx8mq-usb-phy"; 1166 reg = <0x381f0040 0x40>; 1167 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1168 clock-names = "phy"; 1169 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1170 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1171 assigned-clock-rates = <100000000>; 1172 #phy-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 usb_dwc3_1: usb@38200000 { 1177 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1178 reg = <0x38200000 0x10000>; 1179 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1180 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1181 <&clk IMX8MQ_CLK_32K>; 1182 clock-names = "bus_early", "ref", "suspend"; 1183 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1184 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1185 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1186 <&clk IMX8MQ_SYS1_PLL_100M>; 1187 assigned-clock-rates = <500000000>, <100000000>; 1188 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1189 phys = <&usb3_phy1>, <&usb3_phy1>; 1190 phy-names = "usb2-phy", "usb3-phy"; 1191 power-domains = <&pgc_otg2>; 1192 usb3-resume-missing-cas; 1193 status = "disabled"; 1194 }; 1195 1196 usb3_phy1: usb-phy@382f0040 { 1197 compatible = "fsl,imx8mq-usb-phy"; 1198 reg = <0x382f0040 0x40>; 1199 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1200 clock-names = "phy"; 1201 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1202 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1203 assigned-clock-rates = <100000000>; 1204 #phy-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 vpu: video-codec@38300000 { 1209 compatible = "nxp,imx8mq-vpu"; 1210 reg = <0x38300000 0x10000>, 1211 <0x38310000 0x10000>, 1212 <0x38320000 0x10000>; 1213 reg-names = "g1", "g2", "ctrl"; 1214 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1216 interrupt-names = "g1", "g2"; 1217 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1218 <&clk IMX8MQ_CLK_VPU_G2_ROOT>, 1219 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; 1220 clock-names = "g1", "g2", "bus"; 1221 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 1222 <&clk IMX8MQ_CLK_VPU_G2>, 1223 <&clk IMX8MQ_CLK_VPU_BUS>, 1224 <&clk IMX8MQ_VPU_PLL_BYPASS>; 1225 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 1226 <&clk IMX8MQ_VPU_PLL_OUT>, 1227 <&clk IMX8MQ_SYS1_PLL_800M>, 1228 <&clk IMX8MQ_VPU_PLL>; 1229 assigned-clock-rates = <600000000>, <600000000>, 1230 <800000000>, <0>; 1231 power-domains = <&pgc_vpu>; 1232 }; 1233 1234 pcie0: pcie@33800000 { 1235 compatible = "fsl,imx8mq-pcie"; 1236 reg = <0x33800000 0x400000>, 1237 <0x1ff00000 0x80000>; 1238 reg-names = "dbi", "config"; 1239 #address-cells = <3>; 1240 #size-cells = <2>; 1241 device_type = "pci"; 1242 bus-range = <0x00 0xff>; 1243 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1244 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1245 num-lanes = <1>; 1246 num-viewport = <4>; 1247 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1248 interrupt-names = "msi"; 1249 #interrupt-cells = <1>; 1250 interrupt-map-mask = <0 0 0 0x7>; 1251 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1252 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1253 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1254 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1255 fsl,max-link-speed = <2>; 1256 power-domains = <&pgc_pcie>; 1257 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1258 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1259 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1260 reset-names = "pciephy", "apps", "turnoff"; 1261 status = "disabled"; 1262 }; 1263 1264 pcie1: pcie@33c00000 { 1265 compatible = "fsl,imx8mq-pcie"; 1266 reg = <0x33c00000 0x400000>, 1267 <0x27f00000 0x80000>; 1268 reg-names = "dbi", "config"; 1269 #address-cells = <3>; 1270 #size-cells = <2>; 1271 device_type = "pci"; 1272 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ 1273 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1274 num-lanes = <1>; 1275 num-viewport = <4>; 1276 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1277 interrupt-names = "msi"; 1278 #interrupt-cells = <1>; 1279 interrupt-map-mask = <0 0 0 0x7>; 1280 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1281 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1282 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1283 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1284 fsl,max-link-speed = <2>; 1285 power-domains = <&pgc_pcie>; 1286 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1287 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1288 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1289 reset-names = "pciephy", "apps", "turnoff"; 1290 status = "disabled"; 1291 }; 1292 1293 gic: interrupt-controller@38800000 { 1294 compatible = "arm,gic-v3"; 1295 reg = <0x38800000 0x10000>, /* GIC Dist */ 1296 <0x38880000 0xc0000>, /* GICR */ 1297 <0x31000000 0x2000>, /* GICC */ 1298 <0x31010000 0x2000>, /* GICV */ 1299 <0x31020000 0x2000>; /* GICH */ 1300 #interrupt-cells = <3>; 1301 interrupt-controller; 1302 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1303 interrupt-parent = <&gic>; 1304 }; 1305 1306 ddrc: memory-controller@3d400000 { 1307 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1308 reg = <0x3d400000 0x400000>; 1309 clock-names = "core", "pll", "alt", "apb"; 1310 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1311 <&clk IMX8MQ_DRAM_PLL_OUT>, 1312 <&clk IMX8MQ_CLK_DRAM_ALT>, 1313 <&clk IMX8MQ_CLK_DRAM_APB>; 1314 }; 1315 1316 ddr-pmu@3d800000 { 1317 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1318 reg = <0x3d800000 0x400000>; 1319 interrupt-parent = <&gic>; 1320 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1321 }; 1322 }; 1323}; 1324