1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 funnel { 206 /* 207 * non-configurable funnel don't show up on the AMBA 208 * bus. As such no need to add "arm,primecell". 209 */ 210 compatible = "arm,coresight-static-funnel"; 211 212 in-ports { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 port@0 { 217 reg = <0>; 218 219 ca_funnel_in_port0: endpoint { 220 remote-endpoint = <&etm0_out_port>; 221 }; 222 }; 223 224 port@1 { 225 reg = <1>; 226 227 ca_funnel_in_port1: endpoint { 228 remote-endpoint = <&etm1_out_port>; 229 }; 230 }; 231 232 port@2 { 233 reg = <2>; 234 235 ca_funnel_in_port2: endpoint { 236 remote-endpoint = <&etm2_out_port>; 237 }; 238 }; 239 240 port@3 { 241 reg = <3>; 242 243 ca_funnel_in_port3: endpoint { 244 remote-endpoint = <&etm3_out_port>; 245 }; 246 }; 247 }; 248 249 out-ports { 250 port { 251 252 ca_funnel_out_port0: endpoint { 253 remote-endpoint = <&hugo_funnel_in_port0>; 254 }; 255 }; 256 }; 257 }; 258 259 reserved-memory { 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 264 dsp_reserved: dsp@92400000 { 265 reg = <0 0x92400000 0 0x2000000>; 266 no-map; 267 status = "disabled"; 268 }; 269 }; 270 271 pmu { 272 compatible = "arm,cortex-a53-pmu"; 273 interrupts = <GIC_PPI 7 274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 275 }; 276 277 psci { 278 compatible = "arm,psci-1.0"; 279 method = "smc"; 280 }; 281 282 thermal-zones { 283 cpu-thermal { 284 polling-delay-passive = <250>; 285 polling-delay = <2000>; 286 thermal-sensors = <&tmu 0>; 287 trips { 288 cpu_alert0: trip0 { 289 temperature = <85000>; 290 hysteresis = <2000>; 291 type = "passive"; 292 }; 293 294 cpu_crit0: trip1 { 295 temperature = <95000>; 296 hysteresis = <2000>; 297 type = "critical"; 298 }; 299 }; 300 301 cooling-maps { 302 map0 { 303 trip = <&cpu_alert0>; 304 cooling-device = 305 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 306 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 307 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 308 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 309 }; 310 }; 311 }; 312 313 soc-thermal { 314 polling-delay-passive = <250>; 315 polling-delay = <2000>; 316 thermal-sensors = <&tmu 1>; 317 trips { 318 soc_alert0: trip0 { 319 temperature = <85000>; 320 hysteresis = <2000>; 321 type = "passive"; 322 }; 323 324 soc_crit0: trip1 { 325 temperature = <95000>; 326 hysteresis = <2000>; 327 type = "critical"; 328 }; 329 }; 330 331 cooling-maps { 332 map0 { 333 trip = <&soc_alert0>; 334 cooling-device = 335 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 336 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 337 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 338 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 339 }; 340 }; 341 }; 342 }; 343 344 timer { 345 compatible = "arm,armv8-timer"; 346 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 347 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 348 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 349 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 350 clock-frequency = <8000000>; 351 arm,no-tick-in-suspend; 352 }; 353 354 soc: soc@0 { 355 compatible = "fsl,imx8mp-soc", "simple-bus"; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0x0 0x0 0x0 0x3e000000>; 359 nvmem-cells = <&imx8mp_uid>; 360 nvmem-cell-names = "soc_unique_id"; 361 362 etm0: etm@28440000 { 363 compatible = "arm,coresight-etm4x", "arm,primecell"; 364 reg = <0x28440000 0x1000>; 365 cpu = <&A53_0>; 366 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 367 clock-names = "apb_pclk"; 368 369 out-ports { 370 port { 371 etm0_out_port: endpoint { 372 remote-endpoint = <&ca_funnel_in_port0>; 373 }; 374 }; 375 }; 376 }; 377 378 etm1: etm@28540000 { 379 compatible = "arm,coresight-etm4x", "arm,primecell"; 380 reg = <0x28540000 0x1000>; 381 cpu = <&A53_1>; 382 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 383 clock-names = "apb_pclk"; 384 385 out-ports { 386 port { 387 etm1_out_port: endpoint { 388 remote-endpoint = <&ca_funnel_in_port1>; 389 }; 390 }; 391 }; 392 }; 393 394 etm2: etm@28640000 { 395 compatible = "arm,coresight-etm4x", "arm,primecell"; 396 reg = <0x28640000 0x1000>; 397 cpu = <&A53_2>; 398 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 399 clock-names = "apb_pclk"; 400 401 out-ports { 402 port { 403 etm2_out_port: endpoint { 404 remote-endpoint = <&ca_funnel_in_port2>; 405 }; 406 }; 407 }; 408 }; 409 410 etm3: etm@28740000 { 411 compatible = "arm,coresight-etm4x", "arm,primecell"; 412 reg = <0x28740000 0x1000>; 413 cpu = <&A53_3>; 414 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 415 clock-names = "apb_pclk"; 416 417 out-ports { 418 port { 419 etm3_out_port: endpoint { 420 remote-endpoint = <&ca_funnel_in_port3>; 421 }; 422 }; 423 }; 424 }; 425 426 funnel@28c03000 { 427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 428 reg = <0x28c03000 0x1000>; 429 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 430 clock-names = "apb_pclk"; 431 432 in-ports { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 port@0 { 437 reg = <0>; 438 439 hugo_funnel_in_port0: endpoint { 440 remote-endpoint = <&ca_funnel_out_port0>; 441 }; 442 }; 443 444 port@1 { 445 reg = <1>; 446 447 hugo_funnel_in_port1: endpoint { 448 /* M7 input */ 449 }; 450 }; 451 452 port@2 { 453 reg = <2>; 454 455 hugo_funnel_in_port2: endpoint { 456 /* DSP input */ 457 }; 458 }; 459 /* the other input ports are not connect to anything */ 460 }; 461 462 out-ports { 463 port { 464 hugo_funnel_out_port0: endpoint { 465 remote-endpoint = <&etf_in_port>; 466 }; 467 }; 468 }; 469 }; 470 471 etf@28c04000 { 472 compatible = "arm,coresight-tmc", "arm,primecell"; 473 reg = <0x28c04000 0x1000>; 474 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 475 clock-names = "apb_pclk"; 476 477 in-ports { 478 port { 479 etf_in_port: endpoint { 480 remote-endpoint = <&hugo_funnel_out_port0>; 481 }; 482 }; 483 }; 484 485 out-ports { 486 port { 487 etf_out_port: endpoint { 488 remote-endpoint = <&etr_in_port>; 489 }; 490 }; 491 }; 492 }; 493 494 etr@28c06000 { 495 compatible = "arm,coresight-tmc", "arm,primecell"; 496 reg = <0x28c06000 0x1000>; 497 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 498 clock-names = "apb_pclk"; 499 500 in-ports { 501 port { 502 etr_in_port: endpoint { 503 remote-endpoint = <&etf_out_port>; 504 }; 505 }; 506 }; 507 }; 508 509 aips1: bus@30000000 { 510 compatible = "fsl,aips-bus", "simple-bus"; 511 reg = <0x30000000 0x400000>; 512 #address-cells = <1>; 513 #size-cells = <1>; 514 ranges; 515 516 gpio1: gpio@30200000 { 517 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 518 reg = <0x30200000 0x10000>; 519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 gpio-ranges = <&iomuxc 0 5 30>; 527 }; 528 529 gpio2: gpio@30210000 { 530 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 531 reg = <0x30210000 0x10000>; 532 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 gpio-ranges = <&iomuxc 0 35 21>; 540 }; 541 542 gpio3: gpio@30220000 { 543 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 544 reg = <0x30220000 0x10000>; 545 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 553 }; 554 555 gpio4: gpio@30230000 { 556 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 557 reg = <0x30230000 0x10000>; 558 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 gpio-ranges = <&iomuxc 0 82 32>; 566 }; 567 568 gpio5: gpio@30240000 { 569 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 570 reg = <0x30240000 0x10000>; 571 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 gpio-ranges = <&iomuxc 0 114 30>; 579 }; 580 581 tmu: tmu@30260000 { 582 compatible = "fsl,imx8mp-tmu"; 583 reg = <0x30260000 0x10000>; 584 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 585 nvmem-cells = <&tmu_calib>; 586 nvmem-cell-names = "calib"; 587 #thermal-sensor-cells = <1>; 588 }; 589 590 wdog1: watchdog@30280000 { 591 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 592 reg = <0x30280000 0x10000>; 593 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 595 status = "disabled"; 596 }; 597 598 wdog2: watchdog@30290000 { 599 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 600 reg = <0x30290000 0x10000>; 601 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 603 status = "disabled"; 604 }; 605 606 wdog3: watchdog@302a0000 { 607 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 608 reg = <0x302a0000 0x10000>; 609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 611 status = "disabled"; 612 }; 613 614 gpt1: timer@302d0000 { 615 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 616 reg = <0x302d0000 0x10000>; 617 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 619 clock-names = "ipg", "per"; 620 }; 621 622 gpt2: timer@302e0000 { 623 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 624 reg = <0x302e0000 0x10000>; 625 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 627 clock-names = "ipg", "per"; 628 }; 629 630 gpt3: timer@302f0000 { 631 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 632 reg = <0x302f0000 0x10000>; 633 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 635 clock-names = "ipg", "per"; 636 }; 637 638 iomuxc: pinctrl@30330000 { 639 compatible = "fsl,imx8mp-iomuxc"; 640 reg = <0x30330000 0x10000>; 641 }; 642 643 gpr: syscon@30340000 { 644 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 645 reg = <0x30340000 0x10000>; 646 }; 647 648 ocotp: efuse@30350000 { 649 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 650 reg = <0x30350000 0x10000>; 651 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 652 /* For nvmem subnodes */ 653 #address-cells = <1>; 654 #size-cells = <1>; 655 656 /* 657 * The register address below maps to the MX8M 658 * Fusemap Description Table entries this way. 659 * Assuming 660 * reg = <ADDR SIZE>; 661 * then 662 * Fuse Address = (ADDR * 4) + 0x400 663 * Note that if SIZE is greater than 4, then 664 * each subsequent fuse is located at offset 665 * +0x10 in Fusemap Description Table (e.g. 666 * reg = <0x8 0x8> describes fuses 0x420 and 667 * 0x430). 668 */ 669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 670 reg = <0x8 0x8>; 671 }; 672 673 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 674 reg = <0x10 4>; 675 }; 676 677 eth_mac1: mac-address@90 { /* 0x640 */ 678 reg = <0x90 6>; 679 }; 680 681 eth_mac2: mac-address@96 { /* 0x658 */ 682 reg = <0x96 6>; 683 }; 684 685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 686 reg = <0x264 0x10>; 687 }; 688 }; 689 690 anatop: clock-controller@30360000 { 691 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 692 reg = <0x30360000 0x10000>; 693 #clock-cells = <1>; 694 }; 695 696 snvs: snvs@30370000 { 697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 698 reg = <0x30370000 0x10000>; 699 700 snvs_rtc: snvs-rtc-lp { 701 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 702 regmap = <&snvs>; 703 offset = <0x34>; 704 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 707 clock-names = "snvs-rtc"; 708 }; 709 710 snvs_pwrkey: snvs-powerkey { 711 compatible = "fsl,sec-v4.0-pwrkey"; 712 regmap = <&snvs>; 713 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 715 clock-names = "snvs-pwrkey"; 716 linux,keycode = <KEY_POWER>; 717 wakeup-source; 718 status = "disabled"; 719 }; 720 721 snvs_lpgpr: snvs-lpgpr { 722 compatible = "fsl,imx8mp-snvs-lpgpr", 723 "fsl,imx7d-snvs-lpgpr"; 724 }; 725 }; 726 727 clk: clock-controller@30380000 { 728 compatible = "fsl,imx8mp-ccm"; 729 reg = <0x30380000 0x10000>; 730 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 732 #clock-cells = <1>; 733 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 734 <&clk_ext3>, <&clk_ext4>; 735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 736 "clk_ext3", "clk_ext4"; 737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 738 <&clk IMX8MP_CLK_A53_CORE>, 739 <&clk IMX8MP_CLK_NOC>, 740 <&clk IMX8MP_CLK_NOC_IO>, 741 <&clk IMX8MP_CLK_GIC>; 742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 743 <&clk IMX8MP_ARM_PLL_OUT>, 744 <&clk IMX8MP_SYS_PLL2_1000M>, 745 <&clk IMX8MP_SYS_PLL1_800M>, 746 <&clk IMX8MP_SYS_PLL2_500M>; 747 assigned-clock-rates = <0>, <0>, 748 <1000000000>, 749 <800000000>, 750 <500000000>; 751 }; 752 753 src: reset-controller@30390000 { 754 compatible = "fsl,imx8mp-src", "syscon"; 755 reg = <0x30390000 0x10000>; 756 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 757 #reset-cells = <1>; 758 }; 759 760 gpc: gpc@303a0000 { 761 compatible = "fsl,imx8mp-gpc"; 762 reg = <0x303a0000 0x1000>; 763 interrupt-parent = <&gic>; 764 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-controller; 766 #interrupt-cells = <3>; 767 768 pgc { 769 #address-cells = <1>; 770 #size-cells = <0>; 771 772 pgc_mipi_phy1: power-domain@0 { 773 #power-domain-cells = <0>; 774 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 775 }; 776 777 pgc_pcie_phy: power-domain@1 { 778 #power-domain-cells = <0>; 779 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 780 }; 781 782 pgc_usb1_phy: power-domain@2 { 783 #power-domain-cells = <0>; 784 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 785 }; 786 787 pgc_usb2_phy: power-domain@3 { 788 #power-domain-cells = <0>; 789 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 790 }; 791 792 pgc_audio: power-domain@5 { 793 #power-domain-cells = <0>; 794 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 795 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 796 <&clk IMX8MP_CLK_AUDIO_AXI>; 797 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 798 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 799 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 800 <&clk IMX8MP_SYS_PLL1_800M>; 801 assigned-clock-rates = <400000000>, 802 <600000000>; 803 }; 804 805 pgc_gpu2d: power-domain@6 { 806 #power-domain-cells = <0>; 807 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 808 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 809 power-domains = <&pgc_gpumix>; 810 }; 811 812 pgc_gpumix: power-domain@7 { 813 #power-domain-cells = <0>; 814 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 815 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 816 <&clk IMX8MP_CLK_GPU_AHB>; 817 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 818 <&clk IMX8MP_CLK_GPU_AHB>; 819 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 820 <&clk IMX8MP_SYS_PLL1_800M>; 821 assigned-clock-rates = <800000000>, <400000000>; 822 }; 823 824 pgc_gpu3d: power-domain@9 { 825 #power-domain-cells = <0>; 826 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 827 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 828 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 829 power-domains = <&pgc_gpumix>; 830 }; 831 832 pgc_mediamix: power-domain@10 { 833 #power-domain-cells = <0>; 834 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 835 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 836 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 837 }; 838 839 pgc_mipi_phy2: power-domain@16 { 840 #power-domain-cells = <0>; 841 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 842 }; 843 844 pgc_hsiomix: power-domain@17 { 845 #power-domain-cells = <0>; 846 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 847 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 848 <&clk IMX8MP_CLK_HSIO_ROOT>; 849 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 850 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 851 assigned-clock-rates = <500000000>; 852 }; 853 854 pgc_ispdwp: power-domain@18 { 855 #power-domain-cells = <0>; 856 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 857 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 858 }; 859 860 pgc_vpumix: power-domain@19 { 861 #power-domain-cells = <0>; 862 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 863 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 864 }; 865 866 pgc_vpu_g1: power-domain@20 { 867 #power-domain-cells = <0>; 868 power-domains = <&pgc_vpumix>; 869 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 870 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 871 }; 872 873 pgc_vpu_g2: power-domain@21 { 874 #power-domain-cells = <0>; 875 power-domains = <&pgc_vpumix>; 876 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 877 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 878 }; 879 880 pgc_vpu_vc8000e: power-domain@22 { 881 #power-domain-cells = <0>; 882 power-domains = <&pgc_vpumix>; 883 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 884 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 885 }; 886 887 pgc_mlmix: power-domain@24 { 888 #power-domain-cells = <0>; 889 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 890 clocks = <&clk IMX8MP_CLK_ML_AXI>, 891 <&clk IMX8MP_CLK_ML_AHB>, 892 <&clk IMX8MP_CLK_NPU_ROOT>; 893 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 894 <&clk IMX8MP_CLK_ML_AXI>, 895 <&clk IMX8MP_CLK_ML_AHB>; 896 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 897 <&clk IMX8MP_SYS_PLL1_800M>, 898 <&clk IMX8MP_SYS_PLL1_800M>; 899 assigned-clock-rates = <800000000>, 900 <800000000>, 901 <300000000>; 902 }; 903 }; 904 }; 905 }; 906 907 aips2: bus@30400000 { 908 compatible = "fsl,aips-bus", "simple-bus"; 909 reg = <0x30400000 0x400000>; 910 #address-cells = <1>; 911 #size-cells = <1>; 912 ranges; 913 914 pwm1: pwm@30660000 { 915 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 916 reg = <0x30660000 0x10000>; 917 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 919 <&clk IMX8MP_CLK_PWM1_ROOT>; 920 clock-names = "ipg", "per"; 921 #pwm-cells = <3>; 922 status = "disabled"; 923 }; 924 925 pwm2: pwm@30670000 { 926 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 927 reg = <0x30670000 0x10000>; 928 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 930 <&clk IMX8MP_CLK_PWM2_ROOT>; 931 clock-names = "ipg", "per"; 932 #pwm-cells = <3>; 933 status = "disabled"; 934 }; 935 936 pwm3: pwm@30680000 { 937 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 938 reg = <0x30680000 0x10000>; 939 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 941 <&clk IMX8MP_CLK_PWM3_ROOT>; 942 clock-names = "ipg", "per"; 943 #pwm-cells = <3>; 944 status = "disabled"; 945 }; 946 947 pwm4: pwm@30690000 { 948 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 949 reg = <0x30690000 0x10000>; 950 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 952 <&clk IMX8MP_CLK_PWM4_ROOT>; 953 clock-names = "ipg", "per"; 954 #pwm-cells = <3>; 955 status = "disabled"; 956 }; 957 958 system_counter: timer@306a0000 { 959 compatible = "nxp,sysctr-timer"; 960 reg = <0x306a0000 0x20000>; 961 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&osc_24m>; 963 clock-names = "per"; 964 }; 965 966 gpt6: timer@306e0000 { 967 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 968 reg = <0x306e0000 0x10000>; 969 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 971 clock-names = "ipg", "per"; 972 }; 973 974 gpt5: timer@306f0000 { 975 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 976 reg = <0x306f0000 0x10000>; 977 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 979 clock-names = "ipg", "per"; 980 }; 981 982 gpt4: timer@30700000 { 983 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 984 reg = <0x30700000 0x10000>; 985 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 987 clock-names = "ipg", "per"; 988 }; 989 }; 990 991 aips3: bus@30800000 { 992 compatible = "fsl,aips-bus", "simple-bus"; 993 reg = <0x30800000 0x400000>; 994 #address-cells = <1>; 995 #size-cells = <1>; 996 ranges; 997 998 spba-bus@30800000 { 999 compatible = "fsl,spba-bus", "simple-bus"; 1000 reg = <0x30800000 0x100000>; 1001 #address-cells = <1>; 1002 #size-cells = <1>; 1003 ranges; 1004 1005 ecspi1: spi@30820000 { 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1009 reg = <0x30820000 0x10000>; 1010 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1012 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1013 clock-names = "ipg", "per"; 1014 assigned-clock-rates = <80000000>; 1015 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1016 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1017 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1018 dma-names = "rx", "tx"; 1019 status = "disabled"; 1020 }; 1021 1022 ecspi2: spi@30830000 { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1026 reg = <0x30830000 0x10000>; 1027 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1029 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1030 clock-names = "ipg", "per"; 1031 assigned-clock-rates = <80000000>; 1032 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1033 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1034 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1035 dma-names = "rx", "tx"; 1036 status = "disabled"; 1037 }; 1038 1039 ecspi3: spi@30840000 { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1043 reg = <0x30840000 0x10000>; 1044 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1046 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1047 clock-names = "ipg", "per"; 1048 assigned-clock-rates = <80000000>; 1049 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1050 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1051 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1052 dma-names = "rx", "tx"; 1053 status = "disabled"; 1054 }; 1055 1056 uart1: serial@30860000 { 1057 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1058 reg = <0x30860000 0x10000>; 1059 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1061 <&clk IMX8MP_CLK_UART1_ROOT>; 1062 clock-names = "ipg", "per"; 1063 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1064 dma-names = "rx", "tx"; 1065 status = "disabled"; 1066 }; 1067 1068 uart3: serial@30880000 { 1069 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1070 reg = <0x30880000 0x10000>; 1071 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1073 <&clk IMX8MP_CLK_UART3_ROOT>; 1074 clock-names = "ipg", "per"; 1075 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1076 dma-names = "rx", "tx"; 1077 status = "disabled"; 1078 }; 1079 1080 uart2: serial@30890000 { 1081 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1082 reg = <0x30890000 0x10000>; 1083 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1085 <&clk IMX8MP_CLK_UART2_ROOT>; 1086 clock-names = "ipg", "per"; 1087 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1088 dma-names = "rx", "tx"; 1089 status = "disabled"; 1090 }; 1091 1092 flexcan1: can@308c0000 { 1093 compatible = "fsl,imx8mp-flexcan"; 1094 reg = <0x308c0000 0x10000>; 1095 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1097 <&clk IMX8MP_CLK_CAN1_ROOT>; 1098 clock-names = "ipg", "per"; 1099 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1100 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1101 assigned-clock-rates = <40000000>; 1102 fsl,clk-source = /bits/ 8 <0>; 1103 fsl,stop-mode = <&gpr 0x10 4>; 1104 status = "disabled"; 1105 }; 1106 1107 flexcan2: can@308d0000 { 1108 compatible = "fsl,imx8mp-flexcan"; 1109 reg = <0x308d0000 0x10000>; 1110 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1112 <&clk IMX8MP_CLK_CAN2_ROOT>; 1113 clock-names = "ipg", "per"; 1114 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1115 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1116 assigned-clock-rates = <40000000>; 1117 fsl,clk-source = /bits/ 8 <0>; 1118 fsl,stop-mode = <&gpr 0x10 5>; 1119 status = "disabled"; 1120 }; 1121 }; 1122 1123 crypto: crypto@30900000 { 1124 compatible = "fsl,sec-v4.0"; 1125 #address-cells = <1>; 1126 #size-cells = <1>; 1127 reg = <0x30900000 0x40000>; 1128 ranges = <0 0x30900000 0x40000>; 1129 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&clk IMX8MP_CLK_AHB>, 1131 <&clk IMX8MP_CLK_IPG_ROOT>; 1132 clock-names = "aclk", "ipg"; 1133 1134 sec_jr0: jr@1000 { 1135 compatible = "fsl,sec-v4.0-job-ring"; 1136 reg = <0x1000 0x1000>; 1137 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1138 status = "disabled"; 1139 }; 1140 1141 sec_jr1: jr@2000 { 1142 compatible = "fsl,sec-v4.0-job-ring"; 1143 reg = <0x2000 0x1000>; 1144 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1145 }; 1146 1147 sec_jr2: jr@3000 { 1148 compatible = "fsl,sec-v4.0-job-ring"; 1149 reg = <0x3000 0x1000>; 1150 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1151 }; 1152 }; 1153 1154 i2c1: i2c@30a20000 { 1155 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 reg = <0x30a20000 0x10000>; 1159 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1161 status = "disabled"; 1162 }; 1163 1164 i2c2: i2c@30a30000 { 1165 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 reg = <0x30a30000 0x10000>; 1169 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c3: i2c@30a40000 { 1175 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 reg = <0x30a40000 0x10000>; 1179 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1181 status = "disabled"; 1182 }; 1183 1184 i2c4: i2c@30a50000 { 1185 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 reg = <0x30a50000 0x10000>; 1189 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1191 status = "disabled"; 1192 }; 1193 1194 uart4: serial@30a60000 { 1195 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1196 reg = <0x30a60000 0x10000>; 1197 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1199 <&clk IMX8MP_CLK_UART4_ROOT>; 1200 clock-names = "ipg", "per"; 1201 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1202 dma-names = "rx", "tx"; 1203 status = "disabled"; 1204 }; 1205 1206 mu: mailbox@30aa0000 { 1207 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1208 reg = <0x30aa0000 0x10000>; 1209 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1210 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1211 #mbox-cells = <2>; 1212 }; 1213 1214 mu2: mailbox@30e60000 { 1215 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1216 reg = <0x30e60000 0x10000>; 1217 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1218 #mbox-cells = <2>; 1219 status = "disabled"; 1220 }; 1221 1222 i2c5: i2c@30ad0000 { 1223 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 reg = <0x30ad0000 0x10000>; 1227 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1229 status = "disabled"; 1230 }; 1231 1232 i2c6: i2c@30ae0000 { 1233 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 reg = <0x30ae0000 0x10000>; 1237 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1239 status = "disabled"; 1240 }; 1241 1242 usdhc1: mmc@30b40000 { 1243 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1244 reg = <0x30b40000 0x10000>; 1245 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&clk IMX8MP_CLK_DUMMY>, 1247 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1248 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1249 clock-names = "ipg", "ahb", "per"; 1250 fsl,tuning-start-tap = <20>; 1251 fsl,tuning-step = <2>; 1252 bus-width = <4>; 1253 status = "disabled"; 1254 }; 1255 1256 usdhc2: mmc@30b50000 { 1257 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1258 reg = <0x30b50000 0x10000>; 1259 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&clk IMX8MP_CLK_DUMMY>, 1261 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1262 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1263 clock-names = "ipg", "ahb", "per"; 1264 fsl,tuning-start-tap = <20>; 1265 fsl,tuning-step = <2>; 1266 bus-width = <4>; 1267 status = "disabled"; 1268 }; 1269 1270 usdhc3: mmc@30b60000 { 1271 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1272 reg = <0x30b60000 0x10000>; 1273 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&clk IMX8MP_CLK_DUMMY>, 1275 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1276 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1277 clock-names = "ipg", "ahb", "per"; 1278 fsl,tuning-start-tap = <20>; 1279 fsl,tuning-step = <2>; 1280 bus-width = <4>; 1281 status = "disabled"; 1282 }; 1283 1284 flexspi: spi@30bb0000 { 1285 compatible = "nxp,imx8mp-fspi"; 1286 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1287 reg-names = "fspi_base", "fspi_mmap"; 1288 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1290 <&clk IMX8MP_CLK_QSPI_ROOT>; 1291 clock-names = "fspi_en", "fspi"; 1292 assigned-clock-rates = <80000000>; 1293 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 sdma1: dma-controller@30bd0000 { 1300 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1301 reg = <0x30bd0000 0x10000>; 1302 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1304 <&clk IMX8MP_CLK_AHB>; 1305 clock-names = "ipg", "ahb"; 1306 #dma-cells = <3>; 1307 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1308 }; 1309 1310 fec: ethernet@30be0000 { 1311 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1312 reg = <0x30be0000 0x10000>; 1313 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1318 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1319 <&clk IMX8MP_CLK_ENET_TIMER>, 1320 <&clk IMX8MP_CLK_ENET_REF>, 1321 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1322 clock-names = "ipg", "ahb", "ptp", 1323 "enet_clk_ref", "enet_out"; 1324 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1325 <&clk IMX8MP_CLK_ENET_TIMER>, 1326 <&clk IMX8MP_CLK_ENET_REF>, 1327 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1328 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1329 <&clk IMX8MP_SYS_PLL2_100M>, 1330 <&clk IMX8MP_SYS_PLL2_125M>, 1331 <&clk IMX8MP_SYS_PLL2_50M>; 1332 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1333 fsl,num-tx-queues = <3>; 1334 fsl,num-rx-queues = <3>; 1335 nvmem-cells = <ð_mac1>; 1336 nvmem-cell-names = "mac-address"; 1337 fsl,stop-mode = <&gpr 0x10 3>; 1338 status = "disabled"; 1339 }; 1340 1341 eqos: ethernet@30bf0000 { 1342 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1343 reg = <0x30bf0000 0x10000>; 1344 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1346 interrupt-names = "macirq", "eth_wake_irq"; 1347 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1348 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1349 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1350 <&clk IMX8MP_CLK_ENET_QOS>; 1351 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1352 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1353 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1354 <&clk IMX8MP_CLK_ENET_QOS>; 1355 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1356 <&clk IMX8MP_SYS_PLL2_100M>, 1357 <&clk IMX8MP_SYS_PLL2_125M>; 1358 assigned-clock-rates = <0>, <100000000>, <125000000>; 1359 nvmem-cells = <ð_mac2>; 1360 nvmem-cell-names = "mac-address"; 1361 intf_mode = <&gpr 0x4>; 1362 status = "disabled"; 1363 }; 1364 }; 1365 1366 aips5: bus@30c00000 { 1367 compatible = "fsl,aips-bus", "simple-bus"; 1368 reg = <0x30c00000 0x400000>; 1369 #address-cells = <1>; 1370 #size-cells = <1>; 1371 ranges; 1372 1373 spba-bus@30c00000 { 1374 compatible = "fsl,spba-bus", "simple-bus"; 1375 reg = <0x30c00000 0x100000>; 1376 #address-cells = <1>; 1377 #size-cells = <1>; 1378 ranges; 1379 1380 sai1: sai@30c10000 { 1381 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1382 reg = <0x30c10000 0x10000>; 1383 #sound-dai-cells = <0>; 1384 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1385 <&clk IMX8MP_CLK_DUMMY>, 1386 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1387 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1388 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1389 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1390 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1391 dma-names = "rx", "tx"; 1392 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1393 status = "disabled"; 1394 }; 1395 1396 sai2: sai@30c20000 { 1397 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1398 reg = <0x30c20000 0x10000>; 1399 #sound-dai-cells = <0>; 1400 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1401 <&clk IMX8MP_CLK_DUMMY>, 1402 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1403 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1404 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1405 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1406 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1407 dma-names = "rx", "tx"; 1408 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1409 status = "disabled"; 1410 }; 1411 1412 sai3: sai@30c30000 { 1413 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1414 reg = <0x30c30000 0x10000>; 1415 #sound-dai-cells = <0>; 1416 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1417 <&clk IMX8MP_CLK_DUMMY>, 1418 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1419 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1421 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1422 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1423 dma-names = "rx", "tx"; 1424 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1425 status = "disabled"; 1426 }; 1427 1428 sai5: sai@30c50000 { 1429 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1430 reg = <0x30c50000 0x10000>; 1431 #sound-dai-cells = <0>; 1432 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1433 <&clk IMX8MP_CLK_DUMMY>, 1434 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1435 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1437 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1438 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1439 dma-names = "rx", "tx"; 1440 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1441 status = "disabled"; 1442 }; 1443 1444 sai6: sai@30c60000 { 1445 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1446 reg = <0x30c60000 0x10000>; 1447 #sound-dai-cells = <0>; 1448 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1449 <&clk IMX8MP_CLK_DUMMY>, 1450 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1451 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1453 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1454 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1455 dma-names = "rx", "tx"; 1456 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1457 status = "disabled"; 1458 }; 1459 1460 sai7: sai@30c80000 { 1461 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1462 reg = <0x30c80000 0x10000>; 1463 #sound-dai-cells = <0>; 1464 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1465 <&clk IMX8MP_CLK_DUMMY>, 1466 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1467 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1468 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1469 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1470 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1471 dma-names = "rx", "tx"; 1472 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1473 status = "disabled"; 1474 }; 1475 1476 easrc: easrc@30c90000 { 1477 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1478 reg = <0x30c90000 0x10000>; 1479 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1480 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1481 clock-names = "mem"; 1482 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1483 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1484 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1485 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1486 dma-names = "ctx0_rx", "ctx0_tx", 1487 "ctx1_rx", "ctx1_tx", 1488 "ctx2_rx", "ctx2_tx", 1489 "ctx3_rx", "ctx3_tx"; 1490 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1491 fsl,asrc-rate = <8000>; 1492 fsl,asrc-format = <2>; 1493 status = "disabled"; 1494 }; 1495 1496 micfil: audio-controller@30ca0000 { 1497 compatible = "fsl,imx8mp-micfil"; 1498 reg = <0x30ca0000 0x10000>; 1499 #sound-dai-cells = <0>; 1500 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1504 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1505 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1506 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1507 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1508 <&clk IMX8MP_CLK_EXT3>; 1509 clock-names = "ipg_clk", "ipg_clk_app", 1510 "pll8k", "pll11k", "clkext3"; 1511 dmas = <&sdma2 24 25 0x80000000>; 1512 dma-names = "rx"; 1513 status = "disabled"; 1514 }; 1515 1516 }; 1517 1518 sdma3: dma-controller@30e00000 { 1519 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1520 reg = <0x30e00000 0x10000>; 1521 #dma-cells = <3>; 1522 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1523 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1524 clock-names = "ipg", "ahb"; 1525 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1526 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1527 }; 1528 1529 sdma2: dma-controller@30e10000 { 1530 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1531 reg = <0x30e10000 0x10000>; 1532 #dma-cells = <3>; 1533 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1534 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1535 clock-names = "ipg", "ahb"; 1536 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1537 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1538 }; 1539 1540 audio_blk_ctrl: clock-controller@30e20000 { 1541 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1542 reg = <0x30e20000 0x10000>; 1543 #clock-cells = <1>; 1544 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1545 <&clk IMX8MP_CLK_SAI1>, 1546 <&clk IMX8MP_CLK_SAI2>, 1547 <&clk IMX8MP_CLK_SAI3>, 1548 <&clk IMX8MP_CLK_SAI5>, 1549 <&clk IMX8MP_CLK_SAI6>, 1550 <&clk IMX8MP_CLK_SAI7>; 1551 clock-names = "ahb", 1552 "sai1", "sai2", "sai3", 1553 "sai5", "sai6", "sai7"; 1554 power-domains = <&pgc_audio>; 1555 }; 1556 }; 1557 1558 noc: interconnect@32700000 { 1559 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1560 reg = <0x32700000 0x100000>; 1561 clocks = <&clk IMX8MP_CLK_NOC>; 1562 #interconnect-cells = <1>; 1563 operating-points-v2 = <&noc_opp_table>; 1564 1565 noc_opp_table: opp-table { 1566 compatible = "operating-points-v2"; 1567 1568 opp-200000000 { 1569 opp-hz = /bits/ 64 <200000000>; 1570 }; 1571 1572 opp-1000000000 { 1573 opp-hz = /bits/ 64 <1000000000>; 1574 }; 1575 }; 1576 }; 1577 1578 aips4: bus@32c00000 { 1579 compatible = "fsl,aips-bus", "simple-bus"; 1580 reg = <0x32c00000 0x400000>; 1581 #address-cells = <1>; 1582 #size-cells = <1>; 1583 ranges; 1584 1585 isi_0: isi@32e00000 { 1586 compatible = "fsl,imx8mp-isi"; 1587 reg = <0x32e00000 0x4000>; 1588 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1590 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1591 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1592 clock-names = "axi", "apb"; 1593 fsl,blk-ctrl = <&media_blk_ctrl>; 1594 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1595 status = "disabled"; 1596 1597 ports { 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 port@0 { 1602 reg = <0>; 1603 1604 isi_in_0: endpoint { 1605 remote-endpoint = <&mipi_csi_0_out>; 1606 }; 1607 }; 1608 1609 port@1 { 1610 reg = <1>; 1611 1612 isi_in_1: endpoint { 1613 remote-endpoint = <&mipi_csi_1_out>; 1614 }; 1615 }; 1616 }; 1617 }; 1618 1619 dewarp: dwe@32e30000 { 1620 compatible = "nxp,imx8mp-dw100"; 1621 reg = <0x32e30000 0x10000>; 1622 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1624 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1625 clock-names = "axi", "ahb"; 1626 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1627 }; 1628 1629 mipi_csi_0: csi@32e40000 { 1630 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1631 reg = <0x32e40000 0x10000>; 1632 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1633 clock-frequency = <500000000>; 1634 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1635 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1636 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1637 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1638 clock-names = "pclk", "wrap", "phy", "axi"; 1639 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; 1640 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1641 assigned-clock-rates = <500000000>; 1642 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1643 status = "disabled"; 1644 1645 ports { 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 port@0 { 1650 reg = <0>; 1651 }; 1652 1653 port@1 { 1654 reg = <1>; 1655 1656 mipi_csi_0_out: endpoint { 1657 remote-endpoint = <&isi_in_0>; 1658 }; 1659 }; 1660 }; 1661 }; 1662 1663 mipi_csi_1: csi@32e50000 { 1664 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1665 reg = <0x32e50000 0x10000>; 1666 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1667 clock-frequency = <266000000>; 1668 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1669 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1670 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1671 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1672 clock-names = "pclk", "wrap", "phy", "axi"; 1673 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; 1674 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1675 assigned-clock-rates = <266000000>; 1676 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1677 status = "disabled"; 1678 1679 ports { 1680 #address-cells = <1>; 1681 #size-cells = <0>; 1682 1683 port@0 { 1684 reg = <0>; 1685 }; 1686 1687 port@1 { 1688 reg = <1>; 1689 1690 mipi_csi_1_out: endpoint { 1691 remote-endpoint = <&isi_in_1>; 1692 }; 1693 }; 1694 }; 1695 }; 1696 1697 mipi_dsi: dsi@32e60000 { 1698 compatible = "fsl,imx8mp-mipi-dsim"; 1699 reg = <0x32e60000 0x400>; 1700 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1701 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1702 clock-names = "bus_clk", "sclk_mipi"; 1703 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1704 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1705 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1706 <&clk IMX8MP_CLK_24M>; 1707 assigned-clock-rates = <200000000>, <24000000>; 1708 samsung,pll-clock-frequency = <24000000>; 1709 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1710 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1711 status = "disabled"; 1712 1713 ports { 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 1717 port@0 { 1718 reg = <0>; 1719 1720 dsim_from_lcdif1: endpoint { 1721 remote-endpoint = <&lcdif1_to_dsim>; 1722 }; 1723 }; 1724 }; 1725 }; 1726 1727 lcdif1: display-controller@32e80000 { 1728 compatible = "fsl,imx8mp-lcdif"; 1729 reg = <0x32e80000 0x10000>; 1730 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1731 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1732 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1733 clock-names = "pix", "axi", "disp_axi"; 1734 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1735 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1736 status = "disabled"; 1737 1738 port { 1739 lcdif1_to_dsim: endpoint { 1740 remote-endpoint = <&dsim_from_lcdif1>; 1741 }; 1742 }; 1743 }; 1744 1745 lcdif2: display-controller@32e90000 { 1746 compatible = "fsl,imx8mp-lcdif"; 1747 reg = <0x32e90000 0x10000>; 1748 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1750 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1751 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1752 clock-names = "pix", "axi", "disp_axi"; 1753 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1754 status = "disabled"; 1755 1756 port { 1757 lcdif2_to_ldb: endpoint { 1758 remote-endpoint = <&ldb_from_lcdif2>; 1759 }; 1760 }; 1761 }; 1762 1763 media_blk_ctrl: blk-ctrl@32ec0000 { 1764 compatible = "fsl,imx8mp-media-blk-ctrl", 1765 "syscon"; 1766 reg = <0x32ec0000 0x10000>; 1767 #address-cells = <1>; 1768 #size-cells = <1>; 1769 power-domains = <&pgc_mediamix>, 1770 <&pgc_mipi_phy1>, 1771 <&pgc_mipi_phy1>, 1772 <&pgc_mediamix>, 1773 <&pgc_mediamix>, 1774 <&pgc_mipi_phy2>, 1775 <&pgc_mediamix>, 1776 <&pgc_ispdwp>, 1777 <&pgc_ispdwp>, 1778 <&pgc_mipi_phy2>; 1779 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1780 "lcdif1", "isi", "mipi-csi2", 1781 "lcdif2", "isp", "dwe", 1782 "mipi-dsi2"; 1783 interconnects = 1784 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1785 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1786 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1787 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1788 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1789 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1790 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1791 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1792 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1793 "isi1", "isi2", "isp0", "isp1", 1794 "dwe"; 1795 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1796 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1797 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1798 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1799 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1800 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1801 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1802 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1803 clock-names = "apb", "axi", "cam1", "cam2", 1804 "disp1", "disp2", "isp", "phy"; 1805 1806 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1807 <&clk IMX8MP_CLK_MEDIA_APB>, 1808 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1809 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1810 <&clk IMX8MP_VIDEO_PLL1>; 1811 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1812 <&clk IMX8MP_SYS_PLL1_800M>, 1813 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1814 <&clk IMX8MP_VIDEO_PLL1_OUT>; 1815 assigned-clock-rates = <500000000>, <200000000>, 1816 <0>, <0>, <1039500000>; 1817 #power-domain-cells = <1>; 1818 1819 lvds_bridge: bridge@5c { 1820 compatible = "fsl,imx8mp-ldb"; 1821 reg = <0x5c 0x4>, <0x128 0x4>; 1822 reg-names = "ldb", "lvds"; 1823 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 1824 clock-names = "ldb"; 1825 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1826 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1827 status = "disabled"; 1828 1829 ports { 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 1833 port@0 { 1834 reg = <0>; 1835 1836 ldb_from_lcdif2: endpoint { 1837 remote-endpoint = <&lcdif2_to_ldb>; 1838 }; 1839 }; 1840 1841 port@1 { 1842 reg = <1>; 1843 1844 ldb_lvds_ch0: endpoint { 1845 }; 1846 }; 1847 1848 port@2 { 1849 reg = <2>; 1850 1851 ldb_lvds_ch1: endpoint { 1852 }; 1853 }; 1854 }; 1855 }; 1856 }; 1857 1858 pcie_phy: pcie-phy@32f00000 { 1859 compatible = "fsl,imx8mp-pcie-phy"; 1860 reg = <0x32f00000 0x10000>; 1861 resets = <&src IMX8MP_RESET_PCIEPHY>, 1862 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1863 reset-names = "pciephy", "perst"; 1864 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1865 #phy-cells = <0>; 1866 status = "disabled"; 1867 }; 1868 1869 hsio_blk_ctrl: blk-ctrl@32f10000 { 1870 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1871 reg = <0x32f10000 0x24>; 1872 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1873 <&clk IMX8MP_CLK_PCIE_ROOT>; 1874 clock-names = "usb", "pcie"; 1875 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1876 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1877 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1878 power-domain-names = "bus", "usb", "usb-phy1", 1879 "usb-phy2", "pcie", "pcie-phy"; 1880 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1881 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1882 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1883 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1884 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1885 #power-domain-cells = <1>; 1886 #clock-cells = <0>; 1887 }; 1888 }; 1889 1890 pcie: pcie@33800000 { 1891 compatible = "fsl,imx8mp-pcie"; 1892 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1893 reg-names = "dbi", "config"; 1894 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1895 <&clk IMX8MP_CLK_HSIO_AXI>, 1896 <&clk IMX8MP_CLK_PCIE_ROOT>; 1897 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1898 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1899 assigned-clock-rates = <10000000>; 1900 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1901 #address-cells = <3>; 1902 #size-cells = <2>; 1903 device_type = "pci"; 1904 bus-range = <0x00 0xff>; 1905 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1906 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1907 num-lanes = <1>; 1908 num-viewport = <4>; 1909 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1910 interrupt-names = "msi"; 1911 #interrupt-cells = <1>; 1912 interrupt-map-mask = <0 0 0 0x7>; 1913 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1914 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1915 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1916 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1917 fsl,max-link-speed = <3>; 1918 linux,pci-domain = <0>; 1919 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1920 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1921 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1922 reset-names = "apps", "turnoff"; 1923 phys = <&pcie_phy>; 1924 phy-names = "pcie-phy"; 1925 status = "disabled"; 1926 }; 1927 1928 pcie_ep: pcie-ep@33800000 { 1929 compatible = "fsl,imx8mp-pcie-ep"; 1930 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 1931 reg-names = "dbi", "addr_space"; 1932 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1933 <&clk IMX8MP_CLK_HSIO_AXI>, 1934 <&clk IMX8MP_CLK_PCIE_ROOT>; 1935 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1936 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1937 assigned-clock-rates = <10000000>; 1938 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1939 num-lanes = <1>; 1940 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 1941 interrupt-names = "dma"; 1942 fsl,max-link-speed = <3>; 1943 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1944 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1945 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1946 reset-names = "apps", "turnoff"; 1947 phys = <&pcie_phy>; 1948 phy-names = "pcie-phy"; 1949 num-ib-windows = <4>; 1950 num-ob-windows = <4>; 1951 status = "disabled"; 1952 }; 1953 1954 gpu3d: gpu@38000000 { 1955 compatible = "vivante,gc"; 1956 reg = <0x38000000 0x8000>; 1957 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1958 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1959 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1960 <&clk IMX8MP_CLK_GPU_ROOT>, 1961 <&clk IMX8MP_CLK_GPU_AHB>; 1962 clock-names = "core", "shader", "bus", "reg"; 1963 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1964 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1965 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1966 <&clk IMX8MP_SYS_PLL1_800M>; 1967 assigned-clock-rates = <800000000>, <800000000>; 1968 power-domains = <&pgc_gpu3d>; 1969 }; 1970 1971 gpu2d: gpu@38008000 { 1972 compatible = "vivante,gc"; 1973 reg = <0x38008000 0x8000>; 1974 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1975 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1976 <&clk IMX8MP_CLK_GPU_ROOT>, 1977 <&clk IMX8MP_CLK_GPU_AHB>; 1978 clock-names = "core", "bus", "reg"; 1979 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1980 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1981 assigned-clock-rates = <800000000>; 1982 power-domains = <&pgc_gpu2d>; 1983 }; 1984 1985 vpu_g1: video-codec@38300000 { 1986 compatible = "nxp,imx8mm-vpu-g1"; 1987 reg = <0x38300000 0x10000>; 1988 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1989 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 1990 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 1991 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1992 assigned-clock-rates = <600000000>; 1993 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 1994 }; 1995 1996 vpu_g2: video-codec@38310000 { 1997 compatible = "nxp,imx8mq-vpu-g2"; 1998 reg = <0x38310000 0x10000>; 1999 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2001 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 2002 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2003 assigned-clock-rates = <500000000>; 2004 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2005 }; 2006 2007 vpumix_blk_ctrl: blk-ctrl@38330000 { 2008 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2009 reg = <0x38330000 0x100>; 2010 #power-domain-cells = <1>; 2011 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2012 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2013 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2014 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2015 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2016 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2017 clock-names = "g1", "g2", "vc8000e"; 2018 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 2019 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2020 assigned-clock-rates = <600000000>, <600000000>; 2021 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2022 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2023 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2024 interconnect-names = "g1", "g2", "vc8000e"; 2025 }; 2026 2027 npu: npu@38500000 { 2028 compatible = "vivante,gc"; 2029 reg = <0x38500000 0x200000>; 2030 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2031 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2032 <&clk IMX8MP_CLK_NPU_ROOT>, 2033 <&clk IMX8MP_CLK_ML_AXI>, 2034 <&clk IMX8MP_CLK_ML_AHB>; 2035 clock-names = "core", "shader", "bus", "reg"; 2036 power-domains = <&pgc_mlmix>; 2037 }; 2038 2039 gic: interrupt-controller@38800000 { 2040 compatible = "arm,gic-v3"; 2041 reg = <0x38800000 0x10000>, 2042 <0x38880000 0xc0000>; 2043 #interrupt-cells = <3>; 2044 interrupt-controller; 2045 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2046 interrupt-parent = <&gic>; 2047 }; 2048 2049 edacmc: memory-controller@3d400000 { 2050 compatible = "snps,ddrc-3.80a"; 2051 reg = <0x3d400000 0x400000>; 2052 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2053 }; 2054 2055 ddr-pmu@3d800000 { 2056 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2057 reg = <0x3d800000 0x400000>; 2058 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2059 }; 2060 2061 usb3_phy0: usb-phy@381f0040 { 2062 compatible = "fsl,imx8mp-usb-phy"; 2063 reg = <0x381f0040 0x40>; 2064 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2065 clock-names = "phy"; 2066 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2067 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2068 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2069 #phy-cells = <0>; 2070 status = "disabled"; 2071 }; 2072 2073 usb3_0: usb@32f10100 { 2074 compatible = "fsl,imx8mp-dwc3"; 2075 reg = <0x32f10100 0x8>, 2076 <0x381f0000 0x20>; 2077 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2078 <&clk IMX8MP_CLK_USB_SUSP>; 2079 clock-names = "hsio", "suspend"; 2080 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2081 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2082 #address-cells = <1>; 2083 #size-cells = <1>; 2084 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2085 ranges; 2086 status = "disabled"; 2087 2088 usb_dwc3_0: usb@38100000 { 2089 compatible = "snps,dwc3"; 2090 reg = <0x38100000 0x10000>; 2091 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2092 <&clk IMX8MP_CLK_USB_CORE_REF>, 2093 <&clk IMX8MP_CLK_USB_SUSP>; 2094 clock-names = "bus_early", "ref", "suspend"; 2095 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2096 phys = <&usb3_phy0>, <&usb3_phy0>; 2097 phy-names = "usb2-phy", "usb3-phy"; 2098 snps,gfladj-refclk-lpm-sel-quirk; 2099 snps,parkmode-disable-ss-quirk; 2100 }; 2101 2102 }; 2103 2104 usb3_phy1: usb-phy@382f0040 { 2105 compatible = "fsl,imx8mp-usb-phy"; 2106 reg = <0x382f0040 0x40>; 2107 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2108 clock-names = "phy"; 2109 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2110 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2111 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2112 #phy-cells = <0>; 2113 status = "disabled"; 2114 }; 2115 2116 usb3_1: usb@32f10108 { 2117 compatible = "fsl,imx8mp-dwc3"; 2118 reg = <0x32f10108 0x8>, 2119 <0x382f0000 0x20>; 2120 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2121 <&clk IMX8MP_CLK_USB_SUSP>; 2122 clock-names = "hsio", "suspend"; 2123 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2124 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2125 #address-cells = <1>; 2126 #size-cells = <1>; 2127 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2128 ranges; 2129 status = "disabled"; 2130 2131 usb_dwc3_1: usb@38200000 { 2132 compatible = "snps,dwc3"; 2133 reg = <0x38200000 0x10000>; 2134 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2135 <&clk IMX8MP_CLK_USB_CORE_REF>, 2136 <&clk IMX8MP_CLK_USB_SUSP>; 2137 clock-names = "bus_early", "ref", "suspend"; 2138 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2139 phys = <&usb3_phy1>, <&usb3_phy1>; 2140 phy-names = "usb2-phy", "usb3-phy"; 2141 snps,gfladj-refclk-lpm-sel-quirk; 2142 snps,parkmode-disable-ss-quirk; 2143 }; 2144 }; 2145 2146 dsp: dsp@3b6e8000 { 2147 compatible = "fsl,imx8mp-dsp"; 2148 reg = <0x3b6e8000 0x88000>; 2149 mbox-names = "txdb0", "txdb1", 2150 "rxdb0", "rxdb1"; 2151 mboxes = <&mu2 2 0>, <&mu2 2 1>, 2152 <&mu2 3 0>, <&mu2 3 1>; 2153 memory-region = <&dsp_reserved>; 2154 status = "disabled"; 2155 }; 2156 }; 2157}; 2158