1*5f62a964SEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*5f62a964SEmmanuel Vadot/* 3*5f62a964SEmmanuel Vadot * Copyright 2024 Gateworks Corporation 4*5f62a964SEmmanuel Vadot */ 5*5f62a964SEmmanuel Vadot 6*5f62a964SEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 7*5f62a964SEmmanuel Vadot#include <dt-bindings/leds/common.h> 8*5f62a964SEmmanuel Vadot#include <dt-bindings/phy/phy-imx8-pcie.h> 9*5f62a964SEmmanuel Vadot 10*5f62a964SEmmanuel Vadot/ { 11*5f62a964SEmmanuel Vadot aliases { 12*5f62a964SEmmanuel Vadot ethernet1 = ð1; 13*5f62a964SEmmanuel Vadot fsa1 = &fsa0; 14*5f62a964SEmmanuel Vadot fsa2 = &fsa1; 15*5f62a964SEmmanuel Vadot }; 16*5f62a964SEmmanuel Vadot 17*5f62a964SEmmanuel Vadot led-controller { 18*5f62a964SEmmanuel Vadot compatible = "gpio-leds"; 19*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 20*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_gpio_leds>; 21*5f62a964SEmmanuel Vadot 22*5f62a964SEmmanuel Vadot led-0 { 23*5f62a964SEmmanuel Vadot function = LED_FUNCTION_STATUS; 24*5f62a964SEmmanuel Vadot color = <LED_COLOR_ID_GREEN>; 25*5f62a964SEmmanuel Vadot gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 26*5f62a964SEmmanuel Vadot default-state = "on"; 27*5f62a964SEmmanuel Vadot linux,default-trigger = "heartbeat"; 28*5f62a964SEmmanuel Vadot }; 29*5f62a964SEmmanuel Vadot 30*5f62a964SEmmanuel Vadot led-1 { 31*5f62a964SEmmanuel Vadot function = LED_FUNCTION_STATUS; 32*5f62a964SEmmanuel Vadot color = <LED_COLOR_ID_RED>; 33*5f62a964SEmmanuel Vadot gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 34*5f62a964SEmmanuel Vadot default-state = "off"; 35*5f62a964SEmmanuel Vadot }; 36*5f62a964SEmmanuel Vadot }; 37*5f62a964SEmmanuel Vadot 38*5f62a964SEmmanuel Vadot pcie0_refclk: clock-pcie0 { 39*5f62a964SEmmanuel Vadot compatible = "fixed-clock"; 40*5f62a964SEmmanuel Vadot #clock-cells = <0>; 41*5f62a964SEmmanuel Vadot clock-frequency = <100000000>; 42*5f62a964SEmmanuel Vadot }; 43*5f62a964SEmmanuel Vadot 44*5f62a964SEmmanuel Vadot pps { 45*5f62a964SEmmanuel Vadot compatible = "pps-gpio"; 46*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 47*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_pps>; 48*5f62a964SEmmanuel Vadot gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 49*5f62a964SEmmanuel Vadot }; 50*5f62a964SEmmanuel Vadot 51*5f62a964SEmmanuel Vadot reg_usb2_vbus: regulator-usb2 { 52*5f62a964SEmmanuel Vadot compatible = "regulator-fixed"; 53*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 54*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_reg_usb2_en>; 55*5f62a964SEmmanuel Vadot regulator-name = "usb2_vbus"; 56*5f62a964SEmmanuel Vadot regulator-min-microvolt = <5000000>; 57*5f62a964SEmmanuel Vadot regulator-max-microvolt = <5000000>; 58*5f62a964SEmmanuel Vadot gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 59*5f62a964SEmmanuel Vadot enable-active-high; 60*5f62a964SEmmanuel Vadot }; 61*5f62a964SEmmanuel Vadot 62*5f62a964SEmmanuel Vadot reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 63*5f62a964SEmmanuel Vadot compatible = "regulator-fixed"; 64*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 65*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 66*5f62a964SEmmanuel Vadot regulator-name = "VDD_3V3_SD"; 67*5f62a964SEmmanuel Vadot regulator-max-microvolt = <3300000>; 68*5f62a964SEmmanuel Vadot regulator-min-microvolt = <3300000>; 69*5f62a964SEmmanuel Vadot gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 70*5f62a964SEmmanuel Vadot enable-active-high; 71*5f62a964SEmmanuel Vadot off-on-delay-us = <12000>; 72*5f62a964SEmmanuel Vadot startup-delay-us = <100>; 73*5f62a964SEmmanuel Vadot }; 74*5f62a964SEmmanuel Vadot}; 75*5f62a964SEmmanuel Vadot 76*5f62a964SEmmanuel Vadot&ecspi2 { 77*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 78*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_spi2>; 79*5f62a964SEmmanuel Vadot cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */ 80*5f62a964SEmmanuel Vadot <&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */ 81*5f62a964SEmmanuel Vadot <&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */ 82*5f62a964SEmmanuel Vadot <&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */ 83*5f62a964SEmmanuel Vadot status = "okay"; 84*5f62a964SEmmanuel Vadot 85*5f62a964SEmmanuel Vadot tpm@0 { 86*5f62a964SEmmanuel Vadot compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 87*5f62a964SEmmanuel Vadot reg = <0x0>; 88*5f62a964SEmmanuel Vadot spi-max-frequency = <10000000>; 89*5f62a964SEmmanuel Vadot }; 90*5f62a964SEmmanuel Vadot}; 91*5f62a964SEmmanuel Vadot 92*5f62a964SEmmanuel Vadot&flexcan1 { 93*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 94*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_can1>; 95*5f62a964SEmmanuel Vadot status = "okay"; 96*5f62a964SEmmanuel Vadot}; 97*5f62a964SEmmanuel Vadot 98*5f62a964SEmmanuel Vadot&flexcan2 { 99*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 100*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_can2>; 101*5f62a964SEmmanuel Vadot status = "okay"; 102*5f62a964SEmmanuel Vadot}; 103*5f62a964SEmmanuel Vadot 104*5f62a964SEmmanuel Vadot&gpio1 { 105*5f62a964SEmmanuel Vadot gpio-line-names = 106*5f62a964SEmmanuel Vadot "", "", "", "", 107*5f62a964SEmmanuel Vadot "", "", "", "", 108*5f62a964SEmmanuel Vadot "", "", "", "", 109*5f62a964SEmmanuel Vadot "", "fsa2_gpio1", "", "", 110*5f62a964SEmmanuel Vadot "", "", "", "", 111*5f62a964SEmmanuel Vadot "", "", "", "", 112*5f62a964SEmmanuel Vadot "", "", "", "", 113*5f62a964SEmmanuel Vadot "", "", "", ""; 114*5f62a964SEmmanuel Vadot}; 115*5f62a964SEmmanuel Vadot 116*5f62a964SEmmanuel Vadot&gpio4 { 117*5f62a964SEmmanuel Vadot gpio-line-names = 118*5f62a964SEmmanuel Vadot "", "", "", "", 119*5f62a964SEmmanuel Vadot "", "", "", "", 120*5f62a964SEmmanuel Vadot "dio1", "fsa1_gpio2", "", "dio0", 121*5f62a964SEmmanuel Vadot "", "", "", "", 122*5f62a964SEmmanuel Vadot "", "", "", "", 123*5f62a964SEmmanuel Vadot "", "", "rs485_en", "rs485_term", 124*5f62a964SEmmanuel Vadot "fsa2_gpio2", "fsa1_gpio1", "", "rs485_half", 125*5f62a964SEmmanuel Vadot "", "", "", ""; 126*5f62a964SEmmanuel Vadot}; 127*5f62a964SEmmanuel Vadot 128*5f62a964SEmmanuel Vadot&i2c2 { 129*5f62a964SEmmanuel Vadot accelerometer@19 { 130*5f62a964SEmmanuel Vadot compatible = "st,lis2de12"; 131*5f62a964SEmmanuel Vadot reg = <0x19>; 132*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 133*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_accel>; 134*5f62a964SEmmanuel Vadot interrupt-parent = <&gpio4>; 135*5f62a964SEmmanuel Vadot interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 136*5f62a964SEmmanuel Vadot st,drdy-int-pin = <1>; 137*5f62a964SEmmanuel Vadot }; 138*5f62a964SEmmanuel Vadot 139*5f62a964SEmmanuel Vadot magnetometer@1e { 140*5f62a964SEmmanuel Vadot compatible = "st,lis2mdl"; 141*5f62a964SEmmanuel Vadot reg = <0x1e>; 142*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 143*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_mag>; 144*5f62a964SEmmanuel Vadot interrupt-parent = <&gpio4>; 145*5f62a964SEmmanuel Vadot interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 146*5f62a964SEmmanuel Vadot }; 147*5f62a964SEmmanuel Vadot}; 148*5f62a964SEmmanuel Vadot 149*5f62a964SEmmanuel Vadot&i2c3 { 150*5f62a964SEmmanuel Vadot i2c-mux@70 { 151*5f62a964SEmmanuel Vadot compatible = "nxp,pca9548"; 152*5f62a964SEmmanuel Vadot reg = <0x70>; 153*5f62a964SEmmanuel Vadot #address-cells = <1>; 154*5f62a964SEmmanuel Vadot #size-cells = <0>; 155*5f62a964SEmmanuel Vadot 156*5f62a964SEmmanuel Vadot /* J30 */ 157*5f62a964SEmmanuel Vadot fsa1: i2c@0 { 158*5f62a964SEmmanuel Vadot reg = <0>; 159*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 160*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_fsa2i2c>; 161*5f62a964SEmmanuel Vadot #address-cells = <1>; 162*5f62a964SEmmanuel Vadot #size-cells = <0>; 163*5f62a964SEmmanuel Vadot 164*5f62a964SEmmanuel Vadot gpio@20 { 165*5f62a964SEmmanuel Vadot compatible = "nxp,pca9555"; 166*5f62a964SEmmanuel Vadot reg = <0x20>; 167*5f62a964SEmmanuel Vadot interrupt-parent = <&gpio4>; 168*5f62a964SEmmanuel Vadot interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 169*5f62a964SEmmanuel Vadot interrupt-controller; 170*5f62a964SEmmanuel Vadot #interrupt-cells = <2>; 171*5f62a964SEmmanuel Vadot gpio-controller; 172*5f62a964SEmmanuel Vadot #gpio-cells = <2>; 173*5f62a964SEmmanuel Vadot }; 174*5f62a964SEmmanuel Vadot 175*5f62a964SEmmanuel Vadot eeprom@54 { 176*5f62a964SEmmanuel Vadot compatible = "atmel,24c02"; 177*5f62a964SEmmanuel Vadot reg = <0x54>; 178*5f62a964SEmmanuel Vadot pagesize = <16>; 179*5f62a964SEmmanuel Vadot }; 180*5f62a964SEmmanuel Vadot 181*5f62a964SEmmanuel Vadot eeprom@55 { 182*5f62a964SEmmanuel Vadot compatible = "atmel,24c02"; 183*5f62a964SEmmanuel Vadot reg = <0x55>; 184*5f62a964SEmmanuel Vadot pagesize = <16>; 185*5f62a964SEmmanuel Vadot }; 186*5f62a964SEmmanuel Vadot }; 187*5f62a964SEmmanuel Vadot 188*5f62a964SEmmanuel Vadot /* J29 */ 189*5f62a964SEmmanuel Vadot fsa0: i2c@1 { 190*5f62a964SEmmanuel Vadot reg = <1>; 191*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 192*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_fsa1i2c>; 193*5f62a964SEmmanuel Vadot #address-cells = <1>; 194*5f62a964SEmmanuel Vadot #size-cells = <0>; 195*5f62a964SEmmanuel Vadot 196*5f62a964SEmmanuel Vadot gpio@20 { 197*5f62a964SEmmanuel Vadot compatible = "nxp,pca9555"; 198*5f62a964SEmmanuel Vadot reg = <0x20>; 199*5f62a964SEmmanuel Vadot interrupt-parent = <&gpio4>; 200*5f62a964SEmmanuel Vadot interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 201*5f62a964SEmmanuel Vadot interrupt-controller; 202*5f62a964SEmmanuel Vadot #interrupt-cells = <2>; 203*5f62a964SEmmanuel Vadot gpio-controller; 204*5f62a964SEmmanuel Vadot #gpio-cells = <2>; 205*5f62a964SEmmanuel Vadot }; 206*5f62a964SEmmanuel Vadot 207*5f62a964SEmmanuel Vadot eeprom@54 { 208*5f62a964SEmmanuel Vadot compatible = "atmel,24c02"; 209*5f62a964SEmmanuel Vadot reg = <0x54>; 210*5f62a964SEmmanuel Vadot pagesize = <16>; 211*5f62a964SEmmanuel Vadot }; 212*5f62a964SEmmanuel Vadot 213*5f62a964SEmmanuel Vadot eeprom@55 { 214*5f62a964SEmmanuel Vadot compatible = "atmel,24c02"; 215*5f62a964SEmmanuel Vadot reg = <0x55>; 216*5f62a964SEmmanuel Vadot pagesize = <16>; 217*5f62a964SEmmanuel Vadot }; 218*5f62a964SEmmanuel Vadot }; 219*5f62a964SEmmanuel Vadot 220*5f62a964SEmmanuel Vadot /* J33 */ 221*5f62a964SEmmanuel Vadot i2c@2 { 222*5f62a964SEmmanuel Vadot reg = <2>; 223*5f62a964SEmmanuel Vadot #address-cells = <1>; 224*5f62a964SEmmanuel Vadot #size-cells = <0>; 225*5f62a964SEmmanuel Vadot }; 226*5f62a964SEmmanuel Vadot }; 227*5f62a964SEmmanuel Vadot}; 228*5f62a964SEmmanuel Vadot 229*5f62a964SEmmanuel Vadot&pcie_phy { 230*5f62a964SEmmanuel Vadot clocks = <&pcie0_refclk>; 231*5f62a964SEmmanuel Vadot clock-names = "ref"; 232*5f62a964SEmmanuel Vadot fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 233*5f62a964SEmmanuel Vadot fsl,clkreq-unsupported; 234*5f62a964SEmmanuel Vadot status = "okay"; 235*5f62a964SEmmanuel Vadot}; 236*5f62a964SEmmanuel Vadot 237*5f62a964SEmmanuel Vadot&pcie { 238*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 239*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_pcie0>; 240*5f62a964SEmmanuel Vadot reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 241*5f62a964SEmmanuel Vadot status = "okay"; 242*5f62a964SEmmanuel Vadot 243*5f62a964SEmmanuel Vadot pcie@0,0 { 244*5f62a964SEmmanuel Vadot reg = <0x0000 0 0 0 0>; 245*5f62a964SEmmanuel Vadot device_type = "pci"; 246*5f62a964SEmmanuel Vadot #address-cells = <3>; 247*5f62a964SEmmanuel Vadot #size-cells = <2>; 248*5f62a964SEmmanuel Vadot ranges; 249*5f62a964SEmmanuel Vadot 250*5f62a964SEmmanuel Vadot pcie@0,0 { 251*5f62a964SEmmanuel Vadot reg = <0x0000 0 0 0 0>; 252*5f62a964SEmmanuel Vadot device_type = "pci"; 253*5f62a964SEmmanuel Vadot #address-cells = <3>; 254*5f62a964SEmmanuel Vadot #size-cells = <2>; 255*5f62a964SEmmanuel Vadot ranges; 256*5f62a964SEmmanuel Vadot 257*5f62a964SEmmanuel Vadot pcie@7,0 { 258*5f62a964SEmmanuel Vadot reg = <0x3800 0 0 0 0>; 259*5f62a964SEmmanuel Vadot device_type = "pci"; 260*5f62a964SEmmanuel Vadot #address-cells = <3>; 261*5f62a964SEmmanuel Vadot #size-cells = <2>; 262*5f62a964SEmmanuel Vadot ranges; 263*5f62a964SEmmanuel Vadot 264*5f62a964SEmmanuel Vadot eth1: ethernet@0,0 { 265*5f62a964SEmmanuel Vadot reg = <0x0000 0 0 0 0>; 266*5f62a964SEmmanuel Vadot #address-cells = <3>; 267*5f62a964SEmmanuel Vadot #size-cells = <2>; 268*5f62a964SEmmanuel Vadot ranges; 269*5f62a964SEmmanuel Vadot local-mac-address = [00 00 00 00 00 00]; 270*5f62a964SEmmanuel Vadot }; 271*5f62a964SEmmanuel Vadot }; 272*5f62a964SEmmanuel Vadot }; 273*5f62a964SEmmanuel Vadot }; 274*5f62a964SEmmanuel Vadot}; 275*5f62a964SEmmanuel Vadot 276*5f62a964SEmmanuel Vadot/* GPS */ 277*5f62a964SEmmanuel Vadot&uart1 { 278*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 279*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_uart1>; 280*5f62a964SEmmanuel Vadot status = "okay"; 281*5f62a964SEmmanuel Vadot}; 282*5f62a964SEmmanuel Vadot 283*5f62a964SEmmanuel Vadot/* RS232 */ 284*5f62a964SEmmanuel Vadot&uart4 { 285*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 286*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_uart4>; 287*5f62a964SEmmanuel Vadot status = "okay"; 288*5f62a964SEmmanuel Vadot}; 289*5f62a964SEmmanuel Vadot 290*5f62a964SEmmanuel Vadot/* USB1 - FSA1 */ 291*5f62a964SEmmanuel Vadot&usb3_0 { 292*5f62a964SEmmanuel Vadot fsl,permanently-attached; 293*5f62a964SEmmanuel Vadot fsl,disable-port-power-control; 294*5f62a964SEmmanuel Vadot status = "okay"; 295*5f62a964SEmmanuel Vadot}; 296*5f62a964SEmmanuel Vadot 297*5f62a964SEmmanuel Vadot&usb3_phy0 { 298*5f62a964SEmmanuel Vadot status = "okay"; 299*5f62a964SEmmanuel Vadot}; 300*5f62a964SEmmanuel Vadot 301*5f62a964SEmmanuel Vadot&usb_dwc3_0 { 302*5f62a964SEmmanuel Vadot dr_mode = "host"; 303*5f62a964SEmmanuel Vadot status = "okay"; 304*5f62a964SEmmanuel Vadot}; 305*5f62a964SEmmanuel Vadot 306*5f62a964SEmmanuel Vadot/* USB2 - USB3.0 Hub */ 307*5f62a964SEmmanuel Vadot&usb3_1 { 308*5f62a964SEmmanuel Vadot fsl,permanently-attached; 309*5f62a964SEmmanuel Vadot fsl,disable-port-power-control; 310*5f62a964SEmmanuel Vadot status = "okay"; 311*5f62a964SEmmanuel Vadot}; 312*5f62a964SEmmanuel Vadot 313*5f62a964SEmmanuel Vadot&usb3_phy1 { 314*5f62a964SEmmanuel Vadot vbus-supply = <®_usb2_vbus>; 315*5f62a964SEmmanuel Vadot status = "okay"; 316*5f62a964SEmmanuel Vadot}; 317*5f62a964SEmmanuel Vadot 318*5f62a964SEmmanuel Vadot&usb_dwc3_1 { 319*5f62a964SEmmanuel Vadot dr_mode = "host"; 320*5f62a964SEmmanuel Vadot status = "okay"; 321*5f62a964SEmmanuel Vadot}; 322*5f62a964SEmmanuel Vadot 323*5f62a964SEmmanuel Vadot/* SDIO 1.8V */ 324*5f62a964SEmmanuel Vadot&usdhc1 { 325*5f62a964SEmmanuel Vadot pinctrl-names = "default", "state_100mhz", "state_200mhz"; 326*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc1>; 327*5f62a964SEmmanuel Vadot pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 328*5f62a964SEmmanuel Vadot pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 329*5f62a964SEmmanuel Vadot bus-width = <4>; 330*5f62a964SEmmanuel Vadot non-removable; 331*5f62a964SEmmanuel Vadot status = "okay"; 332*5f62a964SEmmanuel Vadot}; 333*5f62a964SEmmanuel Vadot 334*5f62a964SEmmanuel Vadot/* microSD */ 335*5f62a964SEmmanuel Vadot&usdhc2 { 336*5f62a964SEmmanuel Vadot pinctrl-names = "default", "state_100mhz", "state_200mhz"; 337*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 338*5f62a964SEmmanuel Vadot pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 339*5f62a964SEmmanuel Vadot pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 340*5f62a964SEmmanuel Vadot cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */ 341*5f62a964SEmmanuel Vadot bus-width = <4>; 342*5f62a964SEmmanuel Vadot vmmc-supply = <®_usdhc2_vmmc>; 343*5f62a964SEmmanuel Vadot status = "okay"; 344*5f62a964SEmmanuel Vadot}; 345*5f62a964SEmmanuel Vadot 346*5f62a964SEmmanuel Vadot&iomuxc { 347*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 348*5f62a964SEmmanuel Vadot pinctrl-0 = <&pinctrl_hog>; 349*5f62a964SEmmanuel Vadot 350*5f62a964SEmmanuel Vadot pinctrl_hog: hoggrp { 351*5f62a964SEmmanuel Vadot fsl,pins = < 352*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 353*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 354*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 355*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 356*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 357*5f62a964SEmmanuel Vadot >; 358*5f62a964SEmmanuel Vadot }; 359*5f62a964SEmmanuel Vadot 360*5f62a964SEmmanuel Vadot pinctrl_accel: accelgrp { 361*5f62a964SEmmanuel Vadot fsl,pins = < 362*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */ 363*5f62a964SEmmanuel Vadot >; 364*5f62a964SEmmanuel Vadot }; 365*5f62a964SEmmanuel Vadot 366*5f62a964SEmmanuel Vadot pinctrl_can1: can1grp { 367*5f62a964SEmmanuel Vadot fsl,pins = < 368*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 369*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 370*5f62a964SEmmanuel Vadot >; 371*5f62a964SEmmanuel Vadot }; 372*5f62a964SEmmanuel Vadot 373*5f62a964SEmmanuel Vadot pinctrl_can2: can2grp { 374*5f62a964SEmmanuel Vadot fsl,pins = < 375*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 376*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 377*5f62a964SEmmanuel Vadot >; 378*5f62a964SEmmanuel Vadot }; 379*5f62a964SEmmanuel Vadot 380*5f62a964SEmmanuel Vadot pinctrl_gpio_leds: gpioledgrp { 381*5f62a964SEmmanuel Vadot fsl,pins = < 382*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 383*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 384*5f62a964SEmmanuel Vadot >; 385*5f62a964SEmmanuel Vadot }; 386*5f62a964SEmmanuel Vadot 387*5f62a964SEmmanuel Vadot pinctrl_fsa1i2c: fsa1i2cgrp { 388*5f62a964SEmmanuel Vadot fsl,pins = < 389*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */ 390*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */ 391*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */ 392*5f62a964SEmmanuel Vadot >; 393*5f62a964SEmmanuel Vadot }; 394*5f62a964SEmmanuel Vadot 395*5f62a964SEmmanuel Vadot pinctrl_fsa2i2c: fsa2i2cgrp { 396*5f62a964SEmmanuel Vadot fsl,pins = < 397*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */ 398*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */ 399*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */ 400*5f62a964SEmmanuel Vadot >; 401*5f62a964SEmmanuel Vadot }; 402*5f62a964SEmmanuel Vadot 403*5f62a964SEmmanuel Vadot pinctrl_mag: maggrp { 404*5f62a964SEmmanuel Vadot fsl,pins = < 405*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */ 406*5f62a964SEmmanuel Vadot >; 407*5f62a964SEmmanuel Vadot }; 408*5f62a964SEmmanuel Vadot 409*5f62a964SEmmanuel Vadot pinctrl_pcie0: pcie0grp { 410*5f62a964SEmmanuel Vadot fsl,pins = < 411*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */ 412*5f62a964SEmmanuel Vadot >; 413*5f62a964SEmmanuel Vadot }; 414*5f62a964SEmmanuel Vadot 415*5f62a964SEmmanuel Vadot pinctrl_pps: ppsgrp { 416*5f62a964SEmmanuel Vadot fsl,pins = < 417*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 418*5f62a964SEmmanuel Vadot >; 419*5f62a964SEmmanuel Vadot }; 420*5f62a964SEmmanuel Vadot 421*5f62a964SEmmanuel Vadot pinctrl_reg_usb2_en: regusb2grp { 422*5f62a964SEmmanuel Vadot fsl,pins = < 423*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 424*5f62a964SEmmanuel Vadot >; 425*5f62a964SEmmanuel Vadot }; 426*5f62a964SEmmanuel Vadot 427*5f62a964SEmmanuel Vadot pinctrl_spi2: spi2grp { 428*5f62a964SEmmanuel Vadot fsl,pins = < 429*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0 430*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0 431*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0 432*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */ 433*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */ 434*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */ 435*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */ 436*5f62a964SEmmanuel Vadot >; 437*5f62a964SEmmanuel Vadot }; 438*5f62a964SEmmanuel Vadot 439*5f62a964SEmmanuel Vadot pinctrl_uart1: uart1grp { 440*5f62a964SEmmanuel Vadot fsl,pins = < 441*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 442*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 443*5f62a964SEmmanuel Vadot >; 444*5f62a964SEmmanuel Vadot }; 445*5f62a964SEmmanuel Vadot 446*5f62a964SEmmanuel Vadot pinctrl_uart4: uart4grp { 447*5f62a964SEmmanuel Vadot fsl,pins = < 448*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 449*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 450*5f62a964SEmmanuel Vadot >; 451*5f62a964SEmmanuel Vadot }; 452*5f62a964SEmmanuel Vadot 453*5f62a964SEmmanuel Vadot pinctrl_usdhc1: usdhc1grp { 454*5f62a964SEmmanuel Vadot fsl,pins = < 455*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 456*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 457*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 458*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 459*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 460*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 461*5f62a964SEmmanuel Vadot >; 462*5f62a964SEmmanuel Vadot }; 463*5f62a964SEmmanuel Vadot 464*5f62a964SEmmanuel Vadot pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 465*5f62a964SEmmanuel Vadot fsl,pins = < 466*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 467*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 468*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 469*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 470*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 471*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 472*5f62a964SEmmanuel Vadot >; 473*5f62a964SEmmanuel Vadot }; 474*5f62a964SEmmanuel Vadot 475*5f62a964SEmmanuel Vadot pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 476*5f62a964SEmmanuel Vadot fsl,pins = < 477*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 478*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 479*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 480*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 481*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 482*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 483*5f62a964SEmmanuel Vadot >; 484*5f62a964SEmmanuel Vadot }; 485*5f62a964SEmmanuel Vadot 486*5f62a964SEmmanuel Vadot pinctrl_usdhc2: usdhc2grp { 487*5f62a964SEmmanuel Vadot fsl,pins = < 488*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 489*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 490*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 491*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 492*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 493*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 494*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 495*5f62a964SEmmanuel Vadot >; 496*5f62a964SEmmanuel Vadot }; 497*5f62a964SEmmanuel Vadot 498*5f62a964SEmmanuel Vadot pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 499*5f62a964SEmmanuel Vadot fsl,pins = < 500*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 501*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 502*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 503*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 504*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 505*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 506*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 507*5f62a964SEmmanuel Vadot >; 508*5f62a964SEmmanuel Vadot }; 509*5f62a964SEmmanuel Vadot 510*5f62a964SEmmanuel Vadot pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 511*5f62a964SEmmanuel Vadot fsl,pins = < 512*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 513*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 514*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 515*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 516*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 517*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 518*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 519*5f62a964SEmmanuel Vadot >; 520*5f62a964SEmmanuel Vadot }; 521*5f62a964SEmmanuel Vadot 522*5f62a964SEmmanuel Vadot pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 523*5f62a964SEmmanuel Vadot fsl,pins = < 524*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0 525*5f62a964SEmmanuel Vadot >; 526*5f62a964SEmmanuel Vadot }; 527*5f62a964SEmmanuel Vadot 528*5f62a964SEmmanuel Vadot pinctrl_usdhc2_gpio: usdhc2gpiogrp { 529*5f62a964SEmmanuel Vadot fsl,pins = < 530*5f62a964SEmmanuel Vadot MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 531*5f62a964SEmmanuel Vadot >; 532*5f62a964SEmmanuel Vadot }; 533*5f62a964SEmmanuel Vadot}; 534