1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mp.dtsi" 14 15/ { 16 model = "Gateworks Venice GW74xx i.MX8MP board"; 17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; 18 19 aliases { 20 ethernet0 = &eqos; 21 ethernet1 = &fec; 22 ethernet2 = &lan1; 23 ethernet3 = &lan2; 24 ethernet4 = &lan3; 25 ethernet5 = &lan4; 26 ethernet6 = &lan5; 27 }; 28 29 chosen { 30 stdout-path = &uart2; 31 }; 32 33 memory@40000000 { 34 device_type = "memory"; 35 reg = <0x0 0x40000000 0 0x80000000>; 36 }; 37 38 gpio-keys { 39 compatible = "gpio-keys"; 40 41 key-0 { 42 label = "user_pb"; 43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 44 linux,code = <BTN_0>; 45 }; 46 47 key-1 { 48 label = "user_pb1x"; 49 linux,code = <BTN_1>; 50 interrupt-parent = <&gsc>; 51 interrupts = <0>; 52 }; 53 54 key-2 { 55 label = "key_erased"; 56 linux,code = <BTN_2>; 57 interrupt-parent = <&gsc>; 58 interrupts = <1>; 59 }; 60 61 key-3 { 62 label = "eeprom_wp"; 63 linux,code = <BTN_3>; 64 interrupt-parent = <&gsc>; 65 interrupts = <2>; 66 }; 67 68 key-4 { 69 label = "tamper"; 70 linux,code = <BTN_4>; 71 interrupt-parent = <&gsc>; 72 interrupts = <5>; 73 }; 74 75 key-5 { 76 label = "switch_hold"; 77 linux,code = <BTN_5>; 78 interrupt-parent = <&gsc>; 79 interrupts = <7>; 80 }; 81 }; 82 83 led-controller { 84 compatible = "gpio-leds"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_gpio_leds>; 87 88 led-0 { 89 function = LED_FUNCTION_HEARTBEAT; 90 color = <LED_COLOR_ID_GREEN>; 91 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 92 default-state = "on"; 93 linux,default-trigger = "heartbeat"; 94 }; 95 96 led-1 { 97 function = LED_FUNCTION_STATUS; 98 color = <LED_COLOR_ID_RED>; 99 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 100 default-state = "off"; 101 }; 102 }; 103 104 pcie0_refclk: pcie0-refclk { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <100000000>; 108 }; 109 110 pps { 111 compatible = "pps-gpio"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_pps>; 114 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 115 }; 116 117 reg_usb2_vbus: regulator-usb2 { 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_reg_usb2>; 120 compatible = "regulator-fixed"; 121 regulator-name = "usb_usb2_vbus"; 122 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; 123 enable-active-high; 124 regulator-min-microvolt = <5000000>; 125 regulator-max-microvolt = <5000000>; 126 }; 127 128 reg_can2_stby: regulator-can2-stby { 129 compatible = "regulator-fixed"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_reg_can>; 132 regulator-name = "can2_stby"; 133 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 134 regulator-min-microvolt = <3300000>; 135 regulator-max-microvolt = <3300000>; 136 }; 137 138 reg_wifi_en: regulator-wifi-en { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_reg_wifi>; 141 compatible = "regulator-fixed"; 142 regulator-name = "wl"; 143 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 144 startup-delay-us = <70000>; 145 enable-active-high; 146 regulator-min-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>; 148 }; 149}; 150 151&A53_0 { 152 cpu-supply = <®_arm>; 153}; 154 155&A53_1 { 156 cpu-supply = <®_arm>; 157}; 158 159&A53_2 { 160 cpu-supply = <®_arm>; 161}; 162 163&A53_3 { 164 cpu-supply = <®_arm>; 165}; 166 167/* off-board header */ 168&ecspi2 { 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_spi2>; 171 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 172 status = "okay"; 173}; 174 175&eqos { 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_eqos>; 178 phy-mode = "rgmii-id"; 179 phy-handle = <ðphy0>; 180 status = "okay"; 181 182 mdio { 183 compatible = "snps,dwmac-mdio"; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 ethphy0: ethernet-phy@0 { 188 compatible = "ethernet-phy-ieee802.3-c22"; 189 reg = <0x0>; 190 }; 191 }; 192}; 193 194&fec { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_fec>; 197 phy-mode = "rgmii-id"; 198 local-mac-address = [00 00 00 00 00 00]; 199 status = "okay"; 200 201 fixed-link { 202 speed = <1000>; 203 full-duplex; 204 }; 205}; 206 207&flexcan2 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_flexcan2>; 210 xceiver-supply = <®_can2_stby>; 211 status = "okay"; 212}; 213 214&gpio1 { 215 gpio-line-names = 216 "", "", "", "", "", "", "", "", 217 "", "", "dio0", "", "dio1", "", "", "", 218 "", "", "", "", "", "", "", "", 219 "", "", "", "", "", "", "", ""; 220}; 221 222&gpio2 { 223 gpio-line-names = 224 "", "", "", "", "", "", "", "", 225 "", "", "", "", "", "", "pcie3_wdis#", "", 226 "", "", "pcie2_wdis#", "", "", "", "", "", 227 "", "", "", "", "", "", "", ""; 228}; 229 230&gpio3 { 231 gpio-line-names = 232 "m2_gdis#", "", "", "", "", "", "", "m2_rst#", 233 "", "", "", "", "", "", "", "", 234 "m2_off#", "", "", "", "", "", "", "", 235 "", "", "", "", "", "", "", ""; 236}; 237 238&gpio4 { 239 gpio-line-names = 240 "", "", "", "", "", "", "", "", 241 "", "", "", "", "", "", "", "", 242 "", "", "", "", "m2_wdis#", "", "", "", 243 "", "", "", "", "", "", "", "uart_rs485"; 244}; 245 246&gpio5 { 247 gpio-line-names = 248 "uart_half", "uart_term", "", "", "", "", "", "", 249 "", "", "", "", "", "", "", "", 250 "", "", "", "", "", "", "", "", 251 "", "", "", "", "", "", "", ""; 252}; 253 254&i2c1 { 255 clock-frequency = <100000>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c1>; 258 status = "okay"; 259 260 gsc: gsc@20 { 261 compatible = "gw,gsc"; 262 reg = <0x20>; 263 pinctrl-0 = <&pinctrl_gsc>; 264 interrupt-parent = <&gpio4>; 265 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 266 interrupt-controller; 267 #interrupt-cells = <1>; 268 269 adc { 270 compatible = "gw,gsc-adc"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 channel@6 { 275 gw,mode = <0>; 276 reg = <0x06>; 277 label = "temp"; 278 }; 279 280 channel@8 { 281 gw,mode = <1>; 282 reg = <0x08>; 283 label = "vdd_bat"; 284 }; 285 286 channel@82 { 287 gw,mode = <2>; 288 reg = <0x82>; 289 label = "vdd_adc1"; 290 gw,voltage-divider-ohms = <10000 10000>; 291 }; 292 293 channel@84 { 294 gw,mode = <2>; 295 reg = <0x84>; 296 label = "vdd_adc2"; 297 gw,voltage-divider-ohms = <10000 10000>; 298 }; 299 300 channel@86 { 301 gw,mode = <2>; 302 reg = <0x86>; 303 label = "vdd_vin"; 304 gw,voltage-divider-ohms = <22100 1000>; 305 }; 306 307 channel@88 { 308 gw,mode = <2>; 309 reg = <0x88>; 310 label = "vdd_3p3"; 311 gw,voltage-divider-ohms = <10000 10000>; 312 }; 313 314 channel@8c { 315 gw,mode = <2>; 316 reg = <0x8c>; 317 label = "vdd_2p5"; 318 gw,voltage-divider-ohms = <10000 10000>; 319 }; 320 321 channel@90 { 322 gw,mode = <2>; 323 reg = <0x90>; 324 label = "vdd_soc"; 325 }; 326 327 channel@92 { 328 gw,mode = <2>; 329 reg = <0x92>; 330 label = "vdd_arm"; 331 }; 332 333 channel@98 { 334 gw,mode = <2>; 335 reg = <0x98>; 336 label = "vdd_1p8"; 337 }; 338 339 channel@9a { 340 gw,mode = <2>; 341 reg = <0x9a>; 342 label = "vdd_1p2"; 343 }; 344 345 channel@9c { 346 gw,mode = <2>; 347 reg = <0x9c>; 348 label = "vdd_dram"; 349 }; 350 351 channel@a2 { 352 gw,mode = <2>; 353 reg = <0xa2>; 354 label = "vdd_gsc"; 355 gw,voltage-divider-ohms = <10000 10000>; 356 }; 357 }; 358 }; 359 360 gpio: gpio@23 { 361 compatible = "nxp,pca9555"; 362 reg = <0x23>; 363 gpio-controller; 364 #gpio-cells = <2>; 365 interrupt-parent = <&gsc>; 366 interrupts = <4>; 367 }; 368 369 pmic@25 { 370 compatible = "nxp,pca9450c"; 371 reg = <0x25>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_pmic>; 374 interrupt-parent = <&gpio3>; 375 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 376 377 regulators { 378 BUCK1 { 379 regulator-name = "BUCK1"; 380 regulator-min-microvolt = <720000>; 381 regulator-max-microvolt = <1000000>; 382 regulator-boot-on; 383 regulator-always-on; 384 regulator-ramp-delay = <3125>; 385 }; 386 387 reg_arm: BUCK2 { 388 regulator-name = "BUCK2"; 389 regulator-min-microvolt = <720000>; 390 regulator-max-microvolt = <1025000>; 391 regulator-boot-on; 392 regulator-always-on; 393 regulator-ramp-delay = <3125>; 394 nxp,dvs-run-voltage = <950000>; 395 nxp,dvs-standby-voltage = <850000>; 396 }; 397 398 BUCK4 { 399 regulator-name = "BUCK4"; 400 regulator-min-microvolt = <3000000>; 401 regulator-max-microvolt = <3600000>; 402 regulator-boot-on; 403 regulator-always-on; 404 }; 405 406 BUCK5 { 407 regulator-name = "BUCK5"; 408 regulator-min-microvolt = <1650000>; 409 regulator-max-microvolt = <1950000>; 410 regulator-boot-on; 411 regulator-always-on; 412 }; 413 414 BUCK6 { 415 regulator-name = "BUCK6"; 416 regulator-min-microvolt = <1045000>; 417 regulator-max-microvolt = <1155000>; 418 regulator-boot-on; 419 regulator-always-on; 420 }; 421 422 LDO1 { 423 regulator-name = "LDO1"; 424 regulator-min-microvolt = <1650000>; 425 regulator-max-microvolt = <1950000>; 426 regulator-boot-on; 427 regulator-always-on; 428 }; 429 430 LDO3 { 431 regulator-name = "LDO3"; 432 regulator-min-microvolt = <1710000>; 433 regulator-max-microvolt = <1890000>; 434 regulator-boot-on; 435 regulator-always-on; 436 }; 437 438 LDO5 { 439 regulator-name = "LDO5"; 440 regulator-min-microvolt = <1800000>; 441 regulator-max-microvolt = <3300000>; 442 regulator-boot-on; 443 regulator-always-on; 444 }; 445 }; 446 }; 447 448 eeprom@50 { 449 compatible = "atmel,24c02"; 450 reg = <0x50>; 451 pagesize = <16>; 452 }; 453 454 eeprom@51 { 455 compatible = "atmel,24c02"; 456 reg = <0x51>; 457 pagesize = <16>; 458 }; 459 460 eeprom@52 { 461 compatible = "atmel,24c02"; 462 reg = <0x52>; 463 pagesize = <16>; 464 }; 465 466 eeprom@53 { 467 compatible = "atmel,24c02"; 468 reg = <0x53>; 469 pagesize = <16>; 470 }; 471 472 rtc@68 { 473 compatible = "dallas,ds1672"; 474 reg = <0x68>; 475 }; 476}; 477 478&i2c2 { 479 clock-frequency = <400000>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_i2c2>; 482 status = "okay"; 483 484 accelerometer@19 { 485 compatible = "st,lis2de12"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pinctrl_accel>; 488 reg = <0x19>; 489 st,drdy-int-pin = <1>; 490 interrupt-parent = <&gpio1>; 491 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 492 interrupt-names = "INT1"; 493 }; 494 495 switch: switch@5f { 496 compatible = "microchip,ksz9897"; 497 reg = <0x5f>; 498 pinctrl-0 = <&pinctrl_ksz>; 499 interrupt-parent = <&gpio4>; 500 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 501 502 ports { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 lan1: port@0 { 507 reg = <0>; 508 label = "lan1"; 509 phy-mode = "internal"; 510 local-mac-address = [00 00 00 00 00 00]; 511 }; 512 513 lan2: port@1 { 514 reg = <1>; 515 label = "lan2"; 516 phy-mode = "internal"; 517 local-mac-address = [00 00 00 00 00 00]; 518 }; 519 520 lan3: port@2 { 521 reg = <2>; 522 label = "lan3"; 523 phy-mode = "internal"; 524 local-mac-address = [00 00 00 00 00 00]; 525 }; 526 527 lan4: port@3 { 528 reg = <3>; 529 label = "lan4"; 530 phy-mode = "internal"; 531 local-mac-address = [00 00 00 00 00 00]; 532 }; 533 534 lan5: port@4 { 535 reg = <4>; 536 label = "lan5"; 537 phy-mode = "internal"; 538 local-mac-address = [00 00 00 00 00 00]; 539 }; 540 541 port@5 { 542 reg = <5>; 543 label = "cpu"; 544 ethernet = <&fec>; 545 phy-mode = "rgmii-id"; 546 547 fixed-link { 548 speed = <1000>; 549 full-duplex; 550 }; 551 }; 552 }; 553 }; 554}; 555 556/* off-board header */ 557&i2c3 { 558 clock-frequency = <400000>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pinctrl_i2c3>; 561 status = "okay"; 562}; 563 564/* off-board header */ 565&i2c4 { 566 clock-frequency = <400000>; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_i2c4>; 569 status = "okay"; 570}; 571 572&pcie_phy { 573 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 574 fsl,clkreq-unsupported; 575 clocks = <&pcie0_refclk>; 576 clock-names = "ref"; 577 status = "okay"; 578}; 579 580&pcie { 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pinctrl_pcie0>; 583 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; 584 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 585 <&clk IMX8MP_CLK_PCIE_ROOT>, 586 <&clk IMX8MP_CLK_HSIO_AXI>; 587 clock-names = "pcie", "pcie_aux", "pcie_bus"; 588 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 589 assigned-clock-rates = <10000000>; 590 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 591 status = "okay"; 592}; 593 594/* GPS / off-board header */ 595&uart1 { 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pinctrl_uart1>; 598 status = "okay"; 599}; 600 601/* RS232 console */ 602&uart2 { 603 pinctrl-names = "default"; 604 pinctrl-0 = <&pinctrl_uart2>; 605 status = "okay"; 606}; 607 608/* bluetooth HCI */ 609&uart3 { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 612 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 613 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 614 uart-has-rtscts; 615 status = "okay"; 616 617 bluetooth { 618 compatible = "brcm,bcm4330-bt"; 619 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; 620 }; 621}; 622 623&uart4 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_uart4>; 626 status = "okay"; 627}; 628 629/* USB1 - Type C front panel */ 630&usb3_0 { 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_usb1>; 633 fsl,over-current-active-low; 634 status = "okay"; 635}; 636 637&usb3_phy0 { 638 status = "okay"; 639}; 640 641&usb_dwc3_0 { 642 /* dual role is implemented but not a full featured OTG */ 643 adp-disable; 644 hnp-disable; 645 srp-disable; 646 dr_mode = "otg"; 647 usb-role-switch; 648 role-switch-default-mode = "peripheral"; 649 status = "okay"; 650 651 connector { 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_usbcon1>; 654 compatible = "gpio-usb-b-connector", "usb-b-connector"; 655 type = "micro"; 656 label = "Type-C"; 657 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 658 }; 659}; 660 661/* USB2 - USB3.0 Hub */ 662&usb3_phy1 { 663 vbus-supply = <®_usb2_vbus>; 664 status = "okay"; 665}; 666 667&usb3_1 { 668 fsl,permanently-attached; 669 fsl,disable-port-power-control; 670 status = "okay"; 671}; 672 673&usb_dwc3_1 { 674 dr_mode = "host"; 675 status = "okay"; 676}; 677 678/* SDIO WiFi */ 679&usdhc1 { 680 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 681 pinctrl-0 = <&pinctrl_usdhc1>; 682 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 683 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 684 bus-width = <4>; 685 non-removable; 686 vmmc-supply = <®_wifi_en>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "okay"; 690 691 wifi@0 { 692 compatible = "cypress,cyw4373-fmac"; 693 reg = <0>; 694 }; 695}; 696 697/* eMMC */ 698&usdhc3 { 699 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 700 assigned-clock-rates = <400000000>; 701 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 702 pinctrl-0 = <&pinctrl_usdhc3>; 703 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 704 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 705 bus-width = <8>; 706 non-removable; 707 status = "okay"; 708}; 709 710&wdog1 { 711 pinctrl-names = "default"; 712 pinctrl-0 = <&pinctrl_wdog>; 713 fsl,ext-reset-output; 714 status = "okay"; 715}; 716 717&iomuxc { 718 pinctrl-names = "default"; 719 pinctrl-0 = <&pinctrl_hog>; 720 721 pinctrl_hog: hoggrp { 722 fsl,pins = < 723 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ 724 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ 725 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ 726 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 727 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 728 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 729 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ 730 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ 731 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 732 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 733 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ 734 >; 735 }; 736 737 pinctrl_accel: accelgrp { 738 fsl,pins = < 739 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 740 >; 741 }; 742 743 pinctrl_eqos: eqosgrp { 744 fsl,pins = < 745 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 746 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 747 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 748 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 749 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 750 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 751 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 752 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 753 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 754 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 755 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 756 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 757 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 758 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 759 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ 760 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ 761 >; 762 }; 763 764 pinctrl_fec: fecgrp { 765 fsl,pins = < 766 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 767 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 768 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 769 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 770 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 771 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 772 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 773 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 774 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 775 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 776 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 777 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 778 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 779 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 780 >; 781 }; 782 783 pinctrl_flexcan2: flexcan2grp { 784 fsl,pins = < 785 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 786 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 787 >; 788 }; 789 790 pinctrl_gsc: gscgrp { 791 fsl,pins = < 792 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 793 >; 794 }; 795 796 pinctrl_i2c1: i2c1grp { 797 fsl,pins = < 798 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 799 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 800 >; 801 }; 802 803 pinctrl_i2c2: i2c2grp { 804 fsl,pins = < 805 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 806 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 807 >; 808 }; 809 810 pinctrl_i2c3: i2c3grp { 811 fsl,pins = < 812 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 813 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 814 >; 815 }; 816 817 pinctrl_i2c4: i2c4grp { 818 fsl,pins = < 819 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 820 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 821 >; 822 }; 823 824 pinctrl_ksz: kszgrp { 825 fsl,pins = < 826 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ 827 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ 828 >; 829 }; 830 831 pinctrl_gpio_leds: ledgrp { 832 fsl,pins = < 833 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 834 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 835 >; 836 }; 837 838 pinctrl_pcie0: pciegrp { 839 fsl,pins = < 840 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 841 >; 842 }; 843 844 pinctrl_pmic: pmicgrp { 845 fsl,pins = < 846 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 847 >; 848 }; 849 850 pinctrl_pps: ppsgrp { 851 fsl,pins = < 852 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 853 >; 854 }; 855 856 pinctrl_reg_can: regcangrp { 857 fsl,pins = < 858 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 859 >; 860 }; 861 862 pinctrl_reg_usb2: regusb2grp { 863 fsl,pins = < 864 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 865 >; 866 }; 867 868 pinctrl_reg_wifi: regwifigrp { 869 fsl,pins = < 870 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 871 >; 872 }; 873 874 pinctrl_sai2: sai2grp { 875 fsl,pins = < 876 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 877 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 878 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 879 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 880 >; 881 }; 882 883 pinctrl_spi2: spi2grp { 884 fsl,pins = < 885 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 886 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 887 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 888 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 889 >; 890 }; 891 892 pinctrl_uart1: uart1grp { 893 fsl,pins = < 894 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 895 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 896 >; 897 }; 898 899 pinctrl_uart2: uart2grp { 900 fsl,pins = < 901 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 902 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 903 >; 904 }; 905 906 pinctrl_uart3: uart3grp { 907 fsl,pins = < 908 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 909 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 910 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 911 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 912 >; 913 }; 914 915 pinctrl_uart3_gpio: uart3gpiogrp { 916 fsl,pins = < 917 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 918 >; 919 }; 920 921 pinctrl_uart4: uart4grp { 922 fsl,pins = < 923 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 924 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 925 >; 926 }; 927 928 pinctrl_usb1: usb1grp { 929 fsl,pins = < 930 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 931 >; 932 }; 933 934 pinctrl_usbcon1: usb1congrp { 935 fsl,pins = < 936 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 937 >; 938 }; 939 940 pinctrl_usdhc1: usdhc1grp { 941 fsl,pins = < 942 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 943 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 944 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 945 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 946 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 947 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 948 >; 949 }; 950 951 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 952 fsl,pins = < 953 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 954 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 955 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 956 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 957 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 958 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 959 >; 960 }; 961 962 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 963 fsl,pins = < 964 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 965 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 966 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 967 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 968 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 969 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 970 >; 971 }; 972 973 pinctrl_usdhc3: usdhc3grp { 974 fsl,pins = < 975 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 976 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 977 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 978 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 979 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 980 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 981 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 982 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 983 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 984 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 985 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 986 >; 987 }; 988 989 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 990 fsl,pins = < 991 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 992 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 993 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 994 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 995 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 996 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 997 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 998 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 999 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1000 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1001 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1002 >; 1003 }; 1004 1005 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1006 fsl,pins = < 1007 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1008 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1009 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1010 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1011 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1012 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1013 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1014 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1015 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1016 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1017 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1018 >; 1019 }; 1020 1021 pinctrl_wdog: wdoggrp { 1022 fsl,pins = < 1023 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 1024 >; 1025 }; 1026}; 1027