1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 connector { 12 compatible = "gpio-usb-b-connector", "usb-b-connector"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_usbcon1>; 15 type = "micro"; 16 label = "otg"; 17 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 18 19 port { 20 usb_dr_connector: endpoint { 21 remote-endpoint = <&usb3_dwc>; 22 }; 23 }; 24 }; 25 26 led-controller { 27 compatible = "gpio-leds"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_gpio_leds>; 30 31 led-0 { 32 function = LED_FUNCTION_STATUS; 33 color = <LED_COLOR_ID_GREEN>; 34 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 35 default-state = "on"; 36 linux,default-trigger = "heartbeat"; 37 }; 38 39 led-1 { 40 function = LED_FUNCTION_STATUS; 41 color = <LED_COLOR_ID_RED>; 42 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 43 default-state = "off"; 44 }; 45 }; 46 47 pcie0_refclk: clock-pcie0 { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <100000000>; 51 }; 52 53 pps { 54 compatible = "pps-gpio"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_pps>; 57 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 58 status = "okay"; 59 }; 60 61 reg_usb1_vbus: regulator-usb1 { 62 compatible = "regulator-fixed"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_reg_usb1_en>; 65 regulator-name = "usb1_vbus"; 66 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 }; 71 72 reg_usb2_vbus: regulator-usb2 { 73 compatible = "regulator-fixed"; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_reg_usb2_en>; 76 regulator-name = "usb2_vbus"; 77 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 78 enable-active-high; 79 regulator-min-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>; 81 }; 82 83 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 87 regulator-name = "VDD_3V3_SD"; 88 enable-active-high; 89 gpio = <&gpio2 19 0>; /* SD2_RESET */ 90 off-on-delay-us = <12000>; 91 regulator-max-microvolt = <3300000>; 92 regulator-min-microvolt = <3300000>; 93 startup-delay-us = <100>; 94 }; 95}; 96 97/* off-board header */ 98&ecspi2 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_spi2>; 101 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 102 <&gpio1 10 GPIO_ACTIVE_LOW>; 103 status = "okay"; 104 105 tpm@1 { 106 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 107 reg = <0x1>; 108 spi-max-frequency = <36000000>; 109 }; 110}; 111 112&gpio4 { 113 gpio-line-names = 114 "", "", "", "", 115 "", "", "", "", 116 "dio1", "", "", "dio0", 117 "", "", "pci_usb_sel", "", 118 "", "", "", "", 119 "", "", "rs485_en", "rs485_term", 120 "", "", "", "rs485_half", 121 "pci_wdis#", "", "", ""; 122}; 123 124&i2c2 { 125 clock-frequency = <400000>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_i2c2>; 128 status = "okay"; 129 130 accelerometer@19 { 131 compatible = "st,lis2de12"; 132 reg = <0x19>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_accel>; 135 st,drdy-int-pin = <1>; 136 interrupt-parent = <&gpio4>; 137 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 138 }; 139}; 140 141&pcie_phy { 142 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 143 fsl,clkreq-unsupported; 144 clocks = <&pcie0_refclk>; 145 clock-names = "ref"; 146 status = "okay"; 147}; 148 149&pcie { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_pcie0>; 152 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 153 status = "okay"; 154}; 155 156/* GPS */ 157&uart1 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_uart1>; 160 status = "okay"; 161}; 162 163/* off-board header */ 164&uart3 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_uart3>; 167 status = "okay"; 168}; 169 170/* RS232 */ 171&uart4 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_uart4>; 174 status = "okay"; 175}; 176 177/* USB1 - OTG */ 178&usb3_0 { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_usb1>; 181 fsl,over-current-active-low; 182 status = "okay"; 183}; 184 185&usb3_phy0 { 186 vbus-supply = <®_usb1_vbus>; 187 status = "okay"; 188}; 189 190&usb_dwc3_0 { 191 /* dual role is implemented but not a full featured OTG */ 192 adp-disable; 193 hnp-disable; 194 srp-disable; 195 dr_mode = "otg"; 196 usb-role-switch; 197 role-switch-default-mode = "peripheral"; 198 status = "okay"; 199 200 port { 201 usb3_dwc: endpoint { 202 remote-endpoint = <&usb_dr_connector>; 203 }; 204 }; 205}; 206 207/* USB2 - USB3.0 Hub */ 208&usb3_1 { 209 fsl,permanently-attached; 210 fsl,disable-port-power-control; 211 status = "okay"; 212}; 213 214&usb3_phy1 { 215 vbus-supply = <®_usb2_vbus>; 216 status = "okay"; 217}; 218 219&usb_dwc3_1 { 220 dr_mode = "host"; 221 status = "okay"; 222}; 223 224/* microSD */ 225&usdhc2 { 226 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 227 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 228 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 229 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 230 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 231 bus-width = <4>; 232 vmmc-supply = <®_usdhc2_vmmc>; 233 status = "okay"; 234}; 235 236&iomuxc { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_hog>; 239 240 pinctrl_hog: hoggrp { 241 fsl,pins = < 242 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 243 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 244 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ 245 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 246 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 247 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 248 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ 249 >; 250 }; 251 252 pinctrl_accel: accelgrp { 253 fsl,pins = < 254 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ 255 >; 256 }; 257 258 pinctrl_gpio_leds: gpioledgrp { 259 fsl,pins = < 260 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 261 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 262 >; 263 }; 264 265 pinctrl_pcie0: pcie0grp { 266 fsl,pins = < 267 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 268 >; 269 }; 270 271 pinctrl_pps: ppsgrp { 272 fsl,pins = < 273 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 274 >; 275 }; 276 277 pinctrl_reg_usb1_en: regusb1grp { 278 fsl,pins = < 279 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ 280 >; 281 }; 282 283 pinctrl_usb1: usb1grp { 284 fsl,pins = < 285 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ 286 >; 287 }; 288 289 pinctrl_usbcon1: usbcon1grp { 290 fsl,pins = < 291 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ 292 >; 293 }; 294 295 pinctrl_reg_usb2_en: regusb2grp { 296 fsl,pins = < 297 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 298 >; 299 }; 300 301 pinctrl_spi2: spi2grp { 302 fsl,pins = < 303 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 304 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 305 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 306 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 307 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 308 >; 309 }; 310 311 pinctrl_uart1: uart1grp { 312 fsl,pins = < 313 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 314 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 315 >; 316 }; 317 318 pinctrl_uart3: uart3grp { 319 fsl,pins = < 320 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 321 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 322 >; 323 }; 324 325 pinctrl_uart4: uart4grp { 326 fsl,pins = < 327 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 328 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 329 >; 330 }; 331 332 pinctrl_usdhc1: usdhc1grp { 333 fsl,pins = < 334 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 335 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 336 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 337 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 338 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 339 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 340 >; 341 }; 342 343 pinctrl_usdhc2: usdhc2grp { 344 fsl,pins = < 345 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 346 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 347 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 348 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 349 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 350 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 351 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 352 >; 353 }; 354 355 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 356 fsl,pins = < 357 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 358 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 359 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 360 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 361 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 362 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 363 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 364 >; 365 }; 366 367 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 368 fsl,pins = < 369 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 370 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 371 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 372 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 373 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 374 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 375 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 376 >; 377 }; 378 379 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 380 fsl,pins = < 381 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 382 >; 383 }; 384 385 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 386 fsl,pins = < 387 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 388 >; 389 }; 390}; 391