1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/leds/common.h> 9#include <dt-bindings/net/ti-dp83867.h> 10 11/ { 12 aliases { 13 ethernet0 = &eqos; 14 rtc0 = &gsc_rtc; 15 rtc1 = &snvs_rtc; 16 }; 17 18 memory@40000000 { 19 device_type = "memory"; 20 reg = <0x0 0x40000000 0 0x80000000>; 21 }; 22 23 gpio-keys { 24 compatible = "gpio-keys"; 25 26 key-user-pb { 27 label = "user_pb"; 28 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 29 linux,code = <BTN_0>; 30 }; 31 32 key-user-pb1x { 33 label = "user_pb1x"; 34 linux,code = <BTN_1>; 35 interrupt-parent = <&gsc>; 36 interrupts = <0>; 37 }; 38 39 key-erased { 40 label = "key_erased"; 41 linux,code = <BTN_2>; 42 interrupt-parent = <&gsc>; 43 interrupts = <1>; 44 }; 45 46 key-eeprom-wp { 47 label = "eeprom_wp"; 48 linux,code = <BTN_3>; 49 interrupt-parent = <&gsc>; 50 interrupts = <2>; 51 }; 52 53 key-tamper { 54 label = "tamper"; 55 linux,code = <BTN_4>; 56 interrupt-parent = <&gsc>; 57 interrupts = <5>; 58 }; 59 60 switch-hold { 61 label = "switch_hold"; 62 linux,code = <BTN_5>; 63 interrupt-parent = <&gsc>; 64 interrupts = <7>; 65 }; 66 }; 67}; 68 69&A53_0 { 70 cpu-supply = <&buck3_reg>; 71}; 72 73&A53_1 { 74 cpu-supply = <&buck3_reg>; 75}; 76 77&A53_2 { 78 cpu-supply = <&buck3_reg>; 79}; 80 81&A53_3 { 82 cpu-supply = <&buck3_reg>; 83}; 84 85&eqos { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_eqos>; 88 phy-mode = "rgmii-id"; 89 phy-handle = <ðphy0>; 90 status = "okay"; 91 92 mdio { 93 compatible = "snps,dwmac-mdio"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 ethphy0: ethernet-phy@0 { 98 compatible = "ethernet-phy-ieee802.3-c22"; 99 pinctrl-0 = <&pinctrl_ethphy0>; 100 pinctrl-names = "default"; 101 reg = <0x0>; 102 interrupt-parent = <&gpio3>; 103 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 104 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 105 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 106 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 107 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 108 109 leds { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 113 led@1 { 114 reg = <1>; 115 color = <LED_COLOR_ID_AMBER>; 116 function = LED_FUNCTION_LAN; 117 default-state = "keep"; 118 }; 119 120 led@2 { 121 reg = <2>; 122 color = <LED_COLOR_ID_GREEN>; 123 function = LED_FUNCTION_LAN; 124 default-state = "keep"; 125 }; 126 }; 127 }; 128 }; 129}; 130 131&i2c1 { 132 clock-frequency = <100000>; 133 pinctrl-names = "default", "gpio"; 134 pinctrl-0 = <&pinctrl_i2c1>; 135 pinctrl-1 = <&pinctrl_i2c1_gpio>; 136 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 137 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 138 status = "okay"; 139 140 gsc: gsc@20 { 141 compatible = "gw,gsc"; 142 reg = <0x20>; 143 pinctrl-0 = <&pinctrl_gsc>; 144 interrupt-parent = <&gpio2>; 145 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 146 interrupt-controller; 147 #interrupt-cells = <1>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 adc { 152 compatible = "gw,gsc-adc"; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 channel@6 { 157 gw,mode = <0>; 158 reg = <0x06>; 159 label = "temp"; 160 }; 161 162 channel@8 { 163 gw,mode = <3>; 164 reg = <0x08>; 165 label = "vdd_bat"; 166 }; 167 168 channel@16 { 169 gw,mode = <4>; 170 reg = <0x16>; 171 label = "fan_tach"; 172 }; 173 174 channel@82 { 175 gw,mode = <2>; 176 reg = <0x82>; 177 label = "vdd_vin"; 178 gw,voltage-divider-ohms = <22100 1000>; 179 }; 180 181 channel@84 { 182 gw,mode = <2>; 183 reg = <0x84>; 184 label = "vdd_adc1"; 185 gw,voltage-divider-ohms = <10000 10000>; 186 }; 187 188 channel@86 { 189 gw,mode = <2>; 190 reg = <0x86>; 191 label = "vdd_adc2"; 192 gw,voltage-divider-ohms = <10000 10000>; 193 }; 194 195 channel@88 { 196 gw,mode = <2>; 197 reg = <0x88>; 198 label = "vdd_1p0"; 199 }; 200 201 channel@8c { 202 gw,mode = <2>; 203 reg = <0x8c>; 204 label = "vdd_1p8"; 205 }; 206 207 channel@8e { 208 gw,mode = <2>; 209 reg = <0x8e>; 210 label = "vdd_2p5"; 211 }; 212 213 channel@90 { 214 gw,mode = <2>; 215 reg = <0x90>; 216 label = "vdd_3p3"; 217 gw,voltage-divider-ohms = <10000 10000>; 218 }; 219 220 channel@92 { 221 gw,mode = <2>; 222 reg = <0x92>; 223 label = "vdd_dram"; 224 }; 225 226 channel@98 { 227 gw,mode = <2>; 228 reg = <0x98>; 229 label = "vdd_soc"; 230 }; 231 232 channel@9a { 233 gw,mode = <2>; 234 reg = <0x9a>; 235 label = "vdd_arm"; 236 }; 237 238 channel@a2 { 239 gw,mode = <2>; 240 reg = <0xa2>; 241 label = "vdd_gsc"; 242 gw,voltage-divider-ohms = <10000 10000>; 243 }; 244 }; 245 246 fan-controller@0 { 247 compatible = "gw,gsc-fan"; 248 reg = <0x0a>; 249 }; 250 }; 251 252 gpio: gpio@23 { 253 compatible = "nxp,pca9555"; 254 reg = <0x23>; 255 gpio-controller; 256 #gpio-cells = <2>; 257 interrupt-parent = <&gsc>; 258 interrupts = <4>; 259 }; 260 261 eeprom@50 { 262 compatible = "atmel,24c02"; 263 reg = <0x50>; 264 pagesize = <16>; 265 }; 266 267 eeprom@51 { 268 compatible = "atmel,24c02"; 269 reg = <0x51>; 270 pagesize = <16>; 271 }; 272 273 eeprom@52 { 274 compatible = "atmel,24c02"; 275 reg = <0x52>; 276 pagesize = <16>; 277 }; 278 279 eeprom@53 { 280 compatible = "atmel,24c02"; 281 reg = <0x53>; 282 pagesize = <16>; 283 }; 284 285 gsc_rtc: rtc@68 { 286 compatible = "dallas,ds1672"; 287 reg = <0x68>; 288 }; 289 290 pmic@69 { 291 compatible = "mps,mp5416"; 292 reg = <0x69>; 293 294 regulators { 295 /* vdd_soc */ 296 buck1 { 297 regulator-name = "buck1"; 298 regulator-min-microvolt = <850000>; 299 regulator-max-microvolt = <1000000>; 300 regulator-always-on; 301 regulator-boot-on; 302 }; 303 304 /* vdd_dram */ 305 buck2 { 306 regulator-name = "buck2"; 307 regulator-min-microvolt = <1100000>; 308 regulator-max-microvolt = <1100000>; 309 regulator-always-on; 310 regulator-boot-on; 311 }; 312 313 /* vdd_arm */ 314 buck3_reg: buck3 { 315 regulator-name = "buck3"; 316 regulator-min-microvolt = <850000>; 317 regulator-max-microvolt = <1000000>; 318 regulator-always-on; 319 regulator-boot-on; 320 }; 321 322 /* vdd_1p8 */ 323 buck4 { 324 regulator-name = "buck4"; 325 regulator-min-microvolt = <1800000>; 326 regulator-max-microvolt = <1800000>; 327 regulator-always-on; 328 regulator-boot-on; 329 }; 330 331 /* OUT2: nvcc_snvs_1p8 */ 332 ldo1 { 333 regulator-name = "ldo1"; 334 regulator-min-microvolt = <1800000>; 335 regulator-max-microvolt = <1800000>; 336 regulator-always-on; 337 regulator-boot-on; 338 }; 339 340 /* OUT3: vdd_1p0 */ 341 ldo2 { 342 regulator-name = "ldo2"; 343 regulator-min-microvolt = <1000000>; 344 regulator-max-microvolt = <1000000>; 345 regulator-always-on; 346 regulator-boot-on; 347 }; 348 349 /* OUT4: vdd_2p5 */ 350 ldo3 { 351 regulator-name = "ldo3"; 352 regulator-min-microvolt = <2500000>; 353 regulator-max-microvolt = <2500000>; 354 regulator-always-on; 355 regulator-boot-on; 356 }; 357 358 /* OUT5: vdd_3p3 */ 359 ldo4 { 360 regulator-name = "ldo4"; 361 regulator-min-microvolt = <3300000>; 362 regulator-max-microvolt = <3300000>; 363 regulator-always-on; 364 regulator-boot-on; 365 }; 366 }; 367 }; 368}; 369 370/* off-board header */ 371&i2c2 { 372 clock-frequency = <400000>; 373 pinctrl-names = "default", "gpio"; 374 pinctrl-0 = <&pinctrl_i2c2>; 375 pinctrl-1 = <&pinctrl_i2c2_gpio>; 376 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 377 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 378 status = "okay"; 379 380 eeprom@52 { 381 compatible = "atmel,24c32"; 382 reg = <0x52>; 383 pagesize = <32>; 384 }; 385}; 386 387/* off-board header */ 388&i2c3 { 389 clock-frequency = <400000>; 390 pinctrl-names = "default", "gpio"; 391 pinctrl-0 = <&pinctrl_i2c3>; 392 pinctrl-1 = <&pinctrl_i2c3_gpio>; 393 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 394 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 395 status = "okay"; 396}; 397 398/* off-board header */ 399&uart1 { 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_uart1>; 402 status = "okay"; 403}; 404 405/* console */ 406&uart2 { 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_uart2>; 409 status = "okay"; 410}; 411 412/* off-board header */ 413&uart3 { 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_uart3>; 416 status = "okay"; 417}; 418 419/* off-board */ 420&usdhc1 { 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_usdhc1>; 423 bus-width = <4>; 424 non-removable; 425 status = "okay"; 426 bus-width = <4>; 427 non-removable; 428 status = "okay"; 429}; 430 431/* eMMC */ 432&usdhc3 { 433 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 434 pinctrl-0 = <&pinctrl_usdhc3>; 435 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 436 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 437 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 438 assigned-clock-rates = <400000000>; 439 bus-width = <8>; 440 non-removable; 441 status = "okay"; 442}; 443 444&wdog1 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_wdog>; 447 fsl,ext-reset-output; 448 status = "okay"; 449}; 450 451&iomuxc { 452 pinctrl_eqos: eqosgrp { 453 fsl,pins = < 454 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 455 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 456 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 457 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 458 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 459 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 460 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 461 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 462 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 463 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 464 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 465 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 466 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 467 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 468 >; 469 }; 470 471 pinctrl_ethphy0: ethphy0grp { 472 fsl,pins = < 473 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ 474 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ 475 >; 476 }; 477 478 pinctrl_gsc: gscgrp { 479 fsl,pins = < 480 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ 481 >; 482 }; 483 484 pinctrl_i2c1: i2c1grp { 485 fsl,pins = < 486 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 487 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 488 >; 489 }; 490 491 pinctrl_i2c1_gpio: i2c1gpiogrp { 492 fsl,pins = < 493 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 494 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 495 >; 496 }; 497 498 pinctrl_i2c2: i2c2grp { 499 fsl,pins = < 500 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 501 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 502 >; 503 }; 504 505 pinctrl_i2c2_gpio: i2c2gpiogrp { 506 fsl,pins = < 507 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 508 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 509 >; 510 }; 511 512 pinctrl_i2c3: i2c3grp { 513 fsl,pins = < 514 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 515 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 516 >; 517 }; 518 519 pinctrl_i2c3_gpio: i2c3gpiogrp { 520 fsl,pins = < 521 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 522 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 523 >; 524 }; 525 526 pinctrl_uart1: uart1grp { 527 fsl,pins = < 528 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 529 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 530 >; 531 }; 532 533 pinctrl_uart2: uart2grp { 534 fsl,pins = < 535 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 536 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 537 >; 538 }; 539 540 pinctrl_uart3: uart3grp { 541 fsl,pins = < 542 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 543 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 544 >; 545 }; 546 547 pinctrl_usdhc1: usdhc1grp { 548 fsl,pins = < 549 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 550 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 551 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 552 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 553 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 554 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 555 >; 556 }; 557 558 pinctrl_usdhc3: usdhc3grp { 559 fsl,pins = < 560 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 561 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 562 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 563 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 564 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 565 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 566 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 567 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 568 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 569 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 570 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 571 >; 572 }; 573 574 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 575 fsl,pins = < 576 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 577 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 578 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 579 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 580 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 581 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 582 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 583 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 584 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 585 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 586 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 587 >; 588 }; 589 590 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 591 fsl,pins = < 592 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 593 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 594 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 595 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 596 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 597 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 598 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 599 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 600 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 601 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 602 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 603 >; 604 }; 605 606 pinctrl_wdog: wdoggrp { 607 fsl,pins = < 608 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 609 >; 610 }; 611}; 612