1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8mp.dtsi" 9 10/ { 11 model = "NXP i.MX8MPlus EVK board"; 12 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 13 14 chosen { 15 stdout-path = &uart2; 16 }; 17 18 gpio-leds { 19 compatible = "gpio-leds"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_led>; 22 23 status { 24 label = "yellow:status"; 25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 26 default-state = "on"; 27 }; 28 }; 29 30 memory@40000000 { 31 device_type = "memory"; 32 reg = <0x0 0x40000000 0 0xc0000000>, 33 <0x1 0x00000000 0 0xc0000000>; 34 }; 35 36 reg_can1_stby: regulator-can1-stby { 37 compatible = "regulator-fixed"; 38 regulator-name = "can1-stby"; 39 pinctrl-names = "default"; 40 pinctrl-0 = <&pinctrl_flexcan1_reg>; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46 47 reg_can2_stby: regulator-can2-stby { 48 compatible = "regulator-fixed"; 49 regulator-name = "can2-stby"; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_flexcan2_reg>; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 55 enable-active-high; 56 }; 57 58 reg_usdhc2_vmmc: regulator-usdhc2 { 59 compatible = "regulator-fixed"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 62 regulator-name = "VSD_3V3"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 }; 68}; 69 70&flexcan1 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_flexcan1>; 73 xceiver-supply = <®_can1_stby>; 74 status = "okay"; 75}; 76 77&flexcan2 { 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_flexcan2>; 80 xceiver-supply = <®_can2_stby>; 81 status = "disabled";/* can2 pin conflict with pdm */ 82}; 83 84&eqos { 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_eqos>; 87 phy-mode = "rgmii-id"; 88 phy-handle = <ðphy0>; 89 snps,force_thresh_dma_mode; 90 snps,mtl-tx-config = <&mtl_tx_setup>; 91 snps,mtl-rx-config = <&mtl_rx_setup>; 92 status = "okay"; 93 94 mdio { 95 compatible = "snps,dwmac-mdio"; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 ethphy0: ethernet-phy@1 { 100 compatible = "ethernet-phy-ieee802.3-c22"; 101 reg = <1>; 102 eee-broken-1000t; 103 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 104 reset-assert-us = <10000>; 105 reset-deassert-us = <80000>; 106 realtek,clkout-disable; 107 }; 108 }; 109 110 mtl_tx_setup: tx-queues-config { 111 snps,tx-queues-to-use = <5>; 112 snps,tx-sched-sp; 113 114 queue0 { 115 snps,dcb-algorithm; 116 snps,priority = <0x1>; 117 }; 118 119 queue1 { 120 snps,dcb-algorithm; 121 snps,priority = <0x2>; 122 }; 123 124 queue2 { 125 snps,dcb-algorithm; 126 snps,priority = <0x4>; 127 }; 128 129 queue3 { 130 snps,dcb-algorithm; 131 snps,priority = <0x8>; 132 }; 133 134 queue4 { 135 snps,dcb-algorithm; 136 snps,priority = <0xf0>; 137 }; 138 }; 139 140 mtl_rx_setup: rx-queues-config { 141 snps,rx-queues-to-use = <5>; 142 snps,rx-sched-sp; 143 144 queue0 { 145 snps,dcb-algorithm; 146 snps,priority = <0x1>; 147 snps,map-to-dma-channel = <0>; 148 }; 149 150 queue1 { 151 snps,dcb-algorithm; 152 snps,priority = <0x2>; 153 snps,map-to-dma-channel = <1>; 154 }; 155 156 queue2 { 157 snps,dcb-algorithm; 158 snps,priority = <0x4>; 159 snps,map-to-dma-channel = <2>; 160 }; 161 162 queue3 { 163 snps,dcb-algorithm; 164 snps,priority = <0x8>; 165 snps,map-to-dma-channel = <3>; 166 }; 167 168 queue4 { 169 snps,dcb-algorithm; 170 snps,priority = <0xf0>; 171 snps,map-to-dma-channel = <4>; 172 }; 173 }; 174}; 175 176&fec { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_fec>; 179 phy-mode = "rgmii-id"; 180 phy-handle = <ðphy1>; 181 fsl,magic-packet; 182 status = "okay"; 183 184 mdio { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 ethphy1: ethernet-phy@1 { 189 compatible = "ethernet-phy-ieee802.3-c22"; 190 reg = <1>; 191 eee-broken-1000t; 192 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 193 reset-assert-us = <10000>; 194 reset-deassert-us = <80000>; 195 realtek,clkout-disable; 196 }; 197 }; 198}; 199 200&i2c1 { 201 clock-frequency = <400000>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_i2c1>; 204 status = "okay"; 205 206 pmic@25 { 207 compatible = "nxp,pca9450c"; 208 reg = <0x25>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_pmic>; 211 interrupt-parent = <&gpio1>; 212 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 213 214 regulators { 215 BUCK1 { 216 regulator-name = "BUCK1"; 217 regulator-min-microvolt = <720000>; 218 regulator-max-microvolt = <1000000>; 219 regulator-boot-on; 220 regulator-always-on; 221 regulator-ramp-delay = <3125>; 222 }; 223 224 BUCK2 { 225 regulator-name = "BUCK2"; 226 regulator-min-microvolt = <720000>; 227 regulator-max-microvolt = <1025000>; 228 regulator-boot-on; 229 regulator-always-on; 230 regulator-ramp-delay = <3125>; 231 nxp,dvs-run-voltage = <950000>; 232 nxp,dvs-standby-voltage = <850000>; 233 }; 234 235 BUCK4 { 236 regulator-name = "BUCK4"; 237 regulator-min-microvolt = <3000000>; 238 regulator-max-microvolt = <3600000>; 239 regulator-boot-on; 240 regulator-always-on; 241 }; 242 243 BUCK5 { 244 regulator-name = "BUCK5"; 245 regulator-min-microvolt = <1650000>; 246 regulator-max-microvolt = <1950000>; 247 regulator-boot-on; 248 regulator-always-on; 249 }; 250 251 BUCK6 { 252 regulator-name = "BUCK6"; 253 regulator-min-microvolt = <1045000>; 254 regulator-max-microvolt = <1155000>; 255 regulator-boot-on; 256 regulator-always-on; 257 }; 258 259 LDO1 { 260 regulator-name = "LDO1"; 261 regulator-min-microvolt = <1650000>; 262 regulator-max-microvolt = <1950000>; 263 regulator-boot-on; 264 regulator-always-on; 265 }; 266 267 LDO3 { 268 regulator-name = "LDO3"; 269 regulator-min-microvolt = <1710000>; 270 regulator-max-microvolt = <1890000>; 271 regulator-boot-on; 272 regulator-always-on; 273 }; 274 275 LDO5 { 276 regulator-name = "LDO5"; 277 regulator-min-microvolt = <1800000>; 278 regulator-max-microvolt = <3300000>; 279 regulator-boot-on; 280 regulator-always-on; 281 }; 282 }; 283 }; 284}; 285 286&i2c3 { 287 clock-frequency = <400000>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_i2c3>; 290 status = "okay"; 291 292 pca6416: gpio@20 { 293 compatible = "ti,tca6416"; 294 reg = <0x20>; 295 gpio-controller; 296 #gpio-cells = <2>; 297 }; 298}; 299 300&snvs_pwrkey { 301 status = "okay"; 302}; 303 304&uart2 { 305 /* console */ 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_uart2>; 308 status = "okay"; 309}; 310 311&usb3_phy1 { 312 status = "okay"; 313}; 314 315&usb3_1 { 316 status = "okay"; 317}; 318 319&usb_dwc3_1 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_usb1_vbus>; 322 dr_mode = "host"; 323 status = "okay"; 324}; 325 326&usdhc2 { 327 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 328 assigned-clock-rates = <400000000>; 329 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 330 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 331 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 332 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 333 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 334 vmmc-supply = <®_usdhc2_vmmc>; 335 bus-width = <4>; 336 status = "okay"; 337}; 338 339&usdhc3 { 340 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 341 assigned-clock-rates = <400000000>; 342 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 343 pinctrl-0 = <&pinctrl_usdhc3>; 344 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 345 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 346 bus-width = <8>; 347 non-removable; 348 status = "okay"; 349}; 350 351&wdog1 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_wdog>; 354 fsl,ext-reset-output; 355 status = "okay"; 356}; 357 358&iomuxc { 359 pinctrl_eqos: eqosgrp { 360 fsl,pins = < 361 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 362 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 363 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 364 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 365 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 366 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 367 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 368 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 369 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 370 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 371 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 372 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 373 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 374 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 375 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 376 >; 377 }; 378 379 pinctrl_fec: fecgrp { 380 fsl,pins = < 381 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 382 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 383 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 384 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 385 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 386 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 387 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 388 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 389 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 390 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 391 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 392 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 393 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 394 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 395 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 396 >; 397 }; 398 399 pinctrl_flexcan1: flexcan1grp { 400 fsl,pins = < 401 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 402 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 403 >; 404 }; 405 406 pinctrl_flexcan2: flexcan2grp { 407 fsl,pins = < 408 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 409 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 410 >; 411 }; 412 413 pinctrl_flexcan1_reg: flexcan1reggrp { 414 fsl,pins = < 415 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 416 >; 417 }; 418 419 pinctrl_flexcan2_reg: flexcan2reggrp { 420 fsl,pins = < 421 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 422 >; 423 }; 424 425 pinctrl_gpio_led: gpioledgrp { 426 fsl,pins = < 427 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 428 >; 429 }; 430 431 pinctrl_i2c1: i2c1grp { 432 fsl,pins = < 433 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 434 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 435 >; 436 }; 437 438 pinctrl_i2c3: i2c3grp { 439 fsl,pins = < 440 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 441 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 442 >; 443 }; 444 445 pinctrl_pmic: pmicgrp { 446 fsl,pins = < 447 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 448 >; 449 }; 450 451 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 452 fsl,pins = < 453 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 454 >; 455 }; 456 457 pinctrl_uart2: uart2grp { 458 fsl,pins = < 459 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 460 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 461 >; 462 }; 463 464 pinctrl_usb1_vbus: usb1grp { 465 fsl,pins = < 466 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19 467 >; 468 }; 469 470 pinctrl_usdhc2: usdhc2grp { 471 fsl,pins = < 472 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 473 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 474 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 475 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 476 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 477 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 478 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 479 >; 480 }; 481 482 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 483 fsl,pins = < 484 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 485 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 486 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 487 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 488 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 489 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 490 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 491 >; 492 }; 493 494 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 495 fsl,pins = < 496 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 497 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 498 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 499 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 500 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 501 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 502 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 503 >; 504 }; 505 506 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 507 fsl,pins = < 508 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 509 >; 510 }; 511 512 pinctrl_usdhc3: usdhc3grp { 513 fsl,pins = < 514 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 515 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 516 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 517 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 518 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 519 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 520 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 521 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 522 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 523 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 524 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 525 >; 526 }; 527 528 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 529 fsl,pins = < 530 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 531 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 532 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 533 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 534 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 535 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 536 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 537 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 538 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 539 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 540 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 541 >; 542 }; 543 544 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 545 fsl,pins = < 546 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 547 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 548 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 549 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 550 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 551 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 552 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 553 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 554 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 555 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 556 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 557 >; 558 }; 559 560 pinctrl_wdog: wdoggrp { 561 fsl,pins = < 562 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 563 >; 564 }; 565}; 566