xref: /freebsd/sys/contrib/device-tree/src/arm64/freescale/imx8mp-evk.dts (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "NXP i.MX8MPlus EVK board";
12	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
13
14	chosen {
15		stdout-path = &uart2;
16	};
17
18	gpio-leds {
19		compatible = "gpio-leds";
20		pinctrl-names = "default";
21		pinctrl-0 = <&pinctrl_gpio_led>;
22
23		status {
24			label = "yellow:status";
25			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
26			default-state = "on";
27		};
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0 0xc0000000>,
33		      <0x1 0x00000000 0 0xc0000000>;
34	};
35
36	reg_usdhc2_vmmc: regulator-usdhc2 {
37		compatible = "regulator-fixed";
38		pinctrl-names = "default";
39		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40		regulator-name = "VSD_3V3";
41		regulator-min-microvolt = <3300000>;
42		regulator-max-microvolt = <3300000>;
43		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45	};
46};
47
48&fec {
49	pinctrl-names = "default";
50	pinctrl-0 = <&pinctrl_fec>;
51	phy-mode = "rgmii-id";
52	phy-handle = <&ethphy1>;
53	fsl,magic-packet;
54	status = "okay";
55
56	mdio {
57		#address-cells = <1>;
58		#size-cells = <0>;
59
60		ethphy1: ethernet-phy@1 {
61			compatible = "ethernet-phy-ieee802.3-c22";
62			reg = <1>;
63			eee-broken-1000t;
64			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
65		};
66	};
67};
68
69&i2c3 {
70	clock-frequency = <400000>;
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_i2c3>;
73	status = "okay";
74
75	pca6416: gpio@20 {
76		compatible = "ti,tca6416";
77		reg = <0x20>;
78		gpio-controller;
79		#gpio-cells = <2>;
80	};
81};
82
83&snvs_pwrkey {
84	status = "okay";
85};
86
87&uart2 {
88	/* console */
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_uart2>;
91	status = "okay";
92};
93
94&usdhc2 {
95	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
96	assigned-clock-rates = <400000000>;
97	pinctrl-names = "default", "state_100mhz", "state_200mhz";
98	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
99	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
100	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
101	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
102	vmmc-supply = <&reg_usdhc2_vmmc>;
103	bus-width = <4>;
104	status = "okay";
105};
106
107&usdhc3 {
108	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
109	assigned-clock-rates = <400000000>;
110	pinctrl-names = "default", "state_100mhz", "state_200mhz";
111	pinctrl-0 = <&pinctrl_usdhc3>;
112	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
113	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
114	bus-width = <8>;
115	non-removable;
116	status = "okay";
117};
118
119&wdog1 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_wdog>;
122	fsl,ext-reset-output;
123	status = "okay";
124};
125
126&iomuxc {
127	pinctrl-names = "default";
128
129	pinctrl_fec: fecgrp {
130		fsl,pins = <
131			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
132			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
133			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
134			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
135			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
136			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
137			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
138			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
139			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
140			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
141			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
142			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
143			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
144			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
145			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x19
146		>;
147	};
148
149	pinctrl_gpio_led: gpioledgrp {
150		fsl,pins = <
151			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
152		>;
153	};
154
155	pinctrl_i2c3: i2c3grp {
156		fsl,pins = <
157			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
158			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
159		>;
160	};
161
162	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
163		fsl,pins = <
164			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
165		>;
166	};
167
168	pinctrl_uart2: uart2grp {
169		fsl,pins = <
170			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
171			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
172		>;
173	};
174
175	pinctrl_usdhc2: usdhc2grp {
176		fsl,pins = <
177			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
178			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
179			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
180			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
181			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
182			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
183			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
184		>;
185	};
186
187	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
188		fsl,pins = <
189			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
190			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
191			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
192			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
193			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
194			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
195			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
196		>;
197	};
198
199	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
200		fsl,pins = <
201			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
202			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
203			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
204			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
205			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
206			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
207			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
208		>;
209	};
210
211	pinctrl_usdhc2_gpio: usdhc2grp-gpio {
212		fsl,pins = <
213			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
214		>;
215	};
216
217	pinctrl_usdhc3: usdhc3grp {
218		fsl,pins = <
219			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
220			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
221			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
222			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
223			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
224			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
225			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
226			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
227			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
228			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
229			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
230		>;
231	};
232
233	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
234		fsl,pins = <
235			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
236			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
237			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
238			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
239			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
240			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
241			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
242			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
243			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
244			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
245			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
246		>;
247	};
248
249	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
250		fsl,pins = <
251			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
252			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
253			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
254			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
255			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
256			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
257			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
258			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
259			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
260			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
261			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
262		>;
263	};
264
265	pinctrl_wdog: wdoggrp {
266		fsl,pins = <
267			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
268		>;
269	};
270};
271