1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 hdmi-connector { 20 compatible = "hdmi-connector"; 21 label = "hdmi"; 22 type = "a"; 23 24 port { 25 hdmi_connector_in: endpoint { 26 remote-endpoint = <&adv7533_out>; 27 }; 28 }; 29 }; 30 31 gpio-leds { 32 compatible = "gpio-leds"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_led>; 35 36 status { 37 label = "yellow:status"; 38 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 39 default-state = "on"; 40 }; 41 }; 42 43 memory@40000000 { 44 device_type = "memory"; 45 reg = <0x0 0x40000000 0 0xc0000000>, 46 <0x1 0x00000000 0 0xc0000000>; 47 }; 48 49 pcie0_refclk: pcie0-refclk { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <100000000>; 53 }; 54 55 reg_audio_pwr: regulator-audio-pwr { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 59 regulator-name = "audio-pwr"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 reg_can1_stby: regulator-can1-stby { 67 compatible = "regulator-fixed"; 68 regulator-name = "can1-stby"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_flexcan1_reg>; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 74 enable-active-high; 75 }; 76 77 reg_can2_stby: regulator-can2-stby { 78 compatible = "regulator-fixed"; 79 regulator-name = "can2-stby"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_flexcan2_reg>; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 }; 87 88 reg_pcie0: regulator-pcie { 89 compatible = "regulator-fixed"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_pcie0_reg>; 92 regulator-name = "MPCIE_3V3"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 }; 98 99 reg_usdhc2_vmmc: regulator-usdhc2 { 100 compatible = "regulator-fixed"; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 103 regulator-name = "VSD_3V3"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 sound { 111 compatible = "simple-audio-card"; 112 simple-audio-card,name = "wm8960-audio"; 113 simple-audio-card,format = "i2s"; 114 simple-audio-card,frame-master = <&cpudai>; 115 simple-audio-card,bitclock-master = <&cpudai>; 116 simple-audio-card,widgets = 117 "Headphone", "Headphone Jack", 118 "Speaker", "External Speaker", 119 "Microphone", "Mic Jack"; 120 simple-audio-card,routing = 121 "Headphone Jack", "HP_L", 122 "Headphone Jack", "HP_R", 123 "External Speaker", "SPK_LP", 124 "External Speaker", "SPK_LN", 125 "External Speaker", "SPK_RP", 126 "External Speaker", "SPK_RN", 127 "LINPUT1", "Mic Jack", 128 "LINPUT3", "Mic Jack", 129 "Mic Jack", "MICB"; 130 131 cpudai: simple-audio-card,cpu { 132 sound-dai = <&sai3>; 133 }; 134 135 simple-audio-card,codec { 136 sound-dai = <&wm8960>; 137 }; 138 139 }; 140 141 reserved-memory { 142 #address-cells = <2>; 143 #size-cells = <2>; 144 ranges; 145 146 dsp_vdev0vring0: vdev0vring0@942f0000 { 147 reg = <0 0x942f0000 0 0x8000>; 148 no-map; 149 }; 150 151 dsp_vdev0vring1: vdev0vring1@942f8000 { 152 reg = <0 0x942f8000 0 0x8000>; 153 no-map; 154 }; 155 156 dsp_vdev0buffer: vdev0buffer@94300000 { 157 compatible = "shared-dma-pool"; 158 reg = <0 0x94300000 0 0x100000>; 159 no-map; 160 }; 161 }; 162}; 163 164&flexspi { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_flexspi0>; 167 status = "okay"; 168 169 flash@0 { 170 compatible = "jedec,spi-nor"; 171 reg = <0>; 172 spi-max-frequency = <80000000>; 173 spi-tx-bus-width = <1>; 174 spi-rx-bus-width = <4>; 175 }; 176}; 177 178&A53_0 { 179 cpu-supply = <®_arm>; 180}; 181 182&A53_1 { 183 cpu-supply = <®_arm>; 184}; 185 186&A53_2 { 187 cpu-supply = <®_arm>; 188}; 189 190&A53_3 { 191 cpu-supply = <®_arm>; 192}; 193 194&eqos { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_eqos>; 197 phy-mode = "rgmii-id"; 198 phy-handle = <ðphy0>; 199 snps,force_thresh_dma_mode; 200 snps,mtl-tx-config = <&mtl_tx_setup>; 201 snps,mtl-rx-config = <&mtl_rx_setup>; 202 status = "okay"; 203 204 mdio { 205 compatible = "snps,dwmac-mdio"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 209 ethphy0: ethernet-phy@1 { 210 compatible = "ethernet-phy-ieee802.3-c22"; 211 reg = <1>; 212 eee-broken-1000t; 213 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 214 reset-assert-us = <10000>; 215 reset-deassert-us = <80000>; 216 realtek,clkout-disable; 217 }; 218 }; 219 220 mtl_tx_setup: tx-queues-config { 221 snps,tx-queues-to-use = <5>; 222 snps,tx-sched-sp; 223 224 queue0 { 225 snps,dcb-algorithm; 226 snps,priority = <0x1>; 227 }; 228 229 queue1 { 230 snps,dcb-algorithm; 231 snps,priority = <0x2>; 232 }; 233 234 queue2 { 235 snps,dcb-algorithm; 236 snps,priority = <0x4>; 237 }; 238 239 queue3 { 240 snps,dcb-algorithm; 241 snps,priority = <0x8>; 242 }; 243 244 queue4 { 245 snps,dcb-algorithm; 246 snps,priority = <0xf0>; 247 }; 248 }; 249 250 mtl_rx_setup: rx-queues-config { 251 snps,rx-queues-to-use = <5>; 252 snps,rx-sched-sp; 253 254 queue0 { 255 snps,dcb-algorithm; 256 snps,priority = <0x1>; 257 snps,map-to-dma-channel = <0>; 258 }; 259 260 queue1 { 261 snps,dcb-algorithm; 262 snps,priority = <0x2>; 263 snps,map-to-dma-channel = <1>; 264 }; 265 266 queue2 { 267 snps,dcb-algorithm; 268 snps,priority = <0x4>; 269 snps,map-to-dma-channel = <2>; 270 }; 271 272 queue3 { 273 snps,dcb-algorithm; 274 snps,priority = <0x8>; 275 snps,map-to-dma-channel = <3>; 276 }; 277 278 queue4 { 279 snps,dcb-algorithm; 280 snps,priority = <0xf0>; 281 snps,map-to-dma-channel = <4>; 282 }; 283 }; 284}; 285 286&fec { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_fec>; 289 phy-mode = "rgmii-id"; 290 phy-handle = <ðphy1>; 291 fsl,magic-packet; 292 status = "okay"; 293 294 mdio { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 298 ethphy1: ethernet-phy@1 { 299 compatible = "ethernet-phy-ieee802.3-c22"; 300 reg = <1>; 301 eee-broken-1000t; 302 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 303 reset-assert-us = <10000>; 304 reset-deassert-us = <80000>; 305 realtek,clkout-disable; 306 }; 307 }; 308}; 309 310&flexcan1 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_flexcan1>; 313 xceiver-supply = <®_can1_stby>; 314 status = "okay"; 315}; 316 317&flexcan2 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_flexcan2>; 320 xceiver-supply = <®_can2_stby>; 321 status = "disabled";/* can2 pin conflict with pdm */ 322}; 323 324&i2c1 { 325 clock-frequency = <400000>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_i2c1>; 328 status = "okay"; 329 330 pmic@25 { 331 compatible = "nxp,pca9450c"; 332 reg = <0x25>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_pmic>; 335 interrupt-parent = <&gpio1>; 336 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 337 338 regulators { 339 BUCK1 { 340 regulator-name = "BUCK1"; 341 regulator-min-microvolt = <720000>; 342 regulator-max-microvolt = <1000000>; 343 regulator-boot-on; 344 regulator-always-on; 345 regulator-ramp-delay = <3125>; 346 }; 347 348 reg_arm: BUCK2 { 349 regulator-name = "BUCK2"; 350 regulator-min-microvolt = <720000>; 351 regulator-max-microvolt = <1025000>; 352 regulator-boot-on; 353 regulator-always-on; 354 regulator-ramp-delay = <3125>; 355 nxp,dvs-run-voltage = <950000>; 356 nxp,dvs-standby-voltage = <850000>; 357 }; 358 359 BUCK4 { 360 regulator-name = "BUCK4"; 361 regulator-min-microvolt = <3000000>; 362 regulator-max-microvolt = <3600000>; 363 regulator-boot-on; 364 regulator-always-on; 365 }; 366 367 BUCK5 { 368 regulator-name = "BUCK5"; 369 regulator-min-microvolt = <1650000>; 370 regulator-max-microvolt = <1950000>; 371 regulator-boot-on; 372 regulator-always-on; 373 }; 374 375 BUCK6 { 376 regulator-name = "BUCK6"; 377 regulator-min-microvolt = <1045000>; 378 regulator-max-microvolt = <1155000>; 379 regulator-boot-on; 380 regulator-always-on; 381 }; 382 383 LDO1 { 384 regulator-name = "LDO1"; 385 regulator-min-microvolt = <1650000>; 386 regulator-max-microvolt = <1950000>; 387 regulator-boot-on; 388 regulator-always-on; 389 }; 390 391 LDO3 { 392 regulator-name = "LDO3"; 393 regulator-min-microvolt = <1710000>; 394 regulator-max-microvolt = <1890000>; 395 regulator-boot-on; 396 regulator-always-on; 397 }; 398 399 LDO5 { 400 regulator-name = "LDO5"; 401 regulator-min-microvolt = <1800000>; 402 regulator-max-microvolt = <3300000>; 403 regulator-boot-on; 404 regulator-always-on; 405 }; 406 }; 407 }; 408}; 409 410&i2c2 { 411 clock-frequency = <400000>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_i2c2>; 414 status = "okay"; 415 416 hdmi@3d { 417 compatible = "adi,adv7535"; 418 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 419 reg-names = "main", "cec", "edid", "packet"; 420 adi,dsi-lanes = <4>; 421 adi,input-depth = <8>; 422 adi,input-colorspace = "rgb"; 423 adi,input-clock = "1x"; 424 adi,input-style = <1>; 425 adi,input-justification = "evenly"; 426 427 ports { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 port@0 { 432 reg = <0>; 433 434 adv7533_in: endpoint { 435 remote-endpoint = <&dsi_out>; 436 }; 437 }; 438 439 port@1 { 440 reg = <1>; 441 442 adv7533_out: endpoint { 443 remote-endpoint = <&hdmi_connector_in>; 444 }; 445 }; 446 447 }; 448 }; 449}; 450 451&i2c3 { 452 clock-frequency = <400000>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_i2c3>; 455 status = "okay"; 456 457 wm8960: codec@1a { 458 compatible = "wlf,wm8960"; 459 reg = <0x1a>; 460 #sound-dai-cells = <0>; 461 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 462 clock-names = "mclk"; 463 wlf,shared-lrclk; 464 wlf,hp-cfg = <3 2 3>; 465 wlf,gpio-cfg = <1 3>; 466 SPKVDD1-supply = <®_audio_pwr>; 467 }; 468 469 pca6416: gpio@20 { 470 compatible = "ti,tca6416"; 471 reg = <0x20>; 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_pca6416_int>; 478 interrupt-parent = <&gpio1>; 479 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 480 gpio-line-names = "EXT_PWREN1", 481 "EXT_PWREN2", 482 "CAN1/I2C5_SEL", 483 "PDM/CAN2_SEL", 484 "FAN_EN", 485 "PWR_MEAS_IO1", 486 "PWR_MEAS_IO2", 487 "EXP_P0_7", 488 "EXP_P1_0", 489 "EXP_P1_1", 490 "EXP_P1_2", 491 "EXP_P1_3", 492 "EXP_P1_4", 493 "EXP_P1_5", 494 "EXP_P1_6", 495 "EXP_P1_7"; 496 }; 497}; 498 499/* I2C on expansion connector J22. */ 500&i2c5 { 501 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_i2c5>; 504 status = "disabled"; /* can1 pins conflict with i2c5 */ 505 506 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 507 * LOW: CAN1 (default, pull-down) 508 * HIGH: I2C5 509 * You need to set it to high to enable I2C5 (for example, add gpio-hog 510 * in pca6416 node). 511 */ 512}; 513 514&lcdif1 { 515 status = "okay"; 516}; 517 518&mipi_dsi { 519 samsung,esc-clock-frequency = <10000000>; 520 status = "okay"; 521 522 ports { 523 port@1 { 524 reg = <1>; 525 526 dsi_out: endpoint { 527 remote-endpoint = <&adv7533_in>; 528 data-lanes = <1 2 3 4>; 529 }; 530 }; 531 }; 532}; 533 534&pcie_phy { 535 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 536 clocks = <&pcie0_refclk>; 537 clock-names = "ref"; 538 status = "okay"; 539}; 540 541&pcie { 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_pcie0>; 544 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 545 vpcie-supply = <®_pcie0>; 546 status = "okay"; 547}; 548 549&pwm1 { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_pwm1>; 552 status = "okay"; 553}; 554 555&pwm2 { 556 pinctrl-names = "default"; 557 pinctrl-0 = <&pinctrl_pwm2>; 558 status = "okay"; 559}; 560 561&pwm4 { 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_pwm4>; 564 status = "okay"; 565}; 566 567&sai3 { 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_sai3>; 570 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 571 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 572 assigned-clock-rates = <12288000>; 573 fsl,sai-mclk-direction-output; 574 status = "okay"; 575}; 576 577&snvs_pwrkey { 578 status = "okay"; 579}; 580 581&uart1 { /* BT */ 582 pinctrl-names = "default"; 583 pinctrl-0 = <&pinctrl_uart1>; 584 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 585 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 586 uart-has-rtscts; 587 status = "okay"; 588}; 589 590&uart2 { 591 /* console */ 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_uart2>; 594 status = "okay"; 595}; 596 597&usb3_phy1 { 598 status = "okay"; 599}; 600 601&usb3_1 { 602 status = "okay"; 603}; 604 605&usb_dwc3_1 { 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_usb1_vbus>; 608 dr_mode = "host"; 609 status = "okay"; 610}; 611 612&uart3 { 613 pinctrl-names = "default"; 614 pinctrl-0 = <&pinctrl_uart3>; 615 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 616 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 617 uart-has-rtscts; 618 status = "okay"; 619}; 620 621&usdhc2 { 622 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 623 assigned-clock-rates = <400000000>; 624 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 625 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 626 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 627 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 628 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 629 vmmc-supply = <®_usdhc2_vmmc>; 630 bus-width = <4>; 631 status = "okay"; 632}; 633 634&usdhc3 { 635 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 636 assigned-clock-rates = <400000000>; 637 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 638 pinctrl-0 = <&pinctrl_usdhc3>; 639 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 640 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 641 bus-width = <8>; 642 non-removable; 643 status = "okay"; 644}; 645 646&wdog1 { 647 pinctrl-names = "default"; 648 pinctrl-0 = <&pinctrl_wdog>; 649 fsl,ext-reset-output; 650 status = "okay"; 651}; 652 653&iomuxc { 654 pinctrl_audio_pwr_reg: audiopwrreggrp { 655 fsl,pins = < 656 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 657 >; 658 }; 659 660 pinctrl_eqos: eqosgrp { 661 fsl,pins = < 662 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 663 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 664 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 665 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 666 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 667 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 668 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 669 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 670 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 671 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 672 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 673 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 674 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 675 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 676 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 677 >; 678 }; 679 680 pinctrl_fec: fecgrp { 681 fsl,pins = < 682 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 683 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 684 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 685 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 686 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 687 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 688 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 689 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 690 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 691 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 692 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 693 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 694 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 695 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 696 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 697 >; 698 }; 699 700 pinctrl_flexcan1: flexcan1grp { 701 fsl,pins = < 702 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 703 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 704 >; 705 }; 706 707 pinctrl_flexcan2: flexcan2grp { 708 fsl,pins = < 709 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 710 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 711 >; 712 }; 713 714 pinctrl_flexcan1_reg: flexcan1reggrp { 715 fsl,pins = < 716 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 717 >; 718 }; 719 720 pinctrl_flexcan2_reg: flexcan2reggrp { 721 fsl,pins = < 722 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 723 >; 724 }; 725 726 pinctrl_flexspi0: flexspi0grp { 727 fsl,pins = < 728 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 729 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 730 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 731 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 732 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 733 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 734 >; 735 }; 736 737 pinctrl_gpio_led: gpioledgrp { 738 fsl,pins = < 739 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 740 >; 741 }; 742 743 pinctrl_i2c1: i2c1grp { 744 fsl,pins = < 745 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 746 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 747 >; 748 }; 749 750 pinctrl_i2c2: i2c2grp { 751 fsl,pins = < 752 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 753 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 754 >; 755 }; 756 757 pinctrl_i2c3: i2c3grp { 758 fsl,pins = < 759 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 760 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 761 >; 762 }; 763 764 pinctrl_i2c5: i2c5grp { 765 fsl,pins = < 766 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 767 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 768 >; 769 }; 770 771 pinctrl_pcie0: pcie0grp { 772 fsl,pins = < 773 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 774 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 775 >; 776 }; 777 778 pinctrl_pcie0_reg: pcie0reggrp { 779 fsl,pins = < 780 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 781 >; 782 }; 783 784 pinctrl_pmic: pmicgrp { 785 fsl,pins = < 786 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 787 >; 788 }; 789 790 pinctrl_pca6416_int: pca6416_int_grp { 791 fsl,pins = < 792 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 793 >; 794 }; 795 796 pinctrl_pwm1: pwm1grp { 797 fsl,pins = < 798 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 799 >; 800 }; 801 802 pinctrl_pwm2: pwm2grp { 803 fsl,pins = < 804 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 805 >; 806 }; 807 808 pinctrl_pwm4: pwm4grp { 809 fsl,pins = < 810 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 811 >; 812 }; 813 814 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 815 fsl,pins = < 816 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 817 >; 818 }; 819 820 pinctrl_uart1: uart1grp { 821 fsl,pins = < 822 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 823 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 824 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 825 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 826 >; 827 }; 828 829 pinctrl_sai3: sai3grp { 830 fsl,pins = < 831 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 832 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 833 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 834 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 835 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 836 >; 837 }; 838 839 pinctrl_uart2: uart2grp { 840 fsl,pins = < 841 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 842 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 843 >; 844 }; 845 846 pinctrl_usb1_vbus: usb1grp { 847 fsl,pins = < 848 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 849 >; 850 }; 851 852 pinctrl_uart3: uart3grp { 853 fsl,pins = < 854 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 855 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 856 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 857 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 858 >; 859 }; 860 861 pinctrl_usdhc2: usdhc2grp { 862 fsl,pins = < 863 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 864 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 865 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 866 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 867 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 868 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 869 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 870 >; 871 }; 872 873 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 874 fsl,pins = < 875 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 876 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 877 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 878 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 879 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 880 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 881 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 882 >; 883 }; 884 885 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 886 fsl,pins = < 887 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 888 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 889 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 890 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 891 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 892 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 893 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 894 >; 895 }; 896 897 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 898 fsl,pins = < 899 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 900 >; 901 }; 902 903 pinctrl_usdhc3: usdhc3grp { 904 fsl,pins = < 905 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 906 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 907 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 908 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 909 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 910 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 911 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 912 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 913 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 914 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 915 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 916 >; 917 }; 918 919 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 920 fsl,pins = < 921 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 922 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 923 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 924 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 925 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 926 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 927 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 928 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 929 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 930 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 931 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 932 >; 933 }; 934 935 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 936 fsl,pins = < 937 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 938 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 939 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 940 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 941 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 942 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 943 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 944 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 945 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 946 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 947 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 948 >; 949 }; 950 951 pinctrl_wdog: wdoggrp { 952 fsl,pins = < 953 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 954 >; 955 }; 956}; 957