1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> 4 */ 5 6#include "imx8mp.dtsi" 7 8/ { 9 model = "DH electronics i.MX8M Plus DHCOM SoM"; 10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; 11 12 aliases { 13 ethernet0 = &eqos; 14 ethernet1 = &fec; 15 rtc0 = &rv3032; 16 rtc1 = &snvs_rtc; 17 spi0 = &flexspi; 18 }; 19 20 memory@40000000 { 21 device_type = "memory"; 22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ 23 reg = <0x0 0x40000000 0 0x08000000>; 24 }; 25 26 reg_eth_vio: regulator-eth-vio { 27 compatible = "regulator-fixed"; 28 gpio = <&ioexp 2 GPIO_ACTIVE_LOW>; 29 regulator-always-on; 30 regulator-boot-on; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 regulator-name = "eth_vio"; 34 vin-supply = <&buck4>; 35 }; 36 37 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 38 compatible = "regulator-fixed"; 39 enable-active-high; 40 gpio = <&gpio2 19 0>; /* SD2_RESET */ 41 off-on-delay-us = <12000>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 44 regulator-max-microvolt = <3300000>; 45 regulator-min-microvolt = <3300000>; 46 regulator-name = "VDD_3V3_SD"; 47 startup-delay-us = <100>; 48 vin-supply = <&buck4>; 49 }; 50 51 reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */ 52 compatible = "regulator-fixed"; 53 regulator-always-on; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 regulator-name = "VDD_3P3V_AWO"; 57 }; 58 59 wlan_pwrseq: wifi-pwrseq { 60 compatible = "mmc-pwrseq-simple"; 61 reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>; 62 }; 63}; 64 65&A53_0 { 66 cpu-supply = <&buck2>; 67}; 68 69&A53_1 { 70 cpu-supply = <&buck2>; 71}; 72 73&A53_2 { 74 cpu-supply = <&buck2>; 75}; 76 77&A53_3 { 78 cpu-supply = <&buck2>; 79}; 80 81&ecspi1 { 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_ecspi1>; 84 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 85 status = "disabled"; 86}; 87 88&ecspi2 { 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_ecspi2>; 91 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 92 status = "disabled"; 93}; 94 95&eqos { /* First ethernet */ 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_eqos_rgmii>; 98 phy-handle = <ðphy0g>; 99 phy-mode = "rgmii-id"; 100 status = "okay"; 101 102 mdio { 103 compatible = "snps,dwmac-mdio"; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 107 /* Up to one of these two PHYs may be populated. */ 108 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */ 109 compatible = "ethernet-phy-id0007.c110", 110 "ethernet-phy-ieee802.3-c22"; 111 interrupt-parent = <&gpio3>; 112 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 113 pinctrl-0 = <&pinctrl_ethphy0>; 114 pinctrl-names = "default"; 115 reg = <0>; 116 reset-assert-us = <1000>; 117 reset-deassert-us = <1000>; 118 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; 119 /* Non-default PHY population option. */ 120 status = "disabled"; 121 }; 122 123 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ 124 compatible = "ethernet-phy-id0022.1642", 125 "ethernet-phy-ieee802.3-c22"; 126 interrupt-parent = <&gpio3>; 127 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 128 micrel,led-mode = <0>; 129 pinctrl-0 = <&pinctrl_ethphy0>; 130 pinctrl-names = "default"; 131 reg = <5>; 132 reset-assert-us = <1000>; 133 reset-deassert-us = <1000>; 134 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; 135 /* Default PHY population option. */ 136 status = "okay"; 137 }; 138 }; 139}; 140 141&fec { /* Second ethernet */ 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_fec_rmii>; 144 phy-handle = <ðphy1f>; 145 phy-mode = "rmii"; 146 fsl,magic-packet; 147 status = "okay"; 148 149 mdio { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 /* Up to one PHY may be populated. */ 154 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 155 compatible = "ethernet-phy-id0007.c110", 156 "ethernet-phy-ieee802.3-c22"; 157 interrupt-parent = <&gpio4>; 158 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 159 pinctrl-0 = <&pinctrl_ethphy1>; 160 pinctrl-names = "default"; 161 reg = <1>; 162 reset-assert-us = <1000>; 163 reset-deassert-us = <1000>; 164 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 165 /* Non-default PHY population option. */ 166 status = "disabled"; 167 }; 168 }; 169}; 170 171&flexcan1 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_flexcan1>; 174 status = "disabled"; 175}; 176 177&flexcan2 { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_flexcan2>; 180 status = "disabled"; 181}; 182 183&flexspi { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_flexspi>; 186 status = "okay"; 187 188 flash@0 { /* W25Q128JWPIM */ 189 compatible = "jedec,spi-nor"; 190 reg = <0>; 191 spi-max-frequency = <80000000>; 192 spi-tx-bus-width = <4>; 193 spi-rx-bus-width = <4>; 194 }; 195}; 196 197&gpio1 { 198 gpio-line-names = 199 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", 200 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", 201 "", "", "", "", "", "", "", "", 202 "", "", "", "", "", "", "", ""; 203}; 204 205&gpio2 { 206 gpio-line-names = 207 "", "", "", "", "", "", "", "", 208 "", "", "", "DHCOM-K", "", "", "", "", 209 "", "", "", "", "DHCOM-INT", "", "", "", 210 "", "", "", "", "", "", "", ""; 211}; 212 213&gpio3 { 214 gpio-line-names = 215 "", "", "", "", "", "", "", "", 216 "", "", "", "", "", "", "SOM-HW0", "", 217 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", 218 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; 219}; 220 221&gpio4 { 222 gpio-line-names = 223 "", "", "", "", "", "", "", "", 224 "", "", "", "", "", "", "", "", 225 "", "", "", "SOM-HW1", "", "", "", "", 226 "", "", "", "DHCOM-D", "", "", "", ""; 227}; 228 229&gpio5 { 230 gpio-line-names = 231 "", "", "DHCOM-C", "", "", "", "", "", 232 "", "", "", "", "", "", "", "", 233 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", 234 "", "", "", "", "", "", "", ""; 235}; 236 237&i2c3 { 238 clock-frequency = <100000>; 239 pinctrl-names = "default", "gpio"; 240 pinctrl-0 = <&pinctrl_i2c3>; 241 pinctrl-1 = <&pinctrl_i2c3_gpio>; 242 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 243 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 244 status = "okay"; 245 246 tc_bridge: bridge@f { 247 compatible = "toshiba,tc9595", "toshiba,tc358767"; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_tc9595>; 250 reg = <0xf>; 251 clock-names = "ref"; 252 clocks = <&clk IMX8MP_CLK_CLKOUT2>; 253 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>, 254 <&clk IMX8MP_CLK_CLKOUT2>, 255 <&clk IMX8MP_AUDIO_PLL2_OUT>; 256 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; 257 assigned-clock-rates = <13000000>, <13000000>, <156000000>; 258 reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 259 status = "disabled"; 260 261 ports { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 port@0 { 266 reg = <0>; 267 268 tc_bridge_in: endpoint { 269 data-lanes = <1 2 3 4>; 270 remote-endpoint = <&dsi_out>; 271 }; 272 }; 273 }; 274 }; 275 276 pmic: pmic@25 { 277 compatible = "nxp,pca9450c"; 278 reg = <0x25>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_pmic>; 281 interrupt-parent = <&gpio1>; 282 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 283 284 /* 285 * i.MX 8M Plus Data Sheet for Consumer Products 286 * 3.1.4 Operating ranges 287 * MIMX8ML8CVNKZAB 288 */ 289 regulators { 290 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 291 regulator-min-microvolt = <850000>; 292 regulator-max-microvolt = <1000000>; 293 regulator-ramp-delay = <3125>; 294 regulator-always-on; 295 regulator-boot-on; 296 }; 297 298 buck2: BUCK2 { /* VDD_ARM */ 299 nxp,dvs-run-voltage = <950000>; 300 nxp,dvs-standby-voltage = <850000>; 301 regulator-min-microvolt = <850000>; 302 regulator-max-microvolt = <1000000>; 303 regulator-ramp-delay = <3125>; 304 regulator-always-on; 305 regulator-boot-on; 306 }; 307 308 buck4: BUCK4 { /* VDD_3V3 */ 309 regulator-min-microvolt = <3300000>; 310 regulator-max-microvolt = <3300000>; 311 regulator-always-on; 312 regulator-boot-on; 313 }; 314 315 buck5: BUCK5 { /* VDD_1V8 */ 316 regulator-min-microvolt = <1800000>; 317 regulator-max-microvolt = <1800000>; 318 regulator-always-on; 319 regulator-boot-on; 320 }; 321 322 buck6: BUCK6 { /* NVCC_DRAM_1V1 */ 323 regulator-min-microvolt = <1100000>; 324 regulator-max-microvolt = <1100000>; 325 regulator-always-on; 326 regulator-boot-on; 327 }; 328 329 ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 330 regulator-min-microvolt = <1800000>; 331 regulator-max-microvolt = <1800000>; 332 regulator-always-on; 333 regulator-boot-on; 334 }; 335 336 ldo3: LDO3 { /* VDDA_1V8 */ 337 regulator-min-microvolt = <1800000>; 338 regulator-max-microvolt = <1800000>; 339 regulator-always-on; 340 regulator-boot-on; 341 }; 342 343 ldo4: LDO4 { /* PMIC_LDO4 */ 344 regulator-min-microvolt = <3300000>; 345 regulator-max-microvolt = <3300000>; 346 }; 347 348 ldo5: LDO5 { /* NVCC_SD2 */ 349 regulator-min-microvolt = <1800000>; 350 regulator-max-microvolt = <3300000>; 351 }; 352 }; 353 }; 354 355 adc@48 { 356 compatible = "ti,ads1015"; 357 reg = <0x48>; 358 interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 362 channel@0 { /* Voltage over AIN0 and AIN1. */ 363 reg = <0>; 364 }; 365 366 channel@1 { /* Voltage over AIN0 and AIN3. */ 367 reg = <1>; 368 }; 369 370 channel@2 { /* Voltage over AIN1 and AIN3. */ 371 reg = <2>; 372 }; 373 374 channel@3 { /* Voltage over AIN2 and AIN3. */ 375 reg = <3>; 376 }; 377 378 channel@4 { /* Voltage over AIN0 and GND. */ 379 reg = <4>; 380 }; 381 382 channel@5 { /* Voltage over AIN1 and GND. */ 383 reg = <5>; 384 }; 385 386 channel@6 { /* Voltage over AIN2 and GND. */ 387 reg = <6>; 388 }; 389 390 channel@7 { /* Voltage over AIN3 and GND. */ 391 reg = <7>; 392 }; 393 }; 394 395 touchscreen@49 { 396 compatible = "ti,tsc2004"; 397 reg = <0x49>; 398 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_touch>; 401 vio-supply = <&buck4>; 402 }; 403 404 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ 405 compatible = "atmel,24c32"; /* M24C32-D */ 406 pagesize = <32>; 407 reg = <0x50>; 408 }; 409 410 rv3032: rtc@51 { 411 compatible = "microcrystal,rv3032"; 412 reg = <0x51>; 413 interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>; 414 wakeup-source; 415 }; 416 417 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ 418 compatible = "atmel,24c32"; /* M24C32-D */ 419 pagesize = <32>; 420 reg = <0x53>; 421 }; 422 423 eeprom0wl: eeprom@58 { 424 compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */ 425 pagesize = <32>; 426 reg = <0x58>; 427 }; 428 429 eeprom1wl: eeprom@5b { 430 compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */ 431 pagesize = <32>; 432 reg = <0x5b>; 433 }; 434 435 ioexp: gpio@74 { 436 compatible = "nxp,pca9539"; 437 reg = <0x74>; 438 gpio-controller; 439 #gpio-cells = <2>; 440 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_ioexp>; 445 wakeup-source; 446 447 gpio-line-names = 448 "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT", 449 "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY", 450 "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", 451 "BT_HOST_WAKE", "BT_DEV_WAKE", "", ""; 452 }; 453}; 454 455&i2c4 { 456 clock-frequency = <100000>; 457 pinctrl-names = "default", "gpio"; 458 pinctrl-0 = <&pinctrl_i2c4>; 459 pinctrl-1 = <&pinctrl_i2c4_gpio>; 460 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 461 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 462 status = "okay"; 463}; 464 465&i2c5 { /* HDMI EDID bus */ 466 clock-frequency = <100000>; 467 pinctrl-names = "default", "gpio"; 468 pinctrl-0 = <&pinctrl_i2c5>; 469 pinctrl-1 = <&pinctrl_i2c5_gpio>; 470 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 471 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 472 status = "okay"; 473}; 474 475&mipi_dsi { 476 samsung,burst-clock-frequency = <160000000>; 477 samsung,esc-clock-frequency = <10000000>; 478 479 ports { 480 port@1 { 481 reg = <1>; 482 483 dsi_out: endpoint { 484 data-lanes = <1 2 3 4>; 485 remote-endpoint = <&tc_bridge_in>; 486 }; 487 }; 488 }; 489}; 490 491&pwm1 { 492 pinctrl-0 = <&pinctrl_pwm1>; 493 pinctrl-names = "default"; 494 status = "disabled"; 495}; 496 497&uart1 { 498 /* CA53 console */ 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pinctrl_uart1>; 501 status = "okay"; 502 wakeup-source; 503}; 504 505&uart2 { 506 /* Bluetooth */ 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_uart2>; 509 uart-has-rtscts; 510 status = "okay"; 511 512 /* 513 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock, 514 * which with 16x oversampling yields 5 Mbdps baud base, 515 * which can be well divided by 5/4 to achieve 4 Mbdps, 516 * which is exactly the maximum rate supported by muRata 517 * 2AE bluetooth UART. 518 */ 519 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 520 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 521 assigned-clock-rates = <80000000>; 522 523 bluetooth { 524 compatible = "cypress,cyw4373a0-bt"; 525 shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>; 526 max-speed = <4000000>; 527 }; 528}; 529 530&uart3 { 531 pinctrl-names = "default"; 532 pinctrl-0 = <&pinctrl_uart3>; 533 uart-has-rtscts; 534 status = "okay"; 535}; 536 537&uart4 { 538 pinctrl-names = "default"; 539 pinctrl-0 = <&pinctrl_uart4>; 540 status = "okay"; 541}; 542 543&usb3_phy0 { 544 status = "okay"; 545}; 546 547&usb3_0 { 548 status = "okay"; 549}; 550 551&usb_dwc3_0 { 552 dr_mode = "otg"; 553 status = "okay"; 554}; 555 556&usb3_phy1 { 557 status = "okay"; 558}; 559 560&usb3_1 { 561 status = "okay"; 562}; 563 564&usb_dwc3_1 { 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_usb1_vbus>; 567 dr_mode = "host"; 568 status = "okay"; 569}; 570 571/* SDIO WiFi */ 572&usdhc1 { 573 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 574 pinctrl-0 = <&pinctrl_usdhc1>; 575 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 576 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 577 mmc-pwrseq = <&wlan_pwrseq>; 578 vmmc-supply = <&buck4>; 579 bus-width = <4>; 580 non-removable; 581 cap-power-off-card; 582 keep-power-in-suspend; 583 status = "okay"; 584 585 #address-cells = <1>; 586 #size-cells = <0>; 587 588 brcmf: bcrmf@1 { /* muRata 2AE */ 589 reg = <1>; 590 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 591 /* 592 * The "host-wake" interrupt output is by default not 593 * connected to the SoC, but can be connected on to 594 * SoC pin on the carrier board. 595 */ 596 }; 597}; 598 599/* SD slot */ 600&usdhc2 { 601 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 602 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 603 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 604 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 605 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 606 vmmc-supply = <®_usdhc2_vmmc>; 607 bus-width = <4>; 608 status = "okay"; 609}; 610 611/* eMMC */ 612&usdhc3 { 613 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 614 pinctrl-0 = <&pinctrl_usdhc3>; 615 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 616 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 617 vmmc-supply = <&buck4>; 618 vqmmc-supply = <&buck5>; 619 bus-width = <8>; 620 non-removable; 621 status = "okay"; 622}; 623 624&wdog1 { 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pinctrl_wdog>; 627 fsl,ext-reset-output; 628 status = "okay"; 629}; 630 631&iomuxc { 632 pinctrl-0 = <&pinctrl_hog_base 633 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 634 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 635 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i 636 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l 637 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o 638 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r 639 &pinctrl_dhcom_s &pinctrl_dhcom_int>; 640 pinctrl-names = "default"; 641 642 pinctrl_dhcom_a: dhcom-a-grp { 643 fsl,pins = < 644 /* ENET_QOS_EVENT0-OUT */ 645 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 646 >; 647 }; 648 649 pinctrl_dhcom_b: dhcom-b-grp { 650 fsl,pins = < 651 /* ENET_QOS_EVENT0-IN */ 652 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 653 >; 654 }; 655 656 pinctrl_dhcom_c: dhcom-c-grp { 657 fsl,pins = < 658 /* GPIO_C */ 659 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 660 >; 661 }; 662 663 pinctrl_dhcom_d: dhcom-d-grp { 664 fsl,pins = < 665 /* GPIO_D */ 666 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 667 >; 668 }; 669 670 pinctrl_dhcom_e: dhcom-e-grp { 671 fsl,pins = < 672 /* GPIO_E */ 673 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 674 >; 675 }; 676 677 pinctrl_dhcom_f: dhcom-f-grp { 678 fsl,pins = < 679 /* GPIO_F */ 680 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 681 >; 682 }; 683 684 pinctrl_dhcom_g: dhcom-g-grp { 685 fsl,pins = < 686 /* GPIO_G */ 687 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 688 >; 689 }; 690 691 pinctrl_dhcom_h: dhcom-h-grp { 692 fsl,pins = < 693 /* GPIO_H */ 694 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 695 >; 696 }; 697 698 pinctrl_dhcom_i: dhcom-i-grp { 699 fsl,pins = < 700 /* CSI1_SYNC */ 701 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 702 >; 703 }; 704 705 pinctrl_dhcom_j: dhcom-j-grp { 706 fsl,pins = < 707 /* CSIx_#RST */ 708 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 709 >; 710 }; 711 712 pinctrl_dhcom_k: dhcom-k-grp { 713 fsl,pins = < 714 /* CSIx_PWDN */ 715 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 716 >; 717 }; 718 719 pinctrl_dhcom_l: dhcom-l-grp { 720 fsl,pins = < 721 /* CSI2_SYNC */ 722 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 723 >; 724 }; 725 726 pinctrl_dhcom_m: dhcom-m-grp { 727 fsl,pins = < 728 /* CSIx_MCLK */ 729 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2 730 >; 731 }; 732 733 pinctrl_dhcom_n: dhcom-n-grp { 734 fsl,pins = < 735 /* CSI2_D3- */ 736 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2 737 >; 738 }; 739 740 pinctrl_dhcom_o: dhcom-o-grp { 741 fsl,pins = < 742 /* CSI2_D3+ */ 743 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2 744 >; 745 }; 746 747 pinctrl_dhcom_p: dhcom-p-grp { 748 fsl,pins = < 749 /* CSI2_D2- */ 750 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2 751 >; 752 }; 753 754 pinctrl_dhcom_q: dhcom-q-grp { 755 fsl,pins = < 756 /* CSI2_D2+ */ 757 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2 758 >; 759 }; 760 761 pinctrl_dhcom_r: dhcom-r-grp { 762 fsl,pins = < 763 /* CSI2_D1- */ 764 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2 765 >; 766 }; 767 768 pinctrl_dhcom_s: dhcom-s-grp { 769 fsl,pins = < 770 /* CSI2_D1+ */ 771 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2 772 >; 773 }; 774 775 pinctrl_dhcom_int: dhcom-int-grp { 776 fsl,pins = < 777 /* INT_HIGHEST_PRIO */ 778 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 779 >; 780 }; 781 782 pinctrl_hog_base: dhcom-hog-base-grp { 783 fsl,pins = < 784 /* GPIOs for memory coding */ 785 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 786 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 787 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 788 /* GPIOs for hardware coding */ 789 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 790 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 791 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 792 >; 793 }; 794 795 pinctrl_ecspi1: dhcom-ecspi1-grp { 796 fsl,pins = < 797 MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44 798 MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44 799 MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44 800 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40 801 >; 802 }; 803 804 pinctrl_ecspi2: dhcom-ecspi2-grp { 805 fsl,pins = < 806 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 807 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 808 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 809 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 810 >; 811 }; 812 813 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */ 814 fsl,pins = < 815 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 816 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 817 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 818 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 819 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 820 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 821 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 822 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 823 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 824 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 825 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 826 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 827 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 828 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 829 >; 830 }; 831 832 pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */ 833 fsl,pins = < 834 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 835 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 836 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 837 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 838 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 839 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f 840 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 841 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 842 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 843 /* Clock */ 844 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f 845 >; 846 }; 847 848 pinctrl_ethphy0: dhcom-ethphy0-grp { 849 fsl,pins = < 850 /* ENET_QOS_#INT Interrupt */ 851 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 852 >; 853 }; 854 855 pinctrl_ethphy1: dhcom-ethphy1-grp { 856 fsl,pins = < 857 /* ENET1_#RST Reset */ 858 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 859 /* ENET1_#INT Interrupt */ 860 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 861 >; 862 }; 863 864 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */ 865 fsl,pins = < 866 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f 867 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 868 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 869 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 870 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 871 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 872 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 873 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 874 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 875 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 876 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 877 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 878 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 879 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 880 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 881 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f 882 >; 883 }; 884 885 pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */ 886 fsl,pins = < 887 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 888 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 889 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 890 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 891 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 892 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91 893 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 894 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 895 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 896 /* Clock */ 897 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f 898 >; 899 }; 900 901 pinctrl_flexcan1: dhcom-flexcan1-grp { 902 fsl,pins = < 903 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 904 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 905 >; 906 }; 907 908 pinctrl_flexcan2: dhcom-flexcan2-grp { 909 fsl,pins = < 910 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 911 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 912 >; 913 }; 914 915 pinctrl_flexspi: dhcom-flexspi-grp { 916 fsl,pins = < 917 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 918 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 919 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 920 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 921 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 922 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 923 >; 924 }; 925 926 pinctrl_hdmi: dhcom-hdmi-grp { 927 fsl,pins = < 928 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 929 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 930 >; 931 }; 932 933 pinctrl_i2c3: dhcom-i2c3-grp { 934 fsl,pins = < 935 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 936 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 937 >; 938 }; 939 940 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { 941 fsl,pins = < 942 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 943 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 944 >; 945 }; 946 947 pinctrl_i2c4: dhcom-i2c4-grp { 948 fsl,pins = < 949 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 950 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 951 >; 952 }; 953 954 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { 955 fsl,pins = < 956 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 957 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 958 >; 959 }; 960 961 pinctrl_i2c5: dhcom-i2c5-grp { 962 fsl,pins = < 963 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 964 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 965 >; 966 }; 967 968 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { 969 fsl,pins = < 970 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 971 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 972 >; 973 }; 974 975 pinctrl_ioexp: dhcom-ioexp-grp { 976 fsl,pins = < 977 /* #GPIO_EXP_INT */ 978 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 979 >; 980 }; 981 982 pinctrl_pmic: dhcom-pmic-grp { 983 fsl,pins = < 984 /* PMIC_nINT */ 985 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 986 >; 987 }; 988 989 pinctrl_pwm1: dhcom-pwm1-grp { 990 fsl,pins = < 991 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 992 >; 993 }; 994 995 pinctrl_tc9595: dhcom-tc9595-grp { 996 fsl,pins = < 997 /* RESET_DSIBRIDGE */ 998 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 999 /* DSI-CONV_INT Interrupt */ 1000 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 1001 >; 1002 }; 1003 1004 pinctrl_sai3: dhcom-sai3-grp { 1005 fsl,pins = < 1006 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 1007 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 1008 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 1009 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 1010 >; 1011 }; 1012 1013 pinctrl_touch: dhcom-touch-grp { 1014 fsl,pins = < 1015 /* #TOUCH_INT */ 1016 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 1017 >; 1018 }; 1019 1020 pinctrl_uart1: dhcom-uart1-grp { 1021 fsl,pins = < 1022 /* Console UART */ 1023 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 1024 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 1025 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 1026 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 1027 >; 1028 }; 1029 1030 pinctrl_uart2: dhcom-uart2-grp { 1031 fsl,pins = < 1032 /* Bluetooth UART */ 1033 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 1034 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 1035 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 1036 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 1037 >; 1038 }; 1039 1040 pinctrl_uart3: dhcom-uart3-grp { 1041 fsl,pins = < 1042 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 1043 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 1044 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 1045 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 1046 >; 1047 }; 1048 1049 pinctrl_uart4: dhcom-uart4-grp { 1050 fsl,pins = < 1051 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 1052 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 1053 >; 1054 }; 1055 1056 pinctrl_usb1_vbus: dhcom-usb1-grp { 1057 fsl,pins = < 1058 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 1059 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 1060 >; 1061 }; 1062 1063 pinctrl_usdhc1: dhcom-usdhc1-grp { 1064 fsl,pins = < 1065 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 1066 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 1067 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 1068 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 1069 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 1070 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 1071 >; 1072 }; 1073 1074 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { 1075 fsl,pins = < 1076 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 1077 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 1078 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 1079 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 1080 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 1081 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 1082 >; 1083 }; 1084 1085 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { 1086 fsl,pins = < 1087 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 1088 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 1089 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 1090 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 1091 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 1092 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 1093 >; 1094 }; 1095 1096 pinctrl_usdhc2: dhcom-usdhc2-grp { 1097 fsl,pins = < 1098 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 1099 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 1100 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 1101 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 1102 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 1103 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 1104 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1105 >; 1106 }; 1107 1108 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { 1109 fsl,pins = < 1110 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 1111 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 1112 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 1113 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 1114 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 1115 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 1116 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1117 >; 1118 }; 1119 1120 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { 1121 fsl,pins = < 1122 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 1123 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 1124 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 1125 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 1126 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 1127 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 1128 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1129 >; 1130 }; 1131 1132 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { 1133 fsl,pins = < 1134 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 1135 >; 1136 }; 1137 1138 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { 1139 fsl,pins = < 1140 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 1141 >; 1142 }; 1143 1144 pinctrl_usdhc3: dhcom-usdhc3-grp { 1145 fsl,pins = < 1146 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1147 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1148 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1149 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1150 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1151 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1152 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1153 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1154 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1155 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1156 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1157 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1158 >; 1159 }; 1160 1161 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { 1162 fsl,pins = < 1163 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1164 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1165 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1166 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1167 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1168 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1169 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1170 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1171 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1172 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1173 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1174 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1175 >; 1176 }; 1177 1178 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { 1179 fsl,pins = < 1180 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1181 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1182 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1183 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1184 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1185 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1186 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1187 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1188 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1189 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1190 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1191 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1192 >; 1193 }; 1194 1195 pinctrl_wdog: dhcom-wdog-grp { 1196 fsl,pins = < 1197 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 1198 >; 1199 }; 1200}; 1201