1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright 2022 Ideas on Board Oy 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/usb/pd.h> 12 13#include "imx8mp.dtsi" 14 15/ { 16 model = "Polyhex Debix Model A i.MX8MPlus board"; 17 compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart2; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_gpio_led>; 27 28 led-0 { 29 function = LED_FUNCTION_POWER; 30 color = <LED_COLOR_ID_RED>; 31 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 32 default-state = "on"; 33 }; 34 }; 35 36 reg_usdhc2_vmmc: regulator-usdhc2 { 37 compatible = "regulator-fixed"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 40 regulator-name = "VSD_3V3"; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46 47 reg_usb_hub: regulator-usb-hub { 48 compatible = "regulator-fixed"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_reg_usb_hub>; 51 regulator-name = "USB_HUB"; 52 regulator-min-microvolt = <5000000>; 53 regulator-max-microvolt = <5000000>; 54 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; 55 enable-active-high; 56 }; 57}; 58 59&A53_0 { 60 cpu-supply = <&buck2>; 61}; 62 63&A53_1 { 64 cpu-supply = <&buck2>; 65}; 66 67&A53_2 { 68 cpu-supply = <&buck2>; 69}; 70 71&A53_3 { 72 cpu-supply = <&buck2>; 73}; 74 75&eqos { 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_eqos>; 78 phy-connection-type = "rgmii-id"; 79 phy-handle = <ðphy0>; 80 status = "okay"; 81 82 mdio { 83 compatible = "snps,dwmac-mdio"; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 ethphy0: ethernet-phy@0 { /* RTL8211E */ 88 compatible = "ethernet-phy-ieee802.3-c22"; 89 reg = <0>; 90 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 91 reset-assert-us = <20>; 92 reset-deassert-us = <200000>; 93 }; 94 }; 95}; 96 97&i2c1 { 98 clock-frequency = <400000>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_i2c1>; 101 status = "okay"; 102 103 pmic@25 { 104 compatible = "nxp,pca9450c"; 105 reg = <0x25>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_pmic>; 108 interrupt-parent = <&gpio1>; 109 interrupts = <3 IRQ_TYPE_EDGE_RISING>; 110 111 regulators { 112 buck1: BUCK1 { 113 regulator-name = "BUCK1"; 114 regulator-min-microvolt = <600000>; 115 regulator-max-microvolt = <2187500>; 116 regulator-boot-on; 117 regulator-always-on; 118 regulator-ramp-delay = <3125>; 119 }; 120 121 buck2: BUCK2 { 122 regulator-name = "BUCK2"; 123 regulator-min-microvolt = <600000>; 124 regulator-max-microvolt = <2187500>; 125 regulator-boot-on; 126 regulator-always-on; 127 regulator-ramp-delay = <3125>; 128 nxp,dvs-run-voltage = <950000>; 129 nxp,dvs-standby-voltage = <850000>; 130 }; 131 132 buck4: BUCK4{ 133 regulator-name = "BUCK4"; 134 regulator-min-microvolt = <600000>; 135 regulator-max-microvolt = <3400000>; 136 regulator-boot-on; 137 regulator-always-on; 138 }; 139 140 buck5: BUCK5{ 141 regulator-name = "BUCK5"; 142 regulator-min-microvolt = <600000>; 143 regulator-max-microvolt = <3400000>; 144 regulator-boot-on; 145 regulator-always-on; 146 }; 147 148 buck6: BUCK6 { 149 regulator-name = "BUCK6"; 150 regulator-min-microvolt = <600000>; 151 regulator-max-microvolt = <3400000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 156 ldo1: LDO1 { 157 regulator-name = "LDO1"; 158 regulator-min-microvolt = <1600000>; 159 regulator-max-microvolt = <3300000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 ldo2: LDO2 { 165 regulator-name = "LDO2"; 166 regulator-min-microvolt = <800000>; 167 regulator-max-microvolt = <1150000>; 168 regulator-boot-on; 169 regulator-always-on; 170 }; 171 172 ldo3: LDO3 { 173 regulator-name = "LDO3"; 174 regulator-min-microvolt = <800000>; 175 regulator-max-microvolt = <3300000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 ldo4: LDO4 { 181 regulator-name = "LDO4"; 182 regulator-min-microvolt = <800000>; 183 regulator-max-microvolt = <3300000>; 184 regulator-boot-on; 185 regulator-always-on; 186 }; 187 188 ldo5: LDO5 { 189 regulator-name = "LDO5"; 190 regulator-min-microvolt = <1800000>; 191 regulator-max-microvolt = <3300000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 }; 196 }; 197}; 198 199&i2c2 { 200 clock-frequency = <100000>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_i2c2>; 203 status = "okay"; 204}; 205 206&i2c3 { 207 clock-frequency = <400000>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_i2c3>; 210 status = "okay"; 211}; 212 213&i2c4 { 214 clock-frequency = <100000>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_i2c4>; 217 status = "okay"; 218 219 eeprom@50 { 220 compatible = "atmel,24c02"; 221 reg = <0x50>; 222 pagesize = <16>; 223 }; 224 225 rtc@51 { 226 compatible = "haoyu,hym8563"; 227 reg = <0x51>; 228 #clock-cells = <0>; 229 clock-frequency = <32768>; 230 clock-output-names = "xin32k"; 231 interrupt-parent = <&gpio2>; 232 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_rtc_int>; 235 }; 236}; 237 238&i2c6 { 239 clock-frequency = <400000>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_i2c6>; 242 status = "okay"; 243}; 244 245&snvs_pwrkey { 246 status = "okay"; 247}; 248 249&uart2 { 250 /* console */ 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_uart2>; 253 status = "okay"; 254}; 255 256&uart3 { 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_uart3>; 259 status = "okay"; 260}; 261 262&uart4 { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_uart4>; 265 status = "okay"; 266}; 267 268&usb3_phy1 { 269 status = "okay"; 270}; 271 272&usb3_1 { 273 status = "okay"; 274}; 275 276&usb_dwc3_1 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_usb1>; 281 dr_mode = "host"; 282 status = "okay"; 283 284 /* 2.x hub on port 1 */ 285 usb_hub_2_x: hub@1 { 286 compatible = "usbbda,5411"; 287 reg = <1>; 288 reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; 289 vdd-supply = <®_usb_hub>; 290 peer-hub = <&usb_hub_3_x>; 291 }; 292 293 /* 3.x hub on port 2 */ 294 usb_hub_3_x: hub@2 { 295 compatible = "usbbda,411"; 296 reg = <2>; 297 reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; 298 vdd-supply = <®_usb_hub>; 299 peer-hub = <&usb_hub_2_x>; 300 }; 301}; 302 303/* SD Card */ 304&usdhc2 { 305 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 306 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 307 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 308 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 309 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 310 vmmc-supply = <®_usdhc2_vmmc>; 311 bus-width = <4>; 312 status = "okay"; 313}; 314 315/* eMMC */ 316&usdhc3 { 317 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 318 assigned-clock-rates = <400000000>; 319 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 320 pinctrl-0 = <&pinctrl_usdhc3>; 321 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 322 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 323 bus-width = <8>; 324 non-removable; 325 status = "okay"; 326}; 327 328&wdog1 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_wdog>; 331 fsl,ext-reset-output; 332 status = "okay"; 333}; 334 335&iomuxc { 336 pinctrl_eqos: eqosgrp { 337 fsl,pins = < 338 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 339 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 340 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 341 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 342 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 343 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 344 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 345 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 346 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 347 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 348 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 349 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 350 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 351 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 352 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f 353 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f 354 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 355 >; 356 }; 357 358 pinctrl_fec: fecgrp { 359 fsl,pins = < 360 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 361 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 362 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 363 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 364 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 365 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 366 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 367 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 368 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 369 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 370 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 371 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 372 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 373 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 374 MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f 375 MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f 376 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 377 >; 378 }; 379 380 pinctrl_gpio_led: gpioledgrp { 381 fsl,pins = < 382 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 383 >; 384 }; 385 386 pinctrl_i2c1: i2c1grp { 387 fsl,pins = < 388 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 389 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 390 >; 391 }; 392 393 pinctrl_i2c2: i2c2grp { 394 fsl,pins = < 395 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 396 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 397 >; 398 }; 399 400 pinctrl_i2c3: i2c3grp { 401 fsl,pins = < 402 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 403 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 404 >; 405 }; 406 407 pinctrl_i2c4: i2c4grp { 408 fsl,pins = < 409 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 410 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 411 >; 412 }; 413 414 pinctrl_i2c6: i2c6grp { 415 fsl,pins = < 416 MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 417 MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 418 >; 419 }; 420 421 pinctrl_pmic: pmicirqgrp { 422 fsl,pins = < 423 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 424 >; 425 }; 426 427 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 428 fsl,pins = < 429 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 430 >; 431 }; 432 433 pinctrl_reg_usb_hub: regusbhubgrp { 434 fsl,pins = < 435 MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x19 436 >; 437 }; 438 439 pinctrl_rtc_int: rtcintgrp { 440 fsl,pins = < 441 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 442 >; 443 }; 444 445 pinctrl_uart2: uart2grp { 446 fsl,pins = < 447 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f 448 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f 449 >; 450 }; 451 452 pinctrl_uart3: uart3grp { 453 fsl,pins = < 454 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 455 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 456 >; 457 }; 458 459 pinctrl_uart4: uart4grp { 460 fsl,pins = < 461 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 462 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 463 >; 464 }; 465 466 pinctrl_usb1: usb1grp { 467 fsl,pins = < 468 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 469 MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 470 >; 471 }; 472 473 pinctrl_usdhc2: usdhc2grp { 474 fsl,pins = < 475 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 476 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 477 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 478 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 479 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 480 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 481 >; 482 }; 483 484 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 485 fsl,pins = < 486 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 487 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 488 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 489 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 490 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 491 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 492 >; 493 }; 494 495 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 496 fsl,pins = < 497 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 498 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 499 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 500 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 501 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 502 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 503 >; 504 }; 505 506 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 507 fsl,pins = < 508 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 509 >; 510 }; 511 512 pinctrl_usdhc3: usdhc3grp { 513 fsl,pins = < 514 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 515 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 516 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 517 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 518 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 519 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 520 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 521 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 522 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 523 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 524 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 525 >; 526 }; 527 528 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 529 fsl,pins = < 530 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 531 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 532 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 533 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 534 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 535 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 536 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 537 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 538 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 539 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 540 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 541 >; 542 }; 543 544 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 545 fsl,pins = < 546 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 547 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 548 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 549 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 550 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 551 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 552 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 553 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 554 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 555 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 556 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 557 >; 558 }; 559 560 pinctrl_wdog: wdoggrp { 561 fsl,pins = < 562 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 563 >; 564 }; 565}; 566