1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks 4 */ 5 6/ { 7 aliases { 8 rtc0 = &rtc; 9 rtc1 = &snvs_rtc; 10 }; 11 12 memory@40000000 { 13 device_type = "memory"; 14 reg = <0x0 0x40000000 0 0xc0000000>, 15 <0x1 0x00000000 0 0xc0000000>; 16 }; 17 18 reg_wl_bt: regulator-wifi-bt { 19 compatible = "regulator-fixed"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_reg_wl_bt>; 22 regulator-name = "wl-bt-pow-dwn"; 23 regulator-min-microvolt = <3300000>; 24 regulator-max-microvolt = <3300000>; 25 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; 26 startup-delay-us = <70000>; 27 regulator-always-on; 28 }; 29}; 30 31&A53_0 { 32 cpu-supply = <&buck2>; 33}; 34 35&A53_1 { 36 cpu-supply = <&buck2>; 37}; 38 39&A53_2 { 40 cpu-supply = <&buck2>; 41}; 42 43&A53_3 { 44 cpu-supply = <&buck2>; 45}; 46 47&eqos { 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_eqos>; 50 phy-mode = "rgmii-id"; 51 phy-handle = <ðphy0>; 52 snps,force_thresh_dma_mode; 53 status = "okay"; 54 55 mdio { 56 compatible = "snps,dwmac-mdio"; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 ethphy0: ethernet-phy@3 { 61 compatible = "ethernet-phy-id0022.1640", 62 "ethernet-phy-ieee802.3-c22"; 63 reg = <3>; 64 reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 65 interrupt-parent = <&gpio1>; 66 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 67 }; 68 }; 69}; 70 71&flexspi { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_flexspi0>; 74 status = "okay"; 75 76 flash0: flash@0 { 77 compatible = "jedec,spi-nor"; 78 reg = <0>; 79 spi-max-frequency = <80000000>; 80 spi-tx-bus-width = <1>; 81 spi-rx-bus-width = <4>; 82 }; 83}; 84 85&i2c1 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_i2c1>; 88 clock-frequency = <384000>; 89 status = "okay"; 90 91 pmic@25 { 92 compatible = "nxp,pca9450c"; 93 reg = <0x25>; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_pmic>; 96 interrupt-parent = <&gpio1>; 97 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 98 99 regulators { 100 buck1: BUCK1 { 101 regulator-name = "BUCK1"; 102 regulator-min-microvolt = <600000>; 103 regulator-max-microvolt = <2187500>; 104 regulator-boot-on; 105 regulator-always-on; 106 regulator-ramp-delay = <3125>; 107 }; 108 109 buck2: BUCK2 { 110 regulator-name = "BUCK2"; 111 regulator-min-microvolt = <600000>; 112 regulator-max-microvolt = <2187500>; 113 regulator-boot-on; 114 regulator-always-on; 115 regulator-ramp-delay = <3125>; 116 nxp,dvs-run-voltage = <950000>; 117 nxp,dvs-standby-voltage = <850000>; 118 }; 119 120 buck4: BUCK4 { 121 regulator-name = "BUCK4"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 regulator-boot-on; 125 regulator-always-on; 126 }; 127 128 buck5: BUCK5 { 129 regulator-name = "BUCK5"; 130 regulator-min-microvolt = <1800000>; 131 regulator-max-microvolt = <1800000>; 132 regulator-boot-on; 133 regulator-always-on; 134 }; 135 136 buck6: BUCK6 { 137 regulator-name = "BUCK6"; 138 regulator-min-microvolt = <600000>; 139 regulator-max-microvolt = <3400000>; 140 regulator-boot-on; 141 regulator-always-on; 142 }; 143 144 ldo1: LDO1 { 145 regulator-name = "LDO1"; 146 regulator-min-microvolt = <1600000>; 147 regulator-max-microvolt = <1800000>; 148 regulator-boot-on; 149 regulator-always-on; 150 }; 151 152 ldo3: LDO3 { 153 regulator-name = "LDO3"; 154 regulator-min-microvolt = <800000>; 155 regulator-max-microvolt = <1800000>; 156 regulator-boot-on; 157 regulator-always-on; 158 }; 159 160 ldo4: LDO4 { 161 regulator-name = "LDO4"; 162 regulator-min-microvolt = <800000>; 163 regulator-max-microvolt = <3300000>; 164 regulator-boot-on; 165 regulator-always-on; 166 }; 167 168 ldo5: LDO5 { 169 regulator-name = "LDO5"; 170 regulator-min-microvolt = <1800000>; 171 regulator-max-microvolt = <3300000>; 172 regulator-boot-on; 173 regulator-always-on; 174 }; 175 }; 176 }; 177}; 178 179&i2c3 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_i2c3>; 182 clock-frequency = <384000>; 183 status = "okay"; 184 185 eeprom@50 { 186 compatible = "atmel,24c64"; 187 reg = <0x50>; 188 pagesize = <32>; 189 read-only; /* Manufacturing EEPROM programmed at factory */ 190 }; 191 192 rtc: rtc@51 { 193 compatible = "nxp,pcf85263"; 194 reg = <0x51>; 195 }; 196}; 197 198&snvs_pwrkey { 199 status = "okay"; 200}; 201 202&uart1 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_uart1>; 205 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 206 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 207 uart-has-rtscts; 208 status = "okay"; 209}; 210 211&usdhc1 { 212 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 213 pinctrl-0 = <&pinctrl_usdhc1>; 214 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 215 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 216 bus-width = <4>; 217 vmmc-supply = <®_wl_bt>; 218 cap-sd-highspeed; 219 sd-uhs-sdr50; 220 sd-uhs-sdr104; 221 keep-power-in-suspend; 222 wakeup-source; 223 non-removable; 224 cap-power-off-card; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 status = "okay"; 228 229 mwifiex: wifi@1 { 230 compatible = "marvell,sd8997"; 231 reg = <1>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_wlan>; 234 interrupt-parent = <&gpio2>; 235 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 236 }; 237}; 238 239&usdhc3 { 240 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 241 pinctrl-0 = <&pinctrl_usdhc3>; 242 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 243 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 244 bus-width = <8>; 245 non-removable; 246 status = "okay"; 247}; 248 249&wdog1 { 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_wdog>; 252 fsl,ext-reset-output; 253 status = "okay"; 254}; 255 256&iomuxc { 257 pinctrl_eqos: eqosgrp { 258 fsl,pins = < 259 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 260 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 261 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 262 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 263 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 264 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 265 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 266 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 267 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 268 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 269 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 270 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 271 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 272 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 273 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 274 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 275 >; 276 }; 277 278 pinctrl_flexspi0: flexspi0grp { 279 fsl,pins = < 280 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 281 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 282 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 283 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 284 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 285 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 286 >; 287 }; 288 289 pinctrl_i2c1: i2c1grp { 290 fsl,pins = < 291 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 292 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 293 >; 294 }; 295 296 pinctrl_i2c3: i2c3grp { 297 fsl,pins = < 298 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 299 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 300 >; 301 }; 302 303 pinctrl_pmic: pmicgrp { 304 fsl,pins = < 305 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 306 >; 307 }; 308 309 pinctrl_reg_wl_bt: reg-wl-btgrp { 310 fsl,pins = < 311 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 312 >; 313 }; 314 315 pinctrl_uart1: uart1grp { 316 fsl,pins = < 317 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 318 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 319 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 320 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 321 >; 322 }; 323 324 pinctrl_usdhc1: usdhc1grp { 325 fsl,pins = < 326 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 327 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 328 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 329 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 330 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 331 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 332 >; 333 }; 334 335 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 336 fsl,pins = < 337 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 338 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 339 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 340 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 341 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 342 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 343 >; 344 }; 345 346 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 347 fsl,pins = < 348 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 349 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 350 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 351 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 352 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 353 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 354 >; 355 }; 356 357 pinctrl_usdhc3: usdhc3grp { 358 fsl,pins = < 359 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 360 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 361 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 362 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 363 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 364 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 365 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 366 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 367 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 368 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 369 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 370 >; 371 }; 372 373 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 374 fsl,pins = < 375 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 376 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 377 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 378 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 379 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 380 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 381 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 382 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 383 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 384 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 385 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 386 >; 387 }; 388 389 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 390 fsl,pins = < 391 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 392 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 393 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 394 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 395 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 396 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 397 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 398 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 399 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 400 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 401 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 402 >; 403 }; 404 405 pinctrl_wdog: wdoggrp { 406 fsl,pins = < 407 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 408 >; 409 }; 410 411 pinctrl_wlan: wlangrp { 412 fsl,pins = < 413 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140 414 >; 415 }; 416}; 417