1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 LogicPD, Inc. dba Beacon EmbeddedWorks 4 */ 5 6/ { 7 aliases { 8 rtc0 = &rtc; 9 rtc1 = &snvs_rtc; 10 }; 11 12 memory@40000000 { 13 device_type = "memory"; 14 reg = <0x0 0x40000000 0 0xc0000000>, 15 <0x1 0x00000000 0 0xc0000000>; 16 }; 17 18 reg_wl_bt: regulator-wifi-bt { 19 compatible = "regulator-fixed"; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_reg_wl_bt>; 22 regulator-name = "wl-bt-pow-dwn"; 23 regulator-min-microvolt = <3300000>; 24 regulator-max-microvolt = <3300000>; 25 gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; 26 startup-delay-us = <70000>; 27 regulator-always-on; 28 }; 29}; 30 31&A53_0 { 32 cpu-supply = <&buck2>; 33}; 34 35&A53_1 { 36 cpu-supply = <&buck2>; 37}; 38 39&A53_2 { 40 cpu-supply = <&buck2>; 41}; 42 43&A53_3 { 44 cpu-supply = <&buck2>; 45}; 46 47&eqos { 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_eqos>; 50 phy-mode = "rgmii-id"; 51 phy-handle = <ðphy0>; 52 snps,force_thresh_dma_mode; 53 snps,mtl-rx-config = <&mtl_rx_setup>; 54 snps,mtl-tx-config = <&mtl_tx_setup>; 55 status = "okay"; 56 57 mdio { 58 compatible = "snps,dwmac-mdio"; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 ethphy0: ethernet-phy@3 { 63 compatible = "ethernet-phy-id0022.1640", 64 "ethernet-phy-ieee802.3-c22"; 65 reg = <3>; 66 reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 67 interrupt-parent = <&gpio1>; 68 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 69 }; 70 }; 71 72 mtl_rx_setup: rx-queues-config { 73 snps,rx-queues-to-use = <5>; 74 75 queue0 { 76 snps,dcb-algorithm; 77 snps,priority = <0x1>; 78 snps,map-to-dma-channel = <0>; 79 }; 80 81 queue1 { 82 snps,dcb-algorithm; 83 snps,priority = <0x2>; 84 snps,map-to-dma-channel = <1>; 85 }; 86 87 queue2 { 88 snps,dcb-algorithm; 89 snps,priority = <0x4>; 90 snps,map-to-dma-channel = <2>; 91 }; 92 93 queue3 { 94 snps,dcb-algorithm; 95 snps,priority = <0x8>; 96 snps,map-to-dma-channel = <3>; 97 }; 98 99 queue4 { 100 snps,dcb-algorithm; 101 snps,priority = <0xf0>; 102 snps,map-to-dma-channel = <4>; 103 }; 104 }; 105 106 mtl_tx_setup: tx-queues-config { 107 snps,tx-queues-to-use = <5>; 108 109 queue0 { 110 snps,dcb-algorithm; 111 snps,priority = <0x1>; 112 }; 113 114 queue1 { 115 snps,dcb-algorithm; 116 snps,priority = <0x2>; 117 }; 118 119 queue2 { 120 snps,dcb-algorithm; 121 snps,priority = <0x4>; 122 }; 123 124 queue3 { 125 snps,dcb-algorithm; 126 snps,priority = <0x8>; 127 }; 128 129 queue4 { 130 snps,dcb-algorithm; 131 snps,priority = <0xf0>; 132 }; 133 }; 134}; 135 136&flexspi { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_flexspi0>; 139 status = "okay"; 140 141 flash0: flash@0 { 142 compatible = "jedec,spi-nor"; 143 reg = <0>; 144 spi-max-frequency = <80000000>; 145 spi-tx-bus-width = <1>; 146 spi-rx-bus-width = <4>; 147 }; 148}; 149 150&i2c1 { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_i2c1>; 153 clock-frequency = <384000>; 154 status = "okay"; 155 156 pmic@25 { 157 compatible = "nxp,pca9450c"; 158 reg = <0x25>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_pmic>; 161 interrupt-parent = <&gpio1>; 162 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 163 164 regulators { 165 buck1: BUCK1 { 166 regulator-name = "BUCK1"; 167 regulator-min-microvolt = <600000>; 168 regulator-max-microvolt = <2187500>; 169 regulator-boot-on; 170 regulator-always-on; 171 regulator-ramp-delay = <3125>; 172 }; 173 174 buck2: BUCK2 { 175 regulator-name = "BUCK2"; 176 regulator-min-microvolt = <600000>; 177 regulator-max-microvolt = <2187500>; 178 regulator-boot-on; 179 regulator-always-on; 180 regulator-ramp-delay = <3125>; 181 nxp,dvs-run-voltage = <950000>; 182 nxp,dvs-standby-voltage = <850000>; 183 }; 184 185 buck4: BUCK4 { 186 regulator-name = "BUCK4"; 187 regulator-min-microvolt = <3300000>; 188 regulator-max-microvolt = <3300000>; 189 regulator-boot-on; 190 regulator-always-on; 191 }; 192 193 buck5: BUCK5 { 194 regulator-name = "BUCK5"; 195 regulator-min-microvolt = <1800000>; 196 regulator-max-microvolt = <1800000>; 197 regulator-boot-on; 198 regulator-always-on; 199 }; 200 201 buck6: BUCK6 { 202 regulator-name = "BUCK6"; 203 regulator-min-microvolt = <600000>; 204 regulator-max-microvolt = <3400000>; 205 regulator-boot-on; 206 regulator-always-on; 207 }; 208 209 ldo1: LDO1 { 210 regulator-name = "LDO1"; 211 regulator-min-microvolt = <1600000>; 212 regulator-max-microvolt = <1800000>; 213 regulator-boot-on; 214 regulator-always-on; 215 }; 216 217 ldo3: LDO3 { 218 regulator-name = "LDO3"; 219 regulator-min-microvolt = <800000>; 220 regulator-max-microvolt = <1800000>; 221 regulator-boot-on; 222 regulator-always-on; 223 }; 224 225 ldo4: LDO4 { 226 regulator-name = "LDO4"; 227 regulator-min-microvolt = <800000>; 228 regulator-max-microvolt = <3300000>; 229 regulator-boot-on; 230 regulator-always-on; 231 }; 232 233 ldo5: LDO5 { 234 regulator-name = "LDO5"; 235 regulator-min-microvolt = <1800000>; 236 regulator-max-microvolt = <3300000>; 237 regulator-boot-on; 238 regulator-always-on; 239 }; 240 }; 241 }; 242}; 243 244&i2c3 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_i2c3>; 247 clock-frequency = <384000>; 248 status = "okay"; 249 250 eeprom@50 { 251 compatible = "atmel,24c64"; 252 reg = <0x50>; 253 pagesize = <32>; 254 read-only; /* Manufacturing EEPROM programmed at factory */ 255 }; 256 257 rtc: rtc@51 { 258 compatible = "nxp,pcf85263"; 259 reg = <0x51>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_rtc>; 262 interrupt-parent = <&gpio1>; 263 interrupts = <13 IRQ_TYPE_LEVEL_LOW>; 264 quartz-load-femtofarads = <12500>; 265 wakeup-source; 266 }; 267}; 268 269&snvs_pwrkey { 270 status = "okay"; 271}; 272 273&uart1 { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_uart1>; 276 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 277 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 278 uart-has-rtscts; 279 status = "okay"; 280 281 bluetooth { 282 compatible = "nxp,88w8997-bt"; 283 }; 284}; 285 286&usdhc1 { 287 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 288 pinctrl-0 = <&pinctrl_usdhc1>; 289 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 290 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 291 bus-width = <4>; 292 vmmc-supply = <®_wl_bt>; 293 cap-sd-highspeed; 294 sd-uhs-sdr50; 295 sd-uhs-sdr104; 296 keep-power-in-suspend; 297 wakeup-source; 298 non-removable; 299 cap-power-off-card; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 status = "okay"; 303 304 mwifiex: wifi@1 { 305 compatible = "marvell,sd8997"; 306 reg = <1>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_wlan>; 309 interrupt-parent = <&gpio2>; 310 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 311 }; 312}; 313 314&usdhc3 { 315 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 316 pinctrl-0 = <&pinctrl_usdhc3>; 317 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 318 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 319 bus-width = <8>; 320 non-removable; 321 status = "okay"; 322}; 323 324&wdog1 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_wdog>; 327 fsl,ext-reset-output; 328 status = "okay"; 329}; 330 331&iomuxc { 332 pinctrl_eqos: eqosgrp { 333 fsl,pins = < 334 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 335 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 336 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 337 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 338 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 339 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 340 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 341 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 342 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 343 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 344 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 345 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 346 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 347 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 348 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 349 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 350 >; 351 }; 352 353 pinctrl_flexspi0: flexspi0grp { 354 fsl,pins = < 355 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 356 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 357 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 358 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 359 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 360 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 361 >; 362 }; 363 364 pinctrl_i2c1: i2c1grp { 365 fsl,pins = < 366 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 367 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 368 >; 369 }; 370 371 pinctrl_i2c3: i2c3grp { 372 fsl,pins = < 373 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 374 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 375 >; 376 }; 377 378 pinctrl_pmic: pmicgrp { 379 fsl,pins = < 380 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 381 >; 382 }; 383 384 pinctrl_reg_wl_bt: reg-wl-btgrp { 385 fsl,pins = < 386 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 387 >; 388 }; 389 390 pinctrl_rtc: rtcgrp { 391 fsl,pins = < 392 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1d0 393 >; 394 }; 395 396 pinctrl_uart1: uart1grp { 397 fsl,pins = < 398 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 399 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 400 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 401 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 402 >; 403 }; 404 405 pinctrl_usdhc1: usdhc1grp { 406 fsl,pins = < 407 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 408 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 409 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 410 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 411 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 412 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 413 >; 414 }; 415 416 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 417 fsl,pins = < 418 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 419 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 420 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 421 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 422 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 423 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 424 >; 425 }; 426 427 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 428 fsl,pins = < 429 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 430 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 431 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 432 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 433 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 434 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 435 >; 436 }; 437 438 pinctrl_usdhc3: usdhc3grp { 439 fsl,pins = < 440 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 441 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 442 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 443 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 444 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 445 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 446 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 447 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 448 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 449 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 450 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 451 >; 452 }; 453 454 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 455 fsl,pins = < 456 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 457 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 458 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 459 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 460 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 461 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 462 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 463 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 464 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 465 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 466 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 467 >; 468 }; 469 470 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 471 fsl,pins = < 472 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 473 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 474 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 475 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 476 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 477 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 478 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 479 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 480 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 481 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 482 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 483 >; 484 }; 485 486 pinctrl_wdog: wdoggrp { 487 fsl,pins = < 488 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 489 >; 490 }; 491 492 pinctrl_wlan: wlangrp { 493 fsl,pins = < 494 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x140 495 >; 496 }; 497}; 498