1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include <dt-bindings/phy/phy-imx8-pcie.h> 10#include "imx8mp.dtsi" 11#include "imx8mp-beacon-som.dtsi" 12 13/ { 14 model = "Beacon EmbeddedWorks i.MX8MPlus Development kit"; 15 compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp"; 16 17 aliases { 18 ethernet0 = &eqos; 19 ethernet1 = &fec; 20 }; 21 22 chosen { 23 stdout-path = &uart2; 24 }; 25 26 connector { 27 compatible = "usb-c-connector"; 28 label = "USB-C"; 29 data-role = "dual"; 30 31 ports { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 port@0 { 36 reg = <0>; 37 38 hs_ep: endpoint { 39 remote-endpoint = <&usb3_hs_ep>; 40 }; 41 }; 42 port@1 { 43 reg = <1>; 44 45 ss_ep: endpoint { 46 remote-endpoint = <&hd3ss3220_in_ep>; 47 }; 48 }; 49 }; 50 }; 51 52 gpio-keys { 53 compatible = "gpio-keys"; 54 autorepeat; 55 56 button-0 { 57 label = "btn0"; 58 linux,code = <BTN_0>; 59 gpios = <&pca6416_1 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 60 wakeup-source; 61 }; 62 63 button-1 { 64 label = "btn1"; 65 linux,code = <BTN_1>; 66 gpios = <&pca6416_1 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 67 wakeup-source; 68 }; 69 70 button-2 { 71 label = "btn2"; 72 linux,code = <BTN_2>; 73 gpios = <&pca6416_1 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 74 wakeup-source; 75 }; 76 77 button-3 { 78 label = "btn3"; 79 linux,code = <BTN_3>; 80 gpios = <&pca6416_1 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 81 wakeup-source; 82 }; 83 }; 84 85 leds { 86 compatible = "gpio-leds"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_led3>; 89 90 led-0 { 91 label = "gen_led0"; 92 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; 93 default-state = "off"; 94 }; 95 96 led-1 { 97 label = "gen_led1"; 98 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 102 led-2 { 103 label = "gen_led2"; 104 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; 105 default-state = "off"; 106 }; 107 108 led-3 { 109 label = "heartbeat"; 110 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 111 linux,default-trigger = "heartbeat"; 112 }; 113 }; 114 115 pcie0_refclk: clock-pcie { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 clock-frequency = <100000000>; 119 }; 120 121 reg_usdhc2_vmmc: regulator-usdhc2 { 122 compatible = "regulator-fixed"; 123 regulator-name = "VSD_3V3"; 124 regulator-min-microvolt = <3300000>; 125 regulator-max-microvolt = <3300000>; 126 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 127 enable-active-high; 128 startup-delay-us = <100>; 129 off-on-delay-us = <20000>; 130 }; 131 132 reg_usb1_host_vbus: regulator-usb1-vbus { 133 compatible = "regulator-fixed"; 134 regulator-name = "usb1_host_vbus"; 135 regulator-max-microvolt = <5000000>; 136 regulator-min-microvolt = <5000000>; 137 gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 }; 140}; 141 142&ecspi2 { 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_ecspi2>; 145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 146 status = "okay"; 147 148 tpm: tpm@0 { 149 compatible = "infineon,slb9670"; 150 reg = <0>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_tpm>; 153 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 154 spi-max-frequency = <18500000>; 155 }; 156}; 157 158&fec { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_fec>; 161 phy-mode = "rgmii-id"; 162 phy-handle = <ðphy1>; 163 fsl,magic-packet; 164 status = "okay"; 165 166 mdio { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 ethphy1: ethernet-phy@3 { 171 compatible = "ethernet-phy-id0022.1640", 172 "ethernet-phy-ieee802.3-c22"; 173 reg = <3>; 174 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 175 reset-assert-us = <10000>; 176 reset-deassert-us = <150000>; 177 interrupt-parent = <&gpio4>; 178 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 179 }; 180 }; 181}; 182 183&flexcan1 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_flexcan1>; 186 status = "okay"; 187}; 188 189&gpio2 { 190 usb-mux-hog { 191 gpio-hog; 192 gpios = <20 0>; 193 output-low; 194 line-name = "USB-C Mux En"; 195 }; 196}; 197 198&i2c2 { 199 clock-frequency = <384000>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_i2c2>; 202 status = "okay"; 203 204 pca6416_3: gpio@20 { 205 compatible = "nxp,pcal6416"; 206 reg = <0x20>; 207 gpio-controller; 208 #gpio-cells = <2>; 209 interrupt-parent = <&gpio4>; 210 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 }; 214}; 215 216&i2c3 { 217 /* Connected to USB Hub */ 218 usb-typec@52 { 219 compatible = "nxp,ptn5110"; 220 reg = <0x52>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_typec>; 223 interrupt-parent = <&gpio4>; 224 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 225 226 connector { 227 compatible = "usb-c-connector"; 228 label = "USB-C"; 229 power-role = "source"; 230 data-role = "host"; 231 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 232 }; 233 }; 234}; 235 236&i2c4 { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_i2c4>; 239 clock-frequency = <384000>; 240 status = "okay"; 241 242 pca6416: gpio@20 { 243 compatible = "nxp,pcal6416"; 244 reg = <0x20>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_pcal6414>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-parent = <&gpio4>; 250 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 255 pca6416_1: gpio@21 { 256 compatible = "nxp,pcal6416"; 257 reg = <0x21>; 258 gpio-controller; 259 #gpio-cells = <2>; 260 interrupt-parent = <&gpio4>; 261 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 265 usb-hub-hog { 266 gpio-hog; 267 gpios = <7 0>; 268 output-low; 269 line-name = "USB Hub Enable"; 270 }; 271 }; 272 273 usb-typec@47 { 274 compatible = "ti,hd3ss3220"; 275 reg = <0x47>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_hd3ss3220>; 278 interrupt-parent = <&gpio4>; 279 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 280 281 ports { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 285 port@0 { 286 reg = <0>; 287 288 hd3ss3220_in_ep: endpoint { 289 remote-endpoint = <&ss_ep>; 290 }; 291 }; 292 293 port@1 { 294 reg = <1>; 295 296 hd3ss3220_out_ep: endpoint { 297 remote-endpoint = <&usb3_role_switch>; 298 }; 299 }; 300 }; 301 }; 302}; 303 304&pcie { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_pcie>; 307 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; 308 status = "okay"; 309}; 310 311&pcie_phy { 312 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 313 clocks = <&pcie0_refclk>; 314 clock-names = "ref"; 315 status = "okay"; 316}; 317 318&snvs_pwrkey { 319 status = "okay"; 320}; 321 322&uart2 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_uart2>; 325 status = "okay"; 326}; 327 328&uart3 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart3>; 331 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 332 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 333 uart-has-rtscts; 334 status = "okay"; 335}; 336 337&usb3_0 { 338 status = "okay"; 339}; 340 341&usb_dwc3_0 { 342 dr_mode = "otg"; 343 hnp-disable; 344 srp-disable; 345 adp-disable; 346 usb-role-switch; 347 status = "okay"; 348 349 ports { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 353 port@0 { 354 reg = <0>; 355 usb3_hs_ep: endpoint { 356 remote-endpoint = <&hs_ep>; 357 }; 358 }; 359 port@1 { 360 reg = <1>; 361 usb3_role_switch: endpoint { 362 remote-endpoint = <&hd3ss3220_out_ep>; 363 }; 364 }; 365 }; 366}; 367 368&usb3_phy0 { 369 vbus-supply = <®_usb1_host_vbus>; 370 status = "okay"; 371}; 372 373&usb3_1 { 374 status = "okay"; 375}; 376 377&usb_dwc3_1 { 378 dr_mode = "host"; 379 status = "okay"; 380}; 381 382&usb3_phy1 { 383 status = "okay"; 384}; 385 386&usdhc2 { 387 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 388 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 389 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 390 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 391 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 392 vmmc-supply = <®_usdhc2_vmmc>; 393 bus-width = <4>; 394 status = "okay"; 395}; 396 397&iomuxc { 398 pinctrl_ecspi2: ecspi2grp { 399 fsl,pins = < 400 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 401 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 402 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 403 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 404 >; 405 }; 406 407 pinctrl_fec: fecgrp { 408 fsl,pins = < 409 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 410 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 411 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 412 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 413 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 414 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 415 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 416 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 417 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 418 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 419 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 420 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 421 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 422 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 423 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x140 424 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 425 >; 426 }; 427 428 pinctrl_flexcan1: flexcan1grp { 429 fsl,pins = < 430 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 431 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 432 >; 433 }; 434 435 pinctrl_hd3ss3220: hd3ss3220grp { 436 fsl,pins = < 437 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x140 438 >; 439 }; 440 441 pinctrl_i2c2: i2c2grp { 442 fsl,pins = < 443 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 444 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 445 >; 446 }; 447 448 pinctrl_i2c4: i2c4grp { 449 fsl,pins = < 450 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 451 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 452 >; 453 }; 454 455 pinctrl_led3: led3grp { 456 fsl,pins = < 457 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 458 >; 459 }; 460 461 pinctrl_pcal6414: pcal6414-gpiogrp { 462 fsl,pins = < 463 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x10 464 >; 465 }; 466 467 pinctrl_pcie: pciegrp { 468 fsl,pins = < 469 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* PCIe_nDIS */ 470 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x10 /* PCIe_nRST */ 471 >; 472 }; 473 474 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 475 fsl,pins = < 476 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 477 >; 478 }; 479 480 pinctrl_tpm: tpmgrp { 481 fsl,pins = < 482 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ 483 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1d6 /* IRQ */ 484 >; 485 }; 486 487 pinctrl_typec: typec1grp { 488 fsl,pins = < 489 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0xc4 490 >; 491 }; 492 493 pinctrl_uart2: uart2grp { 494 fsl,pins = < 495 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 496 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 497 >; 498 }; 499 500 pinctrl_uart3: uart3grp { 501 fsl,pins = < 502 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 503 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 504 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 505 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 506 >; 507 }; 508 509 pinctrl_usdhc2: usdhc2grp { 510 fsl,pins = < 511 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 512 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 513 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 514 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 515 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 516 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 517 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 518 >; 519 }; 520 521 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 522 fsl,pins = < 523 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 524 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 525 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 526 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 527 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 528 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 529 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 530 >; 531 }; 532 533 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 534 fsl,pins = < 535 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 536 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 537 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 538 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 539 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 540 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 541 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 542 >; 543 }; 544 545 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 546 fsl,pins = < 547 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 548 >; 549 }; 550}; 551