1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/net/ti-dp83867.h> 12 13#include "imx8mn.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7902 i.MX8MN board"; 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; 18 19 aliases { 20 usb0 = &usbotg1; 21 }; 22 23 chosen { 24 stdout-path = &uart2; 25 }; 26 27 memory@40000000 { 28 device_type = "memory"; 29 reg = <0x0 0x40000000 0 0x80000000>; 30 }; 31 32 can20m: can20m { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <20000000>; 36 clock-output-names = "can20m"; 37 }; 38 39 gpio-keys { 40 compatible = "gpio-keys"; 41 42 user-pb { 43 label = "user_pb"; 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 45 linux,code = <BTN_0>; 46 }; 47 48 user-pb1x { 49 label = "user_pb1x"; 50 linux,code = <BTN_1>; 51 interrupt-parent = <&gsc>; 52 interrupts = <0>; 53 }; 54 55 key-erased { 56 label = "key_erased"; 57 linux,code = <BTN_2>; 58 interrupt-parent = <&gsc>; 59 interrupts = <1>; 60 }; 61 62 eeprom-wp { 63 label = "eeprom_wp"; 64 linux,code = <BTN_3>; 65 interrupt-parent = <&gsc>; 66 interrupts = <2>; 67 }; 68 69 tamper { 70 label = "tamper"; 71 linux,code = <BTN_4>; 72 interrupt-parent = <&gsc>; 73 interrupts = <5>; 74 }; 75 76 switch-hold { 77 label = "switch_hold"; 78 linux,code = <BTN_5>; 79 interrupt-parent = <&gsc>; 80 interrupts = <7>; 81 }; 82 }; 83 84 led-controller { 85 compatible = "gpio-leds"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_gpio_leds>; 88 89 led-0 { 90 function = LED_FUNCTION_STATUS; 91 color = <LED_COLOR_ID_GREEN>; 92 label = "panel1"; 93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 94 default-state = "off"; 95 }; 96 97 led-1 { 98 function = LED_FUNCTION_STATUS; 99 color = <LED_COLOR_ID_GREEN>; 100 label = "panel2"; 101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 102 default-state = "off"; 103 }; 104 105 led-2 { 106 function = LED_FUNCTION_STATUS; 107 color = <LED_COLOR_ID_GREEN>; 108 label = "panel3"; 109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 110 default-state = "off"; 111 }; 112 113 led-3 { 114 function = LED_FUNCTION_STATUS; 115 color = <LED_COLOR_ID_GREEN>; 116 label = "panel4"; 117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 118 default-state = "off"; 119 }; 120 121 led-4 { 122 function = LED_FUNCTION_STATUS; 123 color = <LED_COLOR_ID_GREEN>; 124 label = "panel5"; 125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 126 default-state = "off"; 127 }; 128 }; 129 130 pps { 131 compatible = "pps-gpio"; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_pps>; 134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 135 status = "okay"; 136 }; 137 138 reg_3p3v: regulator-3p3v { 139 compatible = "regulator-fixed"; 140 regulator-name = "3P3V"; 141 regulator-min-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>; 143 regulator-always-on; 144 }; 145 146 reg_usb1_vbus: regulator-usb1 { 147 compatible = "regulator-fixed"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_reg_usb1>; 150 regulator-name = "usb_usb1_vbus"; 151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 regulator-min-microvolt = <5000000>; 154 regulator-max-microvolt = <5000000>; 155 }; 156 157 reg_wifi: regulator-wifi { 158 compatible = "regulator-fixed"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_reg_wl>; 161 regulator-name = "wifi"; 162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 163 enable-active-high; 164 startup-delay-us = <100>; 165 regulator-min-microvolt = <3300000>; 166 regulator-max-microvolt = <3300000>; 167 }; 168}; 169 170&A53_0 { 171 cpu-supply = <&buck2>; 172}; 173 174&A53_1 { 175 cpu-supply = <&buck2>; 176}; 177 178&A53_2 { 179 cpu-supply = <&buck2>; 180}; 181 182&A53_3 { 183 cpu-supply = <&buck2>; 184}; 185 186&ddrc { 187 operating-points-v2 = <&ddrc_opp_table>; 188 189 ddrc_opp_table: opp-table { 190 compatible = "operating-points-v2"; 191 192 opp-25M { 193 opp-hz = /bits/ 64 <25000000>; 194 }; 195 196 opp-100M { 197 opp-hz = /bits/ 64 <100000000>; 198 }; 199 200 opp-750M { 201 opp-hz = /bits/ 64 <750000000>; 202 }; 203 }; 204}; 205 206&ecspi1 { 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_spi1>; 209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 210 status = "okay"; 211 212 can@0 { 213 compatible = "microchip,mcp2515"; 214 reg = <0>; 215 clocks = <&can20m>; 216 oscillator-frequency = <20000000>; 217 interrupt-parent = <&gpio2>; 218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 219 spi-max-frequency = <10000000>; 220 }; 221}; 222 223&disp_blk_ctrl { 224 status = "disabled"; 225}; 226 227/* off-board header */ 228&ecspi2 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_spi2>; 231 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 232 status = "okay"; 233}; 234 235&fec1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_fec1>; 238 phy-mode = "rgmii-id"; 239 phy-handle = <ðphy0>; 240 local-mac-address = [00 00 00 00 00 00]; 241 status = "okay"; 242 243 mdio { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 ethphy0: ethernet-phy@0 { 248 compatible = "ethernet-phy-ieee802.3-c22"; 249 reg = <0>; 250 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 251 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 252 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 253 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 254 }; 255 }; 256}; 257 258&gpio1 { 259 gpio-line-names = "", "", "", "", "", "", "", "", 260 "", "", "", "", "", "m2_reset", "", "m2_wdis#", 261 "", "", "", "", "", "", "", "", 262 "", "", "", "", "", "", "", ""; 263}; 264 265&gpio2 { 266 gpio-line-names = "", "", "", "", "", "", "", "", 267 "uart2_en#", "", "", "", "", "", "", "", 268 "", "", "", "", "", "", "", "", 269 "", "", "", "", "", "", "", ""; 270}; 271 272&gpio3 { 273 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", 274 "", "", "", "", "", "", "", "", 275 "", "", "", "", "", "", "", "", 276 "", "", "", "", "", "", "", ""; 277}; 278 279&gpio4 { 280 gpio-line-names = "", "", "", "", "", "", "", "", 281 "", "", "", "", "", "", "", "", 282 "", "", "", "", "", "app_gpio1", "", "uart1_rs485", 283 "", "uart1_term", "uart1_half", "app_gpio2", 284 "mipi_gpio1", "", "", ""; 285}; 286 287&gpio5 { 288 gpio-line-names = "", "", "", "mipi_gpio4", 289 "mipi_gpio3", "mipi_gpio2", "", "", 290 "", "", "", "", "", "", "", "", 291 "", "", "", "", "", "", "", "", 292 "", "", "", "", "", "", "", ""; 293}; 294 295&gpu { 296 status = "disabled"; 297}; 298 299&i2c1 { 300 clock-frequency = <100000>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_i2c1>; 303 status = "okay"; 304 305 gsc: gsc@20 { 306 compatible = "gw,gsc"; 307 reg = <0x20>; 308 pinctrl-0 = <&pinctrl_gsc>; 309 interrupt-parent = <&gpio2>; 310 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 311 interrupt-controller; 312 #interrupt-cells = <1>; 313 314 adc { 315 compatible = "gw,gsc-adc"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 channel@6 { 320 gw,mode = <0>; 321 reg = <0x06>; 322 label = "temp"; 323 }; 324 325 channel@8 { 326 gw,mode = <1>; 327 reg = <0x08>; 328 label = "vdd_bat"; 329 }; 330 331 channel@82 { 332 gw,mode = <2>; 333 reg = <0x82>; 334 label = "vin"; 335 gw,voltage-divider-ohms = <22100 1000>; 336 gw,voltage-offset-microvolt = <700000>; 337 }; 338 339 channel@84 { 340 gw,mode = <2>; 341 reg = <0x84>; 342 label = "vin_4p0"; 343 gw,voltage-divider-ohms = <10000 10000>; 344 }; 345 346 channel@86 { 347 gw,mode = <2>; 348 reg = <0x86>; 349 label = "vdd_3p3"; 350 gw,voltage-divider-ohms = <10000 10000>; 351 }; 352 353 channel@88 { 354 gw,mode = <2>; 355 reg = <0x88>; 356 label = "vdd_0p9"; 357 }; 358 359 channel@8c { 360 gw,mode = <2>; 361 reg = <0x8c>; 362 label = "vdd_soc"; 363 }; 364 365 channel@8e { 366 gw,mode = <2>; 367 reg = <0x8e>; 368 label = "vdd_arm"; 369 }; 370 371 channel@90 { 372 gw,mode = <2>; 373 reg = <0x90>; 374 label = "vdd_1p8"; 375 }; 376 377 channel@92 { 378 gw,mode = <2>; 379 reg = <0x92>; 380 label = "vdd_dram"; 381 }; 382 383 channel@98 { 384 gw,mode = <2>; 385 reg = <0x98>; 386 label = "vdd_1p0"; 387 }; 388 389 channel@9a { 390 gw,mode = <2>; 391 reg = <0x9a>; 392 label = "vdd_2p5"; 393 gw,voltage-divider-ohms = <10000 10000>; 394 }; 395 396 channel@a2 { 397 gw,mode = <2>; 398 reg = <0xa2>; 399 label = "vdd_gsc"; 400 gw,voltage-divider-ohms = <10000 10000>; 401 }; 402 }; 403 }; 404 405 gpio: gpio@23 { 406 compatible = "nxp,pca9555"; 407 reg = <0x23>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-parent = <&gsc>; 411 interrupts = <4>; 412 }; 413 414 pmic@4b { 415 compatible = "rohm,bd71847"; 416 reg = <0x4b>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_pmic>; 419 interrupt-parent = <&gpio3>; 420 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 421 rohm,reset-snvs-powered; 422 #clock-cells = <0>; 423 clocks = <&osc_32k 0>; 424 clock-output-names = "clk-32k-out"; 425 426 regulators { 427 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 428 BUCK1 { 429 regulator-name = "buck1"; 430 regulator-min-microvolt = <700000>; 431 regulator-max-microvolt = <1300000>; 432 regulator-boot-on; 433 regulator-always-on; 434 regulator-ramp-delay = <1250>; 435 }; 436 437 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 438 buck2: BUCK2 { 439 regulator-name = "buck2"; 440 regulator-min-microvolt = <700000>; 441 regulator-max-microvolt = <1300000>; 442 regulator-boot-on; 443 regulator-always-on; 444 regulator-ramp-delay = <1250>; 445 rohm,dvs-run-voltage = <1000000>; 446 rohm,dvs-idle-voltage = <900000>; 447 }; 448 449 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 450 BUCK3 { 451 regulator-name = "buck3"; 452 regulator-min-microvolt = <700000>; 453 regulator-max-microvolt = <1350000>; 454 regulator-boot-on; 455 regulator-always-on; 456 }; 457 458 /* vdd_3p3 */ 459 BUCK4 { 460 regulator-name = "buck4"; 461 regulator-min-microvolt = <3000000>; 462 regulator-max-microvolt = <3300000>; 463 regulator-boot-on; 464 regulator-always-on; 465 }; 466 467 /* vdd_1p8 */ 468 BUCK5 { 469 regulator-name = "buck5"; 470 regulator-min-microvolt = <1605000>; 471 regulator-max-microvolt = <1995000>; 472 regulator-boot-on; 473 regulator-always-on; 474 }; 475 476 /* vdd_dram */ 477 BUCK6 { 478 regulator-name = "buck6"; 479 regulator-min-microvolt = <800000>; 480 regulator-max-microvolt = <1400000>; 481 regulator-boot-on; 482 regulator-always-on; 483 }; 484 485 /* nvcc_snvs_1p8 */ 486 LDO1 { 487 regulator-name = "ldo1"; 488 regulator-min-microvolt = <1600000>; 489 regulator-max-microvolt = <1900000>; 490 regulator-boot-on; 491 regulator-always-on; 492 }; 493 494 /* vdd_snvs_0p8 */ 495 LDO2 { 496 regulator-name = "ldo2"; 497 regulator-min-microvolt = <800000>; 498 regulator-max-microvolt = <900000>; 499 regulator-boot-on; 500 regulator-always-on; 501 }; 502 503 /* vdda_1p8 */ 504 LDO3 { 505 regulator-name = "ldo3"; 506 regulator-min-microvolt = <1800000>; 507 regulator-max-microvolt = <3300000>; 508 regulator-boot-on; 509 regulator-always-on; 510 }; 511 512 LDO4 { 513 regulator-name = "ldo4"; 514 regulator-min-microvolt = <900000>; 515 regulator-max-microvolt = <1800000>; 516 regulator-boot-on; 517 regulator-always-on; 518 }; 519 520 LDO6 { 521 regulator-name = "ldo6"; 522 regulator-min-microvolt = <900000>; 523 regulator-max-microvolt = <1800000>; 524 regulator-boot-on; 525 regulator-always-on; 526 }; 527 }; 528 }; 529 530 eeprom@50 { 531 compatible = "atmel,24c02"; 532 reg = <0x50>; 533 pagesize = <16>; 534 }; 535 536 eeprom@51 { 537 compatible = "atmel,24c02"; 538 reg = <0x51>; 539 pagesize = <16>; 540 }; 541 542 eeprom@52 { 543 compatible = "atmel,24c02"; 544 reg = <0x52>; 545 pagesize = <16>; 546 }; 547 548 eeprom@53 { 549 compatible = "atmel,24c02"; 550 reg = <0x53>; 551 pagesize = <16>; 552 }; 553 554 rtc@68 { 555 compatible = "dallas,ds1672"; 556 reg = <0x68>; 557 }; 558}; 559 560&i2c2 { 561 clock-frequency = <400000>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_i2c2>; 564 status = "okay"; 565 566 accelerometer@19 { 567 compatible = "st,lis2de12"; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_accel>; 570 reg = <0x19>; 571 st,drdy-int-pin = <1>; 572 interrupt-parent = <&gpio1>; 573 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 574 interrupt-names = "INT1"; 575 }; 576}; 577 578/* off-board header */ 579&i2c3 { 580 clock-frequency = <400000>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pinctrl_i2c3>; 583 status = "okay"; 584}; 585 586/* off-board header */ 587&i2c4 { 588 clock-frequency = <400000>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pinctrl_i2c4>; 591 status = "okay"; 592}; 593 594&pgc_gpumix { 595 status = "disabled"; 596}; 597 598/* off-board header */ 599&sai3 { 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_sai3>; 602 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 603 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 604 assigned-clock-rates = <24576000>; 605 status = "okay"; 606}; 607 608/* RS232/RS485/RS422 selectable */ 609&uart1 { 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 612 status = "okay"; 613}; 614 615/* RS232 console */ 616&uart2 { 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_uart2>; 619 status = "okay"; 620}; 621 622/* bluetooth HCI */ 623&uart3 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 626 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 627 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 628 status = "okay"; 629 630 bluetooth { 631 compatible = "brcm,bcm4330-bt"; 632 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 633 }; 634}; 635 636/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ 637&uart4 { 638 pinctrl-names = "default"; 639 pinctrl-0 = <&pinctrl_uart4>; 640 status = "okay"; 641}; 642 643&usbotg1 { 644 dr_mode = "host"; 645 vbus-supply = <®_usb1_vbus>; 646 disable-over-current; 647 status = "okay"; 648}; 649 650/* SDIO WiFi */ 651&usdhc2 { 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_usdhc2>; 654 bus-width = <4>; 655 non-removable; 656 vmmc-supply = <®_wifi>; 657 status = "okay"; 658}; 659 660/* eMMC */ 661&usdhc3 { 662 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 663 pinctrl-0 = <&pinctrl_usdhc3>; 664 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 665 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 666 bus-width = <8>; 667 non-removable; 668 status = "okay"; 669}; 670 671&wdog1 { 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_wdog>; 674 fsl,ext-reset-output; 675 status = "okay"; 676}; 677 678&iomuxc { 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pinctrl_hog>; 681 682 pinctrl_hog: hoggrp { 683 fsl,pins = < 684 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 685 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ 686 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 687 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 688 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ 689 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ 690 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ 691 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ 692 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ 693 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ 694 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ 695 >; 696 }; 697 698 pinctrl_accel: accelgrp { 699 fsl,pins = < 700 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 701 >; 702 }; 703 704 pinctrl_fec1: fec1grp { 705 fsl,pins = < 706 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 707 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 708 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 709 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 710 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 711 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 712 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 713 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 714 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 715 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 716 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 717 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 718 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 719 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 720 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ 721 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ 722 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 723 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 724 >; 725 }; 726 727 pinctrl_gsc: gscgrp { 728 fsl,pins = < 729 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 730 >; 731 }; 732 733 pinctrl_i2c1: i2c1grp { 734 fsl,pins = < 735 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 736 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 737 >; 738 }; 739 740 pinctrl_i2c2: i2c2grp { 741 fsl,pins = < 742 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 743 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 744 >; 745 }; 746 747 pinctrl_i2c3: i2c3grp { 748 fsl,pins = < 749 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 750 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 751 >; 752 }; 753 754 pinctrl_i2c4: i2c4grp { 755 fsl,pins = < 756 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 757 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 758 >; 759 }; 760 761 pinctrl_gpio_leds: gpioledgrp { 762 fsl,pins = < 763 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 764 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 765 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 766 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 767 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 768 >; 769 }; 770 771 pinctrl_pmic: pmicgrp { 772 fsl,pins = < 773 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 774 >; 775 }; 776 777 pinctrl_pps: ppsgrp { 778 fsl,pins = < 779 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ 780 >; 781 }; 782 783 pinctrl_reg_wl: regwlgrp { 784 fsl,pins = < 785 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ 786 >; 787 }; 788 789 pinctrl_reg_usb1: regusb1grp { 790 fsl,pins = < 791 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 792 >; 793 }; 794 795 pinctrl_sai3: sai3grp { 796 fsl,pins = < 797 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 798 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 799 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 800 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 801 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 802 >; 803 }; 804 805 pinctrl_spi1: spi1grp { 806 fsl,pins = < 807 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 808 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 809 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 810 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 811 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ 812 >; 813 }; 814 815 pinctrl_spi2: spi2grp { 816 fsl,pins = < 817 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 818 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 819 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 820 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ 821 >; 822 }; 823 824 pinctrl_uart1: uart1grp { 825 fsl,pins = < 826 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 827 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 828 >; 829 }; 830 831 pinctrl_uart1_gpio: uart1gpiogrp { 832 fsl,pins = < 833 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ 834 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ 835 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ 836 >; 837 }; 838 839 pinctrl_uart2: uart2grp { 840 fsl,pins = < 841 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 842 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 843 >; 844 }; 845 846 pinctrl_uart3_gpio: uart3_gpiogrp { 847 fsl,pins = < 848 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ 849 >; 850 }; 851 852 pinctrl_uart3: uart3grp { 853 fsl,pins = < 854 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 855 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 856 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ 857 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ 858 >; 859 }; 860 861 pinctrl_uart4: uart4grp { 862 fsl,pins = < 863 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 864 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 865 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ 866 >; 867 }; 868 869 pinctrl_usdhc2: usdhc2grp { 870 fsl,pins = < 871 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 872 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 873 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 874 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 875 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 876 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 877 >; 878 }; 879 880 pinctrl_usdhc3: usdhc3grp { 881 fsl,pins = < 882 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 883 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 884 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 885 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 886 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 887 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 888 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 889 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 890 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 891 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 892 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 893 >; 894 }; 895 896 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 897 fsl,pins = < 898 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 899 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 900 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 901 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 902 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 903 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 904 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 905 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 906 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 907 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 908 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 909 >; 910 }; 911 912 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 913 fsl,pins = < 914 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 915 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 916 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 917 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 918 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 919 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 920 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 921 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 922 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 923 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 924 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 925 >; 926 }; 927 928 pinctrl_wdog: wdoggrp { 929 fsl,pins = < 930 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 931 >; 932 }; 933}; 934