1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/usb/pd.h> 7#include "imx8mn.dtsi" 8 9/ { 10 chosen { 11 stdout-path = &uart2; 12 }; 13 14 gpio-leds { 15 compatible = "gpio-leds"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_led>; 18 19 status { 20 label = "yellow:status"; 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 22 default-state = "on"; 23 }; 24 }; 25 26 hdmi-connector { 27 compatible = "hdmi-connector"; 28 label = "hdmi"; 29 type = "a"; 30 31 port { 32 hdmi_connector_in: endpoint { 33 remote-endpoint = <&adv7533_out>; 34 }; 35 }; 36 }; 37 38 memory@40000000 { 39 device_type = "memory"; 40 reg = <0x0 0x40000000 0 0x80000000>; 41 }; 42 43 reg_usdhc2_vmmc: regulator-usdhc2 { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 47 regulator-name = "VSD_3V3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 51 off-on-delay-us = <12000>; 52 enable-active-high; 53 }; 54 55 ir-receiver { 56 compatible = "gpio-ir-receiver"; 57 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ir>; 60 linux,autosuspend-period = <125>; 61 }; 62 63 audio_codec_bt_sco: audio-codec-bt-sco { 64 compatible = "linux,bt-sco"; 65 #sound-dai-cells = <1>; 66 }; 67 68 wm8524: audio-codec { 69 #sound-dai-cells = <0>; 70 compatible = "wlf,wm8524"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_wlf>; 73 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 74 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; 75 clock-names = "mclk"; 76 }; 77 78 sound-bt-sco { 79 compatible = "simple-audio-card"; 80 simple-audio-card,name = "bt-sco-audio"; 81 simple-audio-card,format = "dsp_a"; 82 simple-audio-card,bitclock-inversion; 83 simple-audio-card,frame-master = <&btcpu>; 84 simple-audio-card,bitclock-master = <&btcpu>; 85 86 btcpu: simple-audio-card,cpu { 87 sound-dai = <&sai2>; 88 dai-tdm-slot-num = <2>; 89 dai-tdm-slot-width = <16>; 90 }; 91 92 simple-audio-card,codec { 93 sound-dai = <&audio_codec_bt_sco 1>; 94 }; 95 }; 96 97 sound-wm8524 { 98 compatible = "fsl,imx-audio-wm8524"; 99 model = "wm8524-audio"; 100 audio-cpu = <&sai3>; 101 audio-codec = <&wm8524>; 102 audio-asrc = <&easrc>; 103 audio-routing = 104 "Line Out Jack", "LINEVOUTL", 105 "Line Out Jack", "LINEVOUTR"; 106 }; 107 108 sound-spdif { 109 compatible = "fsl,imx-audio-spdif"; 110 model = "imx-spdif"; 111 spdif-controller = <&spdif1>; 112 spdif-out; 113 spdif-in; 114 }; 115}; 116 117&easrc { 118 fsl,asrc-rate = <48000>; 119 status = "okay"; 120}; 121 122&fec1 { 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_fec1>; 125 phy-mode = "rgmii-id"; 126 phy-handle = <ðphy0>; 127 fsl,magic-packet; 128 status = "okay"; 129 130 mdio { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 ethphy0: ethernet-phy@0 { 135 compatible = "ethernet-phy-ieee802.3-c22"; 136 reg = <0>; 137 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 138 reset-assert-us = <10000>; 139 qca,disable-smarteee; 140 vddio-supply = <&vddio>; 141 142 vddio: vddio-regulator { 143 regulator-min-microvolt = <1800000>; 144 regulator-max-microvolt = <1800000>; 145 }; 146 }; 147 }; 148}; 149 150&flexspi { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_flexspi>; 153 status = "okay"; 154 155 flash0: flash@0 { 156 compatible = "jedec,spi-nor"; 157 reg = <0>; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 spi-max-frequency = <166000000>; 161 spi-tx-bus-width = <4>; 162 spi-rx-bus-width = <4>; 163 }; 164}; 165 166&i2c1 { 167 clock-frequency = <400000>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_i2c1>; 170 status = "okay"; 171}; 172 173&i2c2 { 174 clock-frequency = <400000>; 175 pinctrl-names = "default", "gpio"; 176 pinctrl-0 = <&pinctrl_i2c2>; 177 pinctrl-1 = <&pinctrl_i2c2_gpio>; 178 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 179 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 180 status = "okay"; 181 182 hdmi@3d { 183 compatible = "adi,adv7535"; 184 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 185 reg-names = "main", "cec", "edid", "packet"; 186 adi,dsi-lanes = <4>; 187 188 adi,input-depth = <8>; 189 adi,input-colorspace = "rgb"; 190 adi,input-clock = "1x"; 191 adi,input-style = <1>; 192 adi,input-justification = "evenly"; 193 194 ports { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 port@0 { 199 reg = <0>; 200 201 adv7533_in: endpoint { 202 remote-endpoint = <&dsi_out>; 203 }; 204 }; 205 206 port@1 { 207 reg = <1>; 208 209 adv7533_out: endpoint { 210 remote-endpoint = <&hdmi_connector_in>; 211 }; 212 }; 213 214 }; 215 }; 216 217 ptn5110: tcpc@50 { 218 compatible = "nxp,ptn5110"; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_typec1>; 221 reg = <0x50>; 222 interrupt-parent = <&gpio2>; 223 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 224 status = "okay"; 225 226 port { 227 typec1_dr_sw: endpoint { 228 remote-endpoint = <&usb1_drd_sw>; 229 }; 230 }; 231 232 typec1_con: connector { 233 compatible = "usb-c-connector"; 234 label = "USB-C"; 235 power-role = "dual"; 236 data-role = "dual"; 237 try-power-role = "sink"; 238 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 239 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 240 PDO_VAR(5000, 20000, 3000)>; 241 op-sink-microwatt = <15000000>; 242 self-powered; 243 }; 244 }; 245}; 246 247&i2c3 { 248 clock-frequency = <400000>; 249 pinctrl-names = "default", "gpio"; 250 pinctrl-0 = <&pinctrl_i2c3>; 251 pinctrl-1 = <&pinctrl_i2c3_gpio>; 252 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 253 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 254 status = "okay"; 255 256 pca6416: gpio@20 { 257 compatible = "ti,tca6416"; 258 reg = <0x20>; 259 gpio-controller; 260 #gpio-cells = <2>; 261 }; 262 263 camera@3c { 264 compatible = "ovti,ov5640"; 265 reg = <0x3c>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_camera>; 268 clocks = <&clk IMX8MN_CLK_CLKO1>; 269 clock-names = "xclk"; 270 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; 271 assigned-clock-parents = <&clk IMX8MN_CLK_24M>; 272 assigned-clock-rates = <24000000>; 273 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 274 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 275 276 port { 277 ov5640_to_mipi_csi2: endpoint { 278 remote-endpoint = <&imx8mn_mipi_csi_in>; 279 clock-lanes = <0>; 280 data-lanes = <1 2>; 281 }; 282 }; 283 }; 284}; 285 286&isi { 287 status = "okay"; 288}; 289 290&mipi_csi { 291 status = "okay"; 292 293 ports { 294 port@0 { 295 imx8mn_mipi_csi_in: endpoint { 296 remote-endpoint = <&ov5640_to_mipi_csi2>; 297 data-lanes = <1 2>; 298 }; 299 }; 300 }; 301}; 302 303&lcdif { 304 status = "okay"; 305}; 306 307&mipi_dsi { 308 samsung,esc-clock-frequency = <10000000>; 309 status = "okay"; 310 311 ports { 312 port@1 { 313 reg = <1>; 314 315 dsi_out: endpoint { 316 remote-endpoint = <&adv7533_in>; 317 data-lanes = <1 2 3 4>; 318 }; 319 }; 320 }; 321}; 322 323&sai2 { 324 #sound-dai-cells = <0>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_sai2>; 327 assigned-clocks = <&clk IMX8MN_CLK_SAI2>; 328 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 329 assigned-clock-rates = <24576000>; 330 status = "okay"; 331}; 332 333&sai3 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_sai3>; 336 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 337 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 338 assigned-clock-rates = <24576000>; 339 fsl,sai-mclk-direction-output; 340 status = "okay"; 341}; 342 343&snvs_pwrkey { 344 status = "okay"; 345}; 346 347&spdif1 { 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_spdif1>; 350 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; 351 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 352 assigned-clock-rates = <24576000>; 353 status = "okay"; 354}; 355 356&uart1 { /* BT */ 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_uart1>; 359 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 360 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 361 uart-has-rtscts; 362 status = "okay"; 363}; 364 365&uart2 { /* console */ 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_uart2>; 368 status = "okay"; 369}; 370 371&uart3 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_uart3>; 374 assigned-clocks = <&clk IMX8MN_CLK_UART3>; 375 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 376 uart-has-rtscts; 377 status = "okay"; 378}; 379 380&usbphynop1 { 381 wakeup-source; 382}; 383 384&usbotg1 { 385 dr_mode = "otg"; 386 hnp-disable; 387 srp-disable; 388 adp-disable; 389 usb-role-switch; 390 disable-over-current; 391 samsung,picophy-pre-emp-curr-control = <3>; 392 samsung,picophy-dc-vol-level-adjust = <7>; 393 status = "okay"; 394 395 port { 396 usb1_drd_sw: endpoint { 397 remote-endpoint = <&typec1_dr_sw>; 398 }; 399 }; 400}; 401 402&usdhc2 { 403 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; 404 assigned-clock-rates = <200000000>; 405 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 406 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 407 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 408 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 409 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 410 bus-width = <4>; 411 vmmc-supply = <®_usdhc2_vmmc>; 412 status = "okay"; 413}; 414 415&usdhc3 { 416 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 417 assigned-clock-rates = <400000000>; 418 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 419 pinctrl-0 = <&pinctrl_usdhc3>; 420 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 421 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 422 bus-width = <8>; 423 non-removable; 424 status = "okay"; 425}; 426 427&wdog1 { 428 pinctrl-names = "default"; 429 pinctrl-0 = <&pinctrl_wdog>; 430 fsl,ext-reset-output; 431 status = "okay"; 432}; 433 434&iomuxc { 435 pinctrl_camera: cameragrp { 436 fsl,pins = < 437 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 438 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 439 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 440 >; 441 }; 442 443 pinctrl_fec1: fec1grp { 444 fsl,pins = < 445 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 446 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 447 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 448 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 449 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 450 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 451 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 452 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 453 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 454 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 455 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 456 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 457 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 458 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 459 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 460 >; 461 }; 462 463 pinctrl_flexspi: flexspigrp { 464 fsl,pins = < 465 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 466 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 467 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 468 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 469 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 470 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 471 >; 472 }; 473 474 pinctrl_gpio_led: gpioledgrp { 475 fsl,pins = < 476 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 477 >; 478 }; 479 480 pinctrl_gpio_wlf: gpiowlfgrp { 481 fsl,pins = < 482 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 483 >; 484 }; 485 486 pinctrl_ir: irgrp { 487 fsl,pins = < 488 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 489 >; 490 }; 491 492 pinctrl_i2c1: i2c1grp { 493 fsl,pins = < 494 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 495 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 496 >; 497 }; 498 499 pinctrl_i2c2: i2c2grp { 500 fsl,pins = < 501 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 502 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 503 >; 504 }; 505 506 pinctrl_i2c2_gpio: i2c2gpiogrp { 507 fsl,pins = < 508 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 509 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 510 >; 511 }; 512 513 pinctrl_i2c3: i2c3grp { 514 fsl,pins = < 515 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 516 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 517 >; 518 }; 519 520 pinctrl_i2c3_gpio: i2c3gpiogrp { 521 fsl,pins = < 522 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 523 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 524 >; 525 }; 526 527 pinctrl_pmic: pmicirqgrp { 528 fsl,pins = < 529 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 530 >; 531 }; 532 533 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 534 fsl,pins = < 535 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 536 >; 537 }; 538 539 pinctrl_sai2: sai2grp { 540 fsl,pins = < 541 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 542 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 543 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 544 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 545 >; 546 }; 547 548 pinctrl_sai3: sai3grp { 549 fsl,pins = < 550 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 551 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 552 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 553 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 554 >; 555 }; 556 557 pinctrl_spdif1: spdif1grp { 558 fsl,pins = < 559 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 560 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 561 >; 562 }; 563 564 pinctrl_typec1: typec1grp { 565 fsl,pins = < 566 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 567 >; 568 }; 569 570 pinctrl_uart1: uart1grp { 571 fsl,pins = < 572 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 573 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 574 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 575 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 576 >; 577 }; 578 579 pinctrl_uart2: uart2grp { 580 fsl,pins = < 581 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 582 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 583 >; 584 }; 585 586 pinctrl_uart3: uart3grp { 587 fsl,pins = < 588 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 589 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 590 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 591 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 592 >; 593 }; 594 595 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 596 fsl,pins = < 597 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 598 >; 599 }; 600 601 pinctrl_usdhc2: usdhc2grp { 602 fsl,pins = < 603 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 604 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 605 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 606 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 607 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 608 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 609 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 610 >; 611 }; 612 613 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 614 fsl,pins = < 615 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 616 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 617 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 618 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 619 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 620 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 621 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 622 >; 623 }; 624 625 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 626 fsl,pins = < 627 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 628 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 629 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 630 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 631 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 632 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 633 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 634 >; 635 }; 636 637 pinctrl_usdhc3: usdhc3grp { 638 fsl,pins = < 639 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 640 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 641 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 642 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 643 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 644 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 645 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 646 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 647 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 648 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 649 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 650 >; 651 }; 652 653 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 654 fsl,pins = < 655 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 656 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 657 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 658 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 659 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 660 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 661 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 662 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 663 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 664 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 665 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 666 >; 667 }; 668 669 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 670 fsl,pins = < 671 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 672 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 673 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 674 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 675 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 676 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 677 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 678 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 679 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 680 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 681 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 682 >; 683 }; 684 685 pinctrl_wdog: wdoggrp { 686 fsl,pins = < 687 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 688 >; 689 }; 690}; 691