1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mm-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 serial0 = &uart1; 34 serial1 = &uart2; 35 serial2 = &uart3; 36 serial3 = &uart4; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &ecspi3; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 idle-states { 47 entry-method = "psci"; 48 49 cpu_pd_wait: cpu-pd-wait { 50 compatible = "arm,idle-state"; 51 arm,psci-suspend-param = <0x0010033>; 52 local-timer-stop; 53 entry-latency-us = <1000>; 54 exit-latency-us = <700>; 55 min-residency-us = <2700>; 56 }; 57 }; 58 59 A53_0: cpu@0 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0>; 63 clock-latency = <61036>; /* two CLK32 periods */ 64 clocks = <&clk IMX8MM_CLK_ARM>; 65 enable-method = "psci"; 66 next-level-cache = <&A53_L2>; 67 operating-points-v2 = <&a53_opp_table>; 68 nvmem-cells = <&cpu_speed_grade>; 69 nvmem-cell-names = "speed_grade"; 70 cpu-idle-states = <&cpu_pd_wait>; 71 #cooling-cells = <2>; 72 }; 73 74 A53_1: cpu@1 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x1>; 78 clock-latency = <61036>; /* two CLK32 periods */ 79 clocks = <&clk IMX8MM_CLK_ARM>; 80 enable-method = "psci"; 81 next-level-cache = <&A53_L2>; 82 operating-points-v2 = <&a53_opp_table>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 #cooling-cells = <2>; 85 }; 86 87 A53_2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x2>; 91 clock-latency = <61036>; /* two CLK32 periods */ 92 clocks = <&clk IMX8MM_CLK_ARM>; 93 enable-method = "psci"; 94 next-level-cache = <&A53_L2>; 95 operating-points-v2 = <&a53_opp_table>; 96 cpu-idle-states = <&cpu_pd_wait>; 97 #cooling-cells = <2>; 98 }; 99 100 A53_3: cpu@3 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a53"; 103 reg = <0x3>; 104 clock-latency = <61036>; /* two CLK32 periods */ 105 clocks = <&clk IMX8MM_CLK_ARM>; 106 enable-method = "psci"; 107 next-level-cache = <&A53_L2>; 108 operating-points-v2 = <&a53_opp_table>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 #cooling-cells = <2>; 111 }; 112 113 A53_L2: l2-cache0 { 114 compatible = "cache"; 115 }; 116 }; 117 118 a53_opp_table: opp-table { 119 compatible = "operating-points-v2"; 120 opp-shared; 121 122 opp-1200000000 { 123 opp-hz = /bits/ 64 <1200000000>; 124 opp-microvolt = <850000>; 125 opp-supported-hw = <0xe>, <0x7>; 126 clock-latency-ns = <150000>; 127 opp-suspend; 128 }; 129 130 opp-1600000000 { 131 opp-hz = /bits/ 64 <1600000000>; 132 opp-microvolt = <950000>; 133 opp-supported-hw = <0xc>, <0x7>; 134 clock-latency-ns = <150000>; 135 opp-suspend; 136 }; 137 138 opp-1800000000 { 139 opp-hz = /bits/ 64 <1800000000>; 140 opp-microvolt = <1000000>; 141 opp-supported-hw = <0x8>, <0x3>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 }; 146 147 osc_32k: clock-osc-32k { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <32768>; 151 clock-output-names = "osc_32k"; 152 }; 153 154 osc_24m: clock-osc-24m { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency = <24000000>; 158 clock-output-names = "osc_24m"; 159 }; 160 161 clk_ext1: clock-ext1 { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <133000000>; 165 clock-output-names = "clk_ext1"; 166 }; 167 168 clk_ext2: clock-ext2 { 169 compatible = "fixed-clock"; 170 #clock-cells = <0>; 171 clock-frequency = <133000000>; 172 clock-output-names = "clk_ext2"; 173 }; 174 175 clk_ext3: clock-ext3 { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <133000000>; 179 clock-output-names = "clk_ext3"; 180 }; 181 182 clk_ext4: clock-ext4 { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency= <133000000>; 186 clock-output-names = "clk_ext4"; 187 }; 188 189 psci { 190 compatible = "arm,psci-1.0"; 191 method = "smc"; 192 }; 193 194 pmu { 195 compatible = "arm,armv8-pmuv3"; 196 interrupts = <GIC_PPI 7 197 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 198 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 199 }; 200 201 timer { 202 compatible = "arm,armv8-timer"; 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 207 clock-frequency = <8000000>; 208 arm,no-tick-in-suspend; 209 }; 210 211 thermal-zones { 212 cpu-thermal { 213 polling-delay-passive = <250>; 214 polling-delay = <2000>; 215 thermal-sensors = <&tmu>; 216 trips { 217 cpu_alert0: trip0 { 218 temperature = <85000>; 219 hysteresis = <2000>; 220 type = "passive"; 221 }; 222 223 cpu_crit0: trip1 { 224 temperature = <95000>; 225 hysteresis = <2000>; 226 type = "critical"; 227 }; 228 }; 229 230 cooling-maps { 231 map0 { 232 trip = <&cpu_alert0>; 233 cooling-device = 234 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 235 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 237 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 238 }; 239 }; 240 }; 241 }; 242 243 usbphynop1: usbphynop1 { 244 compatible = "usb-nop-xceiv"; 245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 248 clock-names = "main_clk"; 249 }; 250 251 usbphynop2: usbphynop2 { 252 compatible = "usb-nop-xceiv"; 253 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 254 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 255 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 256 clock-names = "main_clk"; 257 }; 258 259 soc@0 { 260 compatible = "simple-bus"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0x0 0x0 0x0 0x3e000000>; 264 265 aips1: bus@30000000 { 266 compatible = "fsl,aips-bus", "simple-bus"; 267 reg = <0x30000000 0x400000>; 268 #address-cells = <1>; 269 #size-cells = <1>; 270 ranges = <0x30000000 0x30000000 0x400000>; 271 272 sai1: sai@30010000 { 273 #sound-dai-cells = <0>; 274 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 275 reg = <0x30010000 0x10000>; 276 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 278 <&clk IMX8MM_CLK_SAI1_ROOT>, 279 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 280 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 281 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 282 dma-names = "rx", "tx"; 283 status = "disabled"; 284 }; 285 286 sai2: sai@30020000 { 287 #sound-dai-cells = <0>; 288 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 289 reg = <0x30020000 0x10000>; 290 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 292 <&clk IMX8MM_CLK_SAI2_ROOT>, 293 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 294 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 295 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 296 dma-names = "rx", "tx"; 297 status = "disabled"; 298 }; 299 300 sai3: sai@30030000 { 301 #sound-dai-cells = <0>; 302 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 303 reg = <0x30030000 0x10000>; 304 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 306 <&clk IMX8MM_CLK_SAI3_ROOT>, 307 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 308 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 309 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 310 dma-names = "rx", "tx"; 311 status = "disabled"; 312 }; 313 314 sai5: sai@30050000 { 315 #sound-dai-cells = <0>; 316 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 317 reg = <0x30050000 0x10000>; 318 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 320 <&clk IMX8MM_CLK_SAI5_ROOT>, 321 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 322 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 323 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 324 dma-names = "rx", "tx"; 325 status = "disabled"; 326 }; 327 328 sai6: sai@30060000 { 329 #sound-dai-cells = <0>; 330 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 331 reg = <0x30060000 0x10000>; 332 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 334 <&clk IMX8MM_CLK_SAI6_ROOT>, 335 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 336 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 337 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 342 gpio1: gpio@30200000 { 343 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 344 reg = <0x30200000 0x10000>; 345 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 gpio-ranges = <&iomuxc 0 10 30>; 353 }; 354 355 gpio2: gpio@30210000 { 356 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 357 reg = <0x30210000 0x10000>; 358 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 gpio-ranges = <&iomuxc 0 40 21>; 366 }; 367 368 gpio3: gpio@30220000 { 369 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 370 reg = <0x30220000 0x10000>; 371 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 gpio-ranges = <&iomuxc 0 61 26>; 379 }; 380 381 gpio4: gpio@30230000 { 382 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 383 reg = <0x30230000 0x10000>; 384 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 gpio-ranges = <&iomuxc 0 87 32>; 392 }; 393 394 gpio5: gpio@30240000 { 395 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 396 reg = <0x30240000 0x10000>; 397 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 gpio-ranges = <&iomuxc 0 119 30>; 405 }; 406 407 tmu: tmu@30260000 { 408 compatible = "fsl,imx8mm-tmu"; 409 reg = <0x30260000 0x10000>; 410 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 411 #thermal-sensor-cells = <0>; 412 }; 413 414 wdog1: watchdog@30280000 { 415 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 416 reg = <0x30280000 0x10000>; 417 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 419 status = "disabled"; 420 }; 421 422 wdog2: watchdog@30290000 { 423 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 424 reg = <0x30290000 0x10000>; 425 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 427 status = "disabled"; 428 }; 429 430 wdog3: watchdog@302a0000 { 431 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 432 reg = <0x302a0000 0x10000>; 433 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 435 status = "disabled"; 436 }; 437 438 sdma2: dma-controller@302c0000 { 439 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 440 reg = <0x302c0000 0x10000>; 441 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 443 <&clk IMX8MM_CLK_SDMA2_ROOT>; 444 clock-names = "ipg", "ahb"; 445 #dma-cells = <3>; 446 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 447 }; 448 449 sdma3: dma-controller@302b0000 { 450 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 451 reg = <0x302b0000 0x10000>; 452 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 454 <&clk IMX8MM_CLK_SDMA3_ROOT>; 455 clock-names = "ipg", "ahb"; 456 #dma-cells = <3>; 457 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 458 }; 459 460 iomuxc: pinctrl@30330000 { 461 compatible = "fsl,imx8mm-iomuxc"; 462 reg = <0x30330000 0x10000>; 463 }; 464 465 gpr: iomuxc-gpr@30340000 { 466 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 467 reg = <0x30340000 0x10000>; 468 }; 469 470 ocotp: efuse@30350000 { 471 compatible = "fsl,imx8mm-ocotp", "syscon"; 472 reg = <0x30350000 0x10000>; 473 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 474 /* For nvmem subnodes */ 475 #address-cells = <1>; 476 #size-cells = <1>; 477 478 cpu_speed_grade: speed-grade@10 { 479 reg = <0x10 4>; 480 }; 481 }; 482 483 anatop: anatop@30360000 { 484 compatible = "fsl,imx8mm-anatop", "syscon"; 485 reg = <0x30360000 0x10000>; 486 }; 487 488 snvs: snvs@30370000 { 489 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 490 reg = <0x30370000 0x10000>; 491 492 snvs_rtc: snvs-rtc-lp { 493 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 494 regmap = <&snvs>; 495 offset = <0x34>; 496 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 499 clock-names = "snvs-rtc"; 500 }; 501 502 snvs_pwrkey: snvs-powerkey { 503 compatible = "fsl,sec-v4.0-pwrkey"; 504 regmap = <&snvs>; 505 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 507 clock-names = "snvs-pwrkey"; 508 linux,keycode = <KEY_POWER>; 509 wakeup-source; 510 status = "disabled"; 511 }; 512 }; 513 514 clk: clock-controller@30380000 { 515 compatible = "fsl,imx8mm-ccm"; 516 reg = <0x30380000 0x10000>; 517 #clock-cells = <1>; 518 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 519 <&clk_ext3>, <&clk_ext4>; 520 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 521 "clk_ext3", "clk_ext4"; 522 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 523 <&clk IMX8MM_CLK_A53_CORE>, 524 <&clk IMX8MM_CLK_NOC>, 525 <&clk IMX8MM_CLK_AUDIO_AHB>, 526 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 527 <&clk IMX8MM_SYS_PLL3>, 528 <&clk IMX8MM_VIDEO_PLL1>, 529 <&clk IMX8MM_AUDIO_PLL1>, 530 <&clk IMX8MM_AUDIO_PLL2>; 531 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 532 <&clk IMX8MM_ARM_PLL_OUT>, 533 <&clk IMX8MM_SYS_PLL3_OUT>, 534 <&clk IMX8MM_SYS_PLL1_800M>; 535 assigned-clock-rates = <0>, <0>, <0>, 536 <400000000>, 537 <400000000>, 538 <750000000>, 539 <594000000>, 540 <393216000>, 541 <361267200>; 542 }; 543 544 src: reset-controller@30390000 { 545 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 546 reg = <0x30390000 0x10000>; 547 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 548 #reset-cells = <1>; 549 }; 550 }; 551 552 aips2: bus@30400000 { 553 compatible = "fsl,aips-bus", "simple-bus"; 554 reg = <0x30400000 0x400000>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges = <0x30400000 0x30400000 0x400000>; 558 559 pwm1: pwm@30660000 { 560 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 561 reg = <0x30660000 0x10000>; 562 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 564 <&clk IMX8MM_CLK_PWM1_ROOT>; 565 clock-names = "ipg", "per"; 566 #pwm-cells = <2>; 567 status = "disabled"; 568 }; 569 570 pwm2: pwm@30670000 { 571 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 572 reg = <0x30670000 0x10000>; 573 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 575 <&clk IMX8MM_CLK_PWM2_ROOT>; 576 clock-names = "ipg", "per"; 577 #pwm-cells = <2>; 578 status = "disabled"; 579 }; 580 581 pwm3: pwm@30680000 { 582 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 583 reg = <0x30680000 0x10000>; 584 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 586 <&clk IMX8MM_CLK_PWM3_ROOT>; 587 clock-names = "ipg", "per"; 588 #pwm-cells = <2>; 589 status = "disabled"; 590 }; 591 592 pwm4: pwm@30690000 { 593 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 594 reg = <0x30690000 0x10000>; 595 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 597 <&clk IMX8MM_CLK_PWM4_ROOT>; 598 clock-names = "ipg", "per"; 599 #pwm-cells = <2>; 600 status = "disabled"; 601 }; 602 603 system_counter: timer@306a0000 { 604 compatible = "nxp,sysctr-timer"; 605 reg = <0x306a0000 0x20000>; 606 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&osc_24m>; 608 clock-names = "per"; 609 }; 610 }; 611 612 aips3: bus@30800000 { 613 compatible = "fsl,aips-bus", "simple-bus"; 614 reg = <0x30800000 0x400000>; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 ranges = <0x30800000 0x30800000 0x400000>, 618 <0x8000000 0x8000000 0x10000000>; 619 620 ecspi1: spi@30820000 { 621 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <0x30820000 0x10000>; 625 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 627 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 628 clock-names = "ipg", "per"; 629 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 630 dma-names = "rx", "tx"; 631 status = "disabled"; 632 }; 633 634 ecspi2: spi@30830000 { 635 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 reg = <0x30830000 0x10000>; 639 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 641 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 642 clock-names = "ipg", "per"; 643 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 644 dma-names = "rx", "tx"; 645 status = "disabled"; 646 }; 647 648 ecspi3: spi@30840000 { 649 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <0x30840000 0x10000>; 653 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 655 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 656 clock-names = "ipg", "per"; 657 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 658 dma-names = "rx", "tx"; 659 status = "disabled"; 660 }; 661 662 uart1: serial@30860000 { 663 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 664 reg = <0x30860000 0x10000>; 665 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 667 <&clk IMX8MM_CLK_UART1_ROOT>; 668 clock-names = "ipg", "per"; 669 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 670 dma-names = "rx", "tx"; 671 status = "disabled"; 672 }; 673 674 uart3: serial@30880000 { 675 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 676 reg = <0x30880000 0x10000>; 677 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 679 <&clk IMX8MM_CLK_UART3_ROOT>; 680 clock-names = "ipg", "per"; 681 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 682 dma-names = "rx", "tx"; 683 status = "disabled"; 684 }; 685 686 uart2: serial@30890000 { 687 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 688 reg = <0x30890000 0x10000>; 689 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 691 <&clk IMX8MM_CLK_UART2_ROOT>; 692 clock-names = "ipg", "per"; 693 status = "disabled"; 694 }; 695 696 crypto: crypto@30900000 { 697 compatible = "fsl,sec-v4.0"; 698 #address-cells = <1>; 699 #size-cells = <1>; 700 reg = <0x30900000 0x40000>; 701 ranges = <0 0x30900000 0x40000>; 702 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clk IMX8MM_CLK_AHB>, 704 <&clk IMX8MM_CLK_IPG_ROOT>; 705 clock-names = "aclk", "ipg"; 706 707 sec_jr0: jr@1000 { 708 compatible = "fsl,sec-v4.0-job-ring"; 709 reg = <0x1000 0x1000>; 710 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 711 }; 712 713 sec_jr1: jr@2000 { 714 compatible = "fsl,sec-v4.0-job-ring"; 715 reg = <0x2000 0x1000>; 716 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 717 }; 718 719 sec_jr2: jr@3000 { 720 compatible = "fsl,sec-v4.0-job-ring"; 721 reg = <0x3000 0x1000>; 722 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 723 }; 724 }; 725 726 i2c1: i2c@30a20000 { 727 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 reg = <0x30a20000 0x10000>; 731 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 733 status = "disabled"; 734 }; 735 736 i2c2: i2c@30a30000 { 737 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 reg = <0x30a30000 0x10000>; 741 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 743 status = "disabled"; 744 }; 745 746 i2c3: i2c@30a40000 { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 750 reg = <0x30a40000 0x10000>; 751 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 753 status = "disabled"; 754 }; 755 756 i2c4: i2c@30a50000 { 757 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 reg = <0x30a50000 0x10000>; 761 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 763 status = "disabled"; 764 }; 765 766 uart4: serial@30a60000 { 767 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 768 reg = <0x30a60000 0x10000>; 769 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 771 <&clk IMX8MM_CLK_UART4_ROOT>; 772 clock-names = "ipg", "per"; 773 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 774 dma-names = "rx", "tx"; 775 status = "disabled"; 776 }; 777 778 mu: mailbox@30aa0000 { 779 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 780 reg = <0x30aa0000 0x10000>; 781 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 783 #mbox-cells = <2>; 784 }; 785 786 usdhc1: mmc@30b40000 { 787 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 788 reg = <0x30b40000 0x10000>; 789 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 791 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 792 <&clk IMX8MM_CLK_USDHC1_ROOT>; 793 clock-names = "ipg", "ahb", "per"; 794 fsl,tuning-start-tap = <20>; 795 fsl,tuning-step= <2>; 796 bus-width = <4>; 797 status = "disabled"; 798 }; 799 800 usdhc2: mmc@30b50000 { 801 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 802 reg = <0x30b50000 0x10000>; 803 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 805 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 806 <&clk IMX8MM_CLK_USDHC2_ROOT>; 807 clock-names = "ipg", "ahb", "per"; 808 fsl,tuning-start-tap = <20>; 809 fsl,tuning-step= <2>; 810 bus-width = <4>; 811 status = "disabled"; 812 }; 813 814 usdhc3: mmc@30b60000 { 815 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 816 reg = <0x30b60000 0x10000>; 817 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 819 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 820 <&clk IMX8MM_CLK_USDHC3_ROOT>; 821 clock-names = "ipg", "ahb", "per"; 822 fsl,tuning-start-tap = <20>; 823 fsl,tuning-step= <2>; 824 bus-width = <4>; 825 status = "disabled"; 826 }; 827 828 flexspi: spi@30bb0000 { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 compatible = "nxp,imx8mm-fspi"; 832 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 833 reg-names = "fspi_base", "fspi_mmap"; 834 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 836 <&clk IMX8MM_CLK_QSPI_ROOT>; 837 clock-names = "fspi", "fspi_en"; 838 status = "disabled"; 839 }; 840 841 sdma1: dma-controller@30bd0000 { 842 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 843 reg = <0x30bd0000 0x10000>; 844 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 846 <&clk IMX8MM_CLK_AHB>; 847 clock-names = "ipg", "ahb"; 848 #dma-cells = <3>; 849 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 850 }; 851 852 fec1: ethernet@30be0000 { 853 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; 854 reg = <0x30be0000 0x10000>; 855 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 860 <&clk IMX8MM_CLK_ENET1_ROOT>, 861 <&clk IMX8MM_CLK_ENET_TIMER>, 862 <&clk IMX8MM_CLK_ENET_REF>, 863 <&clk IMX8MM_CLK_ENET_PHY_REF>; 864 clock-names = "ipg", "ahb", "ptp", 865 "enet_clk_ref", "enet_out"; 866 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 867 <&clk IMX8MM_CLK_ENET_TIMER>, 868 <&clk IMX8MM_CLK_ENET_REF>, 869 <&clk IMX8MM_CLK_ENET_TIMER>; 870 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 871 <&clk IMX8MM_SYS_PLL2_100M>, 872 <&clk IMX8MM_SYS_PLL2_125M>; 873 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 874 fsl,num-tx-queues = <3>; 875 fsl,num-rx-queues = <3>; 876 status = "disabled"; 877 }; 878 879 }; 880 881 aips4: bus@32c00000 { 882 compatible = "fsl,aips-bus", "simple-bus"; 883 reg = <0x32c00000 0x400000>; 884 #address-cells = <1>; 885 #size-cells = <1>; 886 ranges = <0x32c00000 0x32c00000 0x400000>; 887 888 usbotg1: usb@32e40000 { 889 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 890 reg = <0x32e40000 0x200>; 891 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 893 clock-names = "usb1_ctrl_root_clk"; 894 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 895 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 896 fsl,usbphy = <&usbphynop1>; 897 fsl,usbmisc = <&usbmisc1 0>; 898 status = "disabled"; 899 }; 900 901 usbmisc1: usbmisc@32e40200 { 902 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 903 #index-cells = <1>; 904 reg = <0x32e40200 0x200>; 905 }; 906 907 usbotg2: usb@32e50000 { 908 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 909 reg = <0x32e50000 0x200>; 910 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 912 clock-names = "usb1_ctrl_root_clk"; 913 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 914 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 915 fsl,usbphy = <&usbphynop2>; 916 fsl,usbmisc = <&usbmisc2 0>; 917 status = "disabled"; 918 }; 919 920 usbmisc2: usbmisc@32e50200 { 921 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 922 #index-cells = <1>; 923 reg = <0x32e50200 0x200>; 924 }; 925 926 }; 927 928 dma_apbh: dma-controller@33000000 { 929 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 930 reg = <0x33000000 0x2000>; 931 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 936 #dma-cells = <1>; 937 dma-channels = <4>; 938 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 939 }; 940 941 gpmi: nand-controller@33002000{ 942 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 943 #address-cells = <1>; 944 #size-cells = <1>; 945 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 946 reg-names = "gpmi-nand", "bch"; 947 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "bch"; 949 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 950 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 951 clock-names = "gpmi_io", "gpmi_bch_apb"; 952 dmas = <&dma_apbh 0>; 953 dma-names = "rx-tx"; 954 status = "disabled"; 955 }; 956 957 gic: interrupt-controller@38800000 { 958 compatible = "arm,gic-v3"; 959 reg = <0x38800000 0x10000>, /* GIC Dist */ 960 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 961 #interrupt-cells = <3>; 962 interrupt-controller; 963 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 964 }; 965 966 ddrc: memory-controller@3d400000 { 967 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 968 reg = <0x3d400000 0x400000>; 969 clock-names = "core", "pll", "alt", "apb"; 970 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 971 <&clk IMX8MM_DRAM_PLL>, 972 <&clk IMX8MM_CLK_DRAM_ALT>, 973 <&clk IMX8MM_CLK_DRAM_APB>; 974 }; 975 976 ddr-pmu@3d800000 { 977 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 978 reg = <0x3d800000 0x400000>; 979 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 980 }; 981 }; 982}; 983