1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7903 i.MX8MM board"; 17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm"; 18 19 aliases { 20 ethernet0 = &fec1; 21 usb0 = &usbotg1; 22 }; 23 24 chosen { 25 stdout-path = &uart2; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0x0 0x40000000 0 0x80000000>; 31 }; 32 33 gpio-keys { 34 compatible = "gpio-keys"; 35 36 key-user-pb { 37 label = "user_pb"; 38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 39 linux,code = <BTN_0>; 40 }; 41 42 key-user-pb1x { 43 label = "user_pb1x"; 44 linux,code = <BTN_1>; 45 interrupt-parent = <&gsc>; 46 interrupts = <0>; 47 }; 48 49 key-erased { 50 label = "key_erased"; 51 linux,code = <BTN_2>; 52 interrupt-parent = <&gsc>; 53 interrupts = <1>; 54 }; 55 56 key-eeprom-wp { 57 label = "eeprom_wp"; 58 linux,code = <BTN_3>; 59 interrupt-parent = <&gsc>; 60 interrupts = <2>; 61 }; 62 63 switch-hold { 64 label = "switch_hold"; 65 linux,code = <BTN_5>; 66 interrupt-parent = <&gsc>; 67 interrupts = <7>; 68 }; 69 }; 70 71 led-controller { 72 compatible = "gpio-leds"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio_leds>; 75 76 led-0 { 77 function = LED_FUNCTION_STATUS; 78 color = <LED_COLOR_ID_RED>; 79 label = "led01_red"; 80 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 81 default-state = "off"; 82 }; 83 84 led-1 { 85 function = LED_FUNCTION_STATUS; 86 color = <LED_COLOR_ID_GREEN>; 87 label = "led01_grn"; 88 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 89 default-state = "off"; 90 }; 91 92 led-2 { 93 function = LED_FUNCTION_STATUS; 94 color = <LED_COLOR_ID_RED>; 95 label = "led02_red"; 96 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 97 default-state = "off"; 98 }; 99 100 led-3 { 101 function = LED_FUNCTION_STATUS; 102 color = <LED_COLOR_ID_GREEN>; 103 label = "led02_grn"; 104 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 105 default-state = "off"; 106 }; 107 108 led-4 { 109 function = LED_FUNCTION_STATUS; 110 color = <LED_COLOR_ID_RED>; 111 label = "led03_red"; 112 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 113 default-state = "off"; 114 }; 115 116 led-5 { 117 function = LED_FUNCTION_STATUS; 118 color = <LED_COLOR_ID_GREEN>; 119 label = "led03_grn"; 120 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 121 default-state = "off"; 122 }; 123 124 led-6 { 125 function = LED_FUNCTION_STATUS; 126 color = <LED_COLOR_ID_RED>; 127 label = "led04_red"; 128 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 129 default-state = "off"; 130 }; 131 132 led-7 { 133 function = LED_FUNCTION_STATUS; 134 color = <LED_COLOR_ID_GREEN>; 135 label = "led04_grn"; 136 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 137 default-state = "off"; 138 }; 139 140 led-8 { 141 function = LED_FUNCTION_STATUS; 142 color = <LED_COLOR_ID_RED>; 143 label = "led05_red"; 144 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 145 default-state = "off"; 146 }; 147 148 led-9 { 149 function = LED_FUNCTION_STATUS; 150 color = <LED_COLOR_ID_GREEN>; 151 label = "led05_grn"; 152 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 153 default-state = "off"; 154 }; 155 156 led-a { 157 function = LED_FUNCTION_STATUS; 158 color = <LED_COLOR_ID_RED>; 159 label = "led06_red"; 160 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 161 default-state = "off"; 162 }; 163 164 led-b { 165 function = LED_FUNCTION_STATUS; 166 color = <LED_COLOR_ID_GREEN>; 167 label = "led06_grn"; 168 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 169 default-state = "off"; 170 }; 171 }; 172 173 pcie0_refclk: pcie0-refclk { 174 compatible = "fixed-clock"; 175 #clock-cells = <0>; 176 clock-frequency = <100000000>; 177 }; 178 179 reg_3p3v: regulator-3p3v { 180 compatible = "regulator-fixed"; 181 regulator-name = "3P3V"; 182 regulator-min-microvolt = <3300000>; 183 regulator-max-microvolt = <3300000>; 184 regulator-always-on; 185 }; 186}; 187 188&A53_0 { 189 cpu-supply = <&buck2>; 190}; 191 192&A53_1 { 193 cpu-supply = <&buck2>; 194}; 195 196&A53_2 { 197 cpu-supply = <&buck2>; 198}; 199 200&A53_3 { 201 cpu-supply = <&buck2>; 202}; 203 204&ddrc { 205 operating-points-v2 = <&ddrc_opp_table>; 206 207 ddrc_opp_table: opp-table { 208 compatible = "operating-points-v2"; 209 210 opp-25000000 { 211 opp-hz = /bits/ 64 <25000000>; 212 }; 213 214 opp-100000000 { 215 opp-hz = /bits/ 64 <100000000>; 216 }; 217 218 opp-750000000 { 219 opp-hz = /bits/ 64 <750000000>; 220 }; 221 }; 222}; 223 224&fec1 { 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_fec1>; 227 phy-mode = "rgmii-id"; 228 phy-handle = <ðphy0>; 229 local-mac-address = [00 00 00 00 00 00]; 230 status = "okay"; 231 232 mdio { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 236 ethphy0: ethernet-phy@0 { 237 compatible = "ethernet-phy-ieee802.3-c22"; 238 reg = <0>; 239 rx-internal-delay-ps = <2000>; 240 tx-internal-delay-ps = <2500>; 241 }; 242 }; 243}; 244 245&gpio1 { 246 gpio-line-names = "", "", "", "", "", "", "", "", 247 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "", 248 "", "", "", "", "", "", "", "", 249 "", "", "", "", "", "", "", ""; 250}; 251 252&gpio2 { 253 gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "", 254 "dig1_out#", "dig1_in", "", "", "", "", "", "", 255 "", "", "", "", "", "", "", "", 256 "", "", "", "", "", "", "", ""; 257}; 258 259&gpio5 { 260 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#", 261 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "", 262 "", "", "", "", "", "", "", "", 263 "", "", "", "", "", "", "", ""; 264}; 265 266&i2c1 { 267 clock-frequency = <100000>; 268 pinctrl-names = "default", "gpio"; 269 pinctrl-0 = <&pinctrl_i2c1>; 270 pinctrl-1 = <&pinctrl_i2c1_gpio>; 271 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 272 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 273 status = "okay"; 274 275 gsc: gsc@20 { 276 compatible = "gw,gsc"; 277 reg = <0x20>; 278 pinctrl-0 = <&pinctrl_gsc>; 279 interrupt-parent = <&gpio4>; 280 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 281 interrupt-controller; 282 #interrupt-cells = <1>; 283 284 adc { 285 compatible = "gw,gsc-adc"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 channel@6 { 290 gw,mode = <0>; 291 reg = <0x06>; 292 label = "temp"; 293 }; 294 295 channel@8 { 296 gw,mode = <1>; 297 reg = <0x08>; 298 label = "vdd_bat"; 299 }; 300 301 channel@82 { 302 gw,mode = <2>; 303 reg = <0x82>; 304 label = "vin"; 305 gw,voltage-divider-ohms = <22100 1000>; 306 gw,voltage-offset-microvolt = <700000>; 307 }; 308 309 channel@84 { 310 gw,mode = <2>; 311 reg = <0x84>; 312 label = "vdd_5p0"; 313 gw,voltage-divider-ohms = <10000 10000>; 314 }; 315 316 channel@86 { 317 gw,mode = <2>; 318 reg = <0x86>; 319 label = "vdd_3p3"; 320 gw,voltage-divider-ohms = <10000 10000>; 321 }; 322 323 channel@88 { 324 gw,mode = <2>; 325 reg = <0x88>; 326 label = "vdd_0p9"; 327 }; 328 329 channel@8c { 330 gw,mode = <2>; 331 reg = <0x8c>; 332 label = "vdd_soc"; 333 }; 334 335 channel@8e { 336 gw,mode = <2>; 337 reg = <0x8e>; 338 label = "vdd_arm"; 339 }; 340 341 channel@90 { 342 gw,mode = <2>; 343 reg = <0x90>; 344 label = "vdd_1p8"; 345 }; 346 347 channel@92 { 348 gw,mode = <2>; 349 reg = <0x92>; 350 label = "vdd_dram"; 351 }; 352 353 channel@a2 { 354 gw,mode = <2>; 355 reg = <0xa2>; 356 label = "vdd_gsc"; 357 gw,voltage-divider-ohms = <10000 10000>; 358 }; 359 }; 360 }; 361 362 gpio: gpio@23 { 363 compatible = "nxp,pca9555"; 364 reg = <0x23>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 interrupt-parent = <&gsc>; 368 interrupts = <4>; 369 }; 370 371 eeprom@50 { 372 compatible = "atmel,24c02"; 373 reg = <0x50>; 374 pagesize = <16>; 375 }; 376 377 eeprom@51 { 378 compatible = "atmel,24c02"; 379 reg = <0x51>; 380 pagesize = <16>; 381 }; 382 383 eeprom@52 { 384 compatible = "atmel,24c02"; 385 reg = <0x52>; 386 pagesize = <16>; 387 }; 388 389 eeprom@53 { 390 compatible = "atmel,24c02"; 391 reg = <0x53>; 392 pagesize = <16>; 393 }; 394 395 rtc@68 { 396 compatible = "dallas,ds1672"; 397 reg = <0x68>; 398 }; 399}; 400 401&i2c2 { 402 clock-frequency = <400000>; 403 pinctrl-names = "default", "gpio"; 404 pinctrl-0 = <&pinctrl_i2c2>; 405 pinctrl-1 = <&pinctrl_i2c2_gpio>; 406 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 407 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 408 status = "okay"; 409 410 pmic@4b { 411 compatible = "rohm,bd71847"; 412 reg = <0x4b>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_pmic>; 415 interrupt-parent = <&gpio3>; 416 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 417 rohm,reset-snvs-powered; 418 #clock-cells = <0>; 419 clocks = <&osc_32k 0>; 420 clock-output-names = "clk-32k-out"; 421 422 regulators { 423 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 424 BUCK1 { 425 regulator-name = "buck1"; 426 regulator-min-microvolt = <700000>; 427 regulator-max-microvolt = <1300000>; 428 regulator-boot-on; 429 regulator-always-on; 430 regulator-ramp-delay = <1250>; 431 }; 432 433 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 434 buck2: BUCK2 { 435 regulator-name = "buck2"; 436 regulator-min-microvolt = <700000>; 437 regulator-max-microvolt = <1300000>; 438 regulator-boot-on; 439 regulator-always-on; 440 regulator-ramp-delay = <1250>; 441 rohm,dvs-run-voltage = <1000000>; 442 rohm,dvs-idle-voltage = <900000>; 443 }; 444 445 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 446 BUCK3 { 447 regulator-name = "buck3"; 448 regulator-min-microvolt = <700000>; 449 regulator-max-microvolt = <1350000>; 450 regulator-boot-on; 451 regulator-always-on; 452 }; 453 454 /* vdd_3p3 */ 455 BUCK4 { 456 regulator-name = "buck4"; 457 regulator-min-microvolt = <3000000>; 458 regulator-max-microvolt = <3300000>; 459 regulator-boot-on; 460 regulator-always-on; 461 }; 462 463 /* vdd_1p8 */ 464 BUCK5 { 465 regulator-name = "buck5"; 466 regulator-min-microvolt = <1605000>; 467 regulator-max-microvolt = <1995000>; 468 regulator-boot-on; 469 regulator-always-on; 470 }; 471 472 /* vdd_dram */ 473 BUCK6 { 474 regulator-name = "buck6"; 475 regulator-min-microvolt = <800000>; 476 regulator-max-microvolt = <1400000>; 477 regulator-boot-on; 478 regulator-always-on; 479 }; 480 481 /* nvcc_snvs_1p8 */ 482 LDO1 { 483 regulator-name = "ldo1"; 484 regulator-min-microvolt = <1600000>; 485 regulator-max-microvolt = <1900000>; 486 regulator-boot-on; 487 regulator-always-on; 488 }; 489 490 /* vdd_snvs_0p8 */ 491 LDO2 { 492 regulator-name = "ldo2"; 493 regulator-min-microvolt = <800000>; 494 regulator-max-microvolt = <900000>; 495 regulator-boot-on; 496 regulator-always-on; 497 }; 498 499 /* vdda_1p8 */ 500 LDO3 { 501 regulator-name = "ldo3"; 502 regulator-min-microvolt = <1800000>; 503 regulator-max-microvolt = <3300000>; 504 regulator-boot-on; 505 regulator-always-on; 506 }; 507 508 LDO4 { 509 regulator-name = "ldo4"; 510 regulator-min-microvolt = <900000>; 511 regulator-max-microvolt = <1800000>; 512 regulator-boot-on; 513 regulator-always-on; 514 }; 515 516 LDO6 { 517 regulator-name = "ldo6"; 518 regulator-min-microvolt = <900000>; 519 regulator-max-microvolt = <1800000>; 520 regulator-boot-on; 521 regulator-always-on; 522 }; 523 }; 524 }; 525}; 526 527&i2c3 { 528 clock-frequency = <400000>; 529 pinctrl-names = "default", "gpio"; 530 pinctrl-0 = <&pinctrl_i2c3>; 531 pinctrl-1 = <&pinctrl_i2c3_gpio>; 532 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 533 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 534 status = "okay"; 535 536 accelerometer@19 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_accel>; 539 compatible = "st,lis2de12"; 540 reg = <0x19>; 541 st,drdy-int-pin = <1>; 542 interrupt-parent = <&gpio1>; 543 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 544 interrupt-names = "INT1"; 545 }; 546}; 547 548&pcie_phy { 549 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 550 fsl,clkreq-unsupported; 551 clocks = <&pcie0_refclk>; 552 clock-names = "ref"; 553 status = "okay"; 554}; 555 556&pcie0 { 557 pinctrl-names = "default"; 558 pinctrl-0 = <&pinctrl_pcie0>; 559 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; 560 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 561 <&clk IMX8MM_CLK_PCIE1_AUX>; 562 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 563 <&clk IMX8MM_CLK_PCIE1_CTRL>; 564 assigned-clock-rates = <10000000>, <250000000>; 565 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 566 <&clk IMX8MM_SYS_PLL2_250M>; 567 status = "okay"; 568}; 569 570&pgc_mipi { 571 status = "disabled"; 572}; 573 574/* off-board RS232/RS485/RS422 */ 575&uart1 { 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_uart1>; 578 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 579 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 580 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 581 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 582 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 583 status = "okay"; 584}; 585 586/* console */ 587&uart2 { 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_uart2>; 590 status = "okay"; 591}; 592 593&usbotg1 { 594 dr_mode = "host"; 595 disable-over-current; 596 status = "okay"; 597}; 598 599/* microSD */ 600&usdhc2 { 601 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 602 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 603 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 604 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 605 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 606 bus-width = <4>; 607 vmmc-supply = <®_3p3v>; 608 status = "okay"; 609}; 610 611/* eMMC */ 612&usdhc3 { 613 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 614 pinctrl-0 = <&pinctrl_usdhc3>; 615 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 616 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 617 bus-width = <8>; 618 non-removable; 619 status = "okay"; 620}; 621 622&wdog1 { 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pinctrl_wdog>; 625 fsl,ext-reset-output; 626 status = "okay"; 627}; 628 629&iomuxc { 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pinctrl_hog>; 632 633 pinctrl_hog: hoggrp { 634 fsl,pins = < 635 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */ 636 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */ 637 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ 638 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ 639 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ 640 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */ 641 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */ 642 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ 643 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ 644 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ 645 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */ 646 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */ 647 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ 648 >; 649 }; 650 651 pinctrl_accel: accelgrp { 652 fsl,pins = < 653 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 654 >; 655 }; 656 657 pinctrl_fec1: fec1grp { 658 fsl,pins = < 659 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 660 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 661 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 662 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 663 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 664 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 665 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 666 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 667 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 668 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 669 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 670 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 671 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 672 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 673 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ 674 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ 675 >; 676 }; 677 678 pinctrl_gsc: gscgrp { 679 fsl,pins = < 680 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 681 >; 682 }; 683 684 pinctrl_i2c1: i2c1grp { 685 fsl,pins = < 686 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 687 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 688 >; 689 }; 690 691 pinctrl_i2c1_gpio: i2c1gpiogrp { 692 fsl,pins = < 693 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 694 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 695 >; 696 }; 697 698 pinctrl_i2c2: i2c2grp { 699 fsl,pins = < 700 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 701 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 702 >; 703 }; 704 705 pinctrl_i2c2_gpio: i2c2gpiogrp { 706 fsl,pins = < 707 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 708 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 709 >; 710 }; 711 712 pinctrl_i2c3: i2c3grp { 713 fsl,pins = < 714 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 715 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 716 >; 717 }; 718 719 pinctrl_i2c3_gpio: i2c3gpiogrp { 720 fsl,pins = < 721 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 722 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 723 >; 724 }; 725 726 pinctrl_gpio_leds: gpioledgrp { 727 fsl,pins = < 728 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 729 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 730 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 731 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 732 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 733 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 734 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 735 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 736 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 737 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 738 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 739 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 740 >; 741 }; 742 743 pinctrl_pcie0: pciegrp { 744 fsl,pins = < 745 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 746 >; 747 }; 748 749 pinctrl_pmic: pmicgrp { 750 fsl,pins = < 751 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 752 >; 753 }; 754 755 pinctrl_uart1: uart1grp { 756 fsl,pins = < 757 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 758 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 759 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 760 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 761 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 762 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140 763 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 764 >; 765 }; 766 767 pinctrl_uart2: uart2grp { 768 fsl,pins = < 769 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 770 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 771 >; 772 }; 773 774 pinctrl_usdhc2: usdhc2grp { 775 fsl,pins = < 776 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 777 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 778 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 779 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 780 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 781 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 782 >; 783 }; 784 785 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 786 fsl,pins = < 787 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 788 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 789 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 790 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 791 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 792 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 793 >; 794 }; 795 796 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 797 fsl,pins = < 798 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 799 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 800 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 801 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 802 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 803 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 804 >; 805 }; 806 807 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 808 fsl,pins = < 809 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 810 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 811 >; 812 }; 813 814 pinctrl_usdhc3: usdhc3grp { 815 fsl,pins = < 816 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 817 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 818 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 819 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 820 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 821 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 822 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 823 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 824 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 825 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 826 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 827 >; 828 }; 829 830 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 831 fsl,pins = < 832 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 833 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 834 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 835 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 836 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 837 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 838 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 839 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 840 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 841 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 842 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 843 >; 844 }; 845 846 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 847 fsl,pins = < 848 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 849 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 850 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 851 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 852 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 853 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 854 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 855 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 856 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 857 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 858 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 859 >; 860 }; 861 862 pinctrl_wdog: wdoggrp { 863 fsl,pins = < 864 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 865 >; 866 }; 867}; 868